The
pmc library is an interface to performance monitoring counters available on some CPUs.
The
pmc library can count events on the following CPU families. Each second-level entry describes a performance counter class. A given class may apply to multiple individual CPU models. Each class has one or more counter types. A CPU may have more than one counter of a given type. Refer to the corresponding processor programmer's manual for more information about individual events.
•
ARM
•
Intel i80200 (PMC_CLASS_I80200)
There are two types of counters available in this class:
PMC_TYPE_I80200_CCNT
cycle counter
PMC_TYPE_I80200_PMCx
performance counter
The following events may be counted by a counter of type PMC_TYPE_I80200_CCNT:
The following events may be counted by a counter of type PMC_TYPE_I80200_PMCx:
dcachebufffull-stall-time
dcachebufffull-stall-count
•
i386
•
Intel i586 (PMC_CLASS_I586)
There are two types of counters available in this class:
PMC_TYPE_I586_TSC
cycle counter
PMC_TYPE_I586_PMCx
performance counter
The following events may be counted by a counter of type PMC_TYPE_I586_PMCx:
•
Intel i686 (PMC_CLASS_I686)
There are two types of counters available in this class:
PMC_TYPE_I686_TSC
cycle counter
PMC_TYPE_I686_PMCx
performance counter
The following events may be counted by a counter of type PMC_TYPE_I686_PMCx:
bus-read-for-ownership-self
bus-read-for-ownership-any
ins-stream-retired-packed-scalar
ins-stream-retired-scalar
ins-stream-comp-retired-packed-scalar
ins-stream-comp-retired-scalar
int-cycles-masked-pending
branch-taken-mispred-retired
•
AMD Athlon / K7 (PMC_CLASS_K7)
There are two types of counters available in this class:
PMC_TYPE_K7_TSC
cycle counter
PMC_TYPE_K7_PMCx
performance counter
The following events may be counted by a counter of type PMC_TYPE_K7_PMCx:
l1cache-writeback-invalid
l1cache-writeback-exclusive
l1cache-writeback-modified
branch-taken-miss-retired
branch-indirect-miss-retired
int-cycles-masked-pending
The
pmc library maintains a mapping between event names and the event selector used by the CPU's performance monitoring hardware. The mapping is described by the following structure:
struct pmc_event {
const char *name;
pmc_evid_t val;
};
The
pmc_configure_counter() function configures the counter
ctr to count the event
evname. The initial value of the counter will be set to
reset_val, and this value will be loaded back into the counter each time it overflows. There are currently no flags defined for the
flags argument.
The
pmc_start_counter() function enables counting on counter
ctr.
The
pmc_stop_counter() function disables counting on counter
ctr.
The
pmc_get_num_counters() function returns the number of counters present in the CPU.
The
pmc_get_counter_class() function returns the counter class of the CPU.
The
pmc_get_counter_type() function places the counter type of counter
ctr into
*typep.
The
pmc_get_counter_value() function places the total number of events counted by counter
ctr into
*valp.
The
pmc_get_accumulated_counter_value() function places the total number of events counted for the current process and all of its children by counter
ctr into
*valp.
The
pmc_get_counter_class_name() function returns the name of the counter class
classval.
The
pmc_get_counter_type_name() function returns the name of the counter type
type.
The
pmc_get_counter_event_name() function returns the name of the event
event for the current CPU's performance counter class.
The
pmc_get_counter_event_list() function returns an array of
pmc_event structures, listing the supported event types for the CPU. The array is terminated by and entry who's
name member is NULL.