patch-2.4.7 linux/drivers/net/sk98lin/h/xmac_ii.h

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diff -u --recursive --new-file v2.4.6/linux/drivers/net/sk98lin/h/xmac_ii.h linux/drivers/net/sk98lin/h/xmac_ii.h
@@ -2,16 +2,15 @@
  *
  * Name:	xmac_ii.h
  * Project:	GEnesis, PCI Gigabit Ethernet Adapter
- * Version:	$Revision: 1.27 $
- * Date:	$Date: 2000/05/17 11:00:46 $
+ * Version:	$Revision: 1.28 $
+ * Date:	$Date: 2000/11/09 12:32:49 $
  * Purpose:	Defines and Macros for XaQti's Gigabit Ethernet Controller
  *
  ******************************************************************************/
 
 /******************************************************************************
  *
- *	(C)Copyright 1998,1999 SysKonnect,
- *	a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *	(C)Copyright 1998-2000 SysKonnect GmbH.
  *
  *	This program is free software; you can redistribute it and/or modify
  *	it under the terms of the GNU General Public License as published by
@@ -27,6 +26,9 @@
  * History:
  *
  *	$Log: xmac_ii.h,v $
+ *	Revision 1.28  2000/11/09 12:32:49  rassmann
+ *	Renamed variables.
+ *	
  *	Revision 1.27  2000/05/17 11:00:46  malthoff
  *	Add bit for enable/disable power management in BCOM chip.
  *	
@@ -145,40 +147,40 @@
  * Note:	NA reg	= Network Address e.g DA, SA etc.
  *
  */
-#define XM_MMU_CMD	0x0000	/* 16 bit r/w	MMU Command Register */
+#define XM_MMU_CMD	0x0000		/* 16 bit r/w	MMU Command Register */
 	/* 0x0004:		reserved */
-#define XM_POFF		0x0008	/* 32 bit r/w	Packet Offset Register */
-#define XM_BURST	0x000c	/* 32 bit r/w	Burst Register for half duplex*/
+#define XM_POFF		0x0008		/* 32 bit r/w	Packet Offset Register */
+#define XM_BURST	0x000c		/* 32 bit r/w	Burst Register for half duplex*/
 #define XM_1L_VLAN_TAG	0x0010	/* 16 bit r/w	One Level VLAN Tag ID */
 #define XM_2L_VLAN_TAG	0x0014	/* 16 bit r/w	Two Level VLAN Tag ID */
 	/* 0x0018 - 0x001e:	reserved */
-#define XM_TX_CMD	0x0020	/* 16 bit r/w	Transmit Command Register */
+#define XM_TX_CMD	0x0020		/* 16 bit r/w	Transmit Command Register */
 #define	XM_TX_RT_LIM	0x0024	/* 16 bit r/w	Transmit Retry Limit Register */
-#define XM_TX_STIME	0x0028	/* 16 bit r/w	Transmit Slottime Register */
-#define XM_TX_IPG	0x002c	/* 16 bit r/w	Transmit Inter Packet Gap */
-#define XM_RX_CMD	0x0030	/* 16 bit r/w	Receive Command Register */
-#define XM_PHY_ADDR	0x0034	/* 16 bit r/w	PHY Address Register */
-#define	XM_PHY_DATA	0x0038	/* 16 bit r/w	PHY Data Register */
+#define XM_TX_STIME	0x0028		/* 16 bit r/w	Transmit Slottime Register */
+#define XM_TX_IPG	0x002c		/* 16 bit r/w	Transmit Inter Packet Gap */
+#define XM_RX_CMD	0x0030		/* 16 bit r/w	Receive Command Register */
+#define XM_PHY_ADDR	0x0034		/* 16 bit r/w	PHY Address Register */
+#define	XM_PHY_DATA	0x0038		/* 16 bit r/w	PHY Data Register */
 	/* 0x003c: 		reserved */
-#define XM_GP_PORT	0x0040	/* 32 bit r/w	General Purpose Port Register */
-#define XM_IMSK		0x0044	/* 16 bit r/w	Interrupt Mask Register */
-#define XM_ISRC		0x0048	/* 16 bit ro	Interrupt Status Register */
-#define XM_HW_CFG	0x004c	/* 16 bit r/w	Hardware Config Register */
+#define XM_GP_PORT	0x0040		/* 32 bit r/w	General Purpose Port Register */
+#define XM_IMSK		0x0044		/* 16 bit r/w	Interrupt Mask Register */
+#define XM_ISRC		0x0048		/* 16 bit ro	Interrupt Status Register */
+#define XM_HW_CFG	0x004c		/* 16 bit r/w	Hardware Config Register */
 	/* 0x0050 - 0x005e:	reserved */
-#define XM_TX_LO_WM	0x0060	/* 16 bit r/w	Tx FIFO Low Water Mark */
-#define XM_TX_HI_WM	0x0062	/* 16 bit r/w	Tx FIFO High Water Mark */
-#define XM_TX_THR	0x0064	/* 16 bit r/w	Tx Request Threshold */
-#define	XM_HT_THR	0x0066	/* 16 bit r/w	Host Request Threshold */
-#define	XM_PAUSE_DA	0x0068	/* NA reg r/w	Pause Destination Address */
+#define XM_TX_LO_WM	0x0060		/* 16 bit r/w	Tx FIFO Low Water Mark */
+#define XM_TX_HI_WM	0x0062		/* 16 bit r/w	Tx FIFO High Water Mark */
+#define XM_TX_THR	0x0064		/* 16 bit r/w	Tx Request Threshold */
+#define	XM_HT_THR	0x0066		/* 16 bit r/w	Host Request Threshold */
+#define	XM_PAUSE_DA	0x0068		/* NA reg r/w	Pause Destination Address */
 	/* 0x006e: 		reserved */
-#define XM_CTL_PARA	0x0070	/* 32 bit r/w	Control Parameter Register */
+#define XM_CTL_PARA	0x0070		/* 32 bit r/w	Control Parameter Register */
 #define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
 #define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
-#define XM_TX_STAT	0x0078	/* 32 bit ro	Tx Status LIFO Register */
+#define XM_TX_STAT	0x0078		/* 32 bit ro	Tx Status LIFO Register */
 
 	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exakt Match Address Registers */
 	/* 				use the XM_EMX() macro to address */
-#define XM_EXM_START	0x0080		/* r/w	Start Address of the EXM Regs */
+#define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */
 
 	/*
 	 * XM_EXM(Reg)
@@ -191,18 +193,18 @@
 	 */
 #define XM_EXM(Reg)	(XM_EXM_START + ((Reg) << 3))
 
-#define XM_SRC_CHK	0x0100	/* NA reg r/w	Source Check Address Register */
-#define XM_SA		0x0108	/* NA reg r/w	Station Address Register */
-#define XM_HSM		0x0110	/* 64 bit r/w	Hash Match Address Registers */
-#define XM_RX_LO_WM	0x0118	/* 16 bit r/w	Receive Low Water Mark */
-#define XM_RX_HI_WM	0x011a	/* 16 bit r/w	Receive High Water Mark */
-#define XM_RX_THR	0x011c	/* 32 bit r/w	Receive Request Threshold */
-#define XM_DEV_ID	0x0120	/* 32 bit ro	Device ID Register */
-#define XM_MODE		0x0124	/* 32 bit r/w	Mode Register */
-#define XM_LSA		0x0128	/* NA reg ro	Last Source Register */
+#define XM_SRC_CHK		0x0100	/* NA reg r/w	Source Check Address Register */
+#define XM_SA			0x0108	/* NA reg r/w	Station Address Register */
+#define XM_HSM			0x0110	/* 64 bit r/w	Hash Match Address Registers */
+#define XM_RX_LO_WM		0x0118	/* 16 bit r/w	Receive Low Water Mark */
+#define XM_RX_HI_WM		0x011a	/* 16 bit r/w	Receive High Water Mark */
+#define XM_RX_THR		0x011c	/* 32 bit r/w	Receive Request Threshold */
+#define XM_DEV_ID		0x0120	/* 32 bit ro	Device ID Register */
+#define XM_MODE			0x0124	/* 32 bit r/w	Mode Register */
+#define XM_LSA			0x0128	/* NA reg ro	Last Source Register */
 	/* 0x012e:		reserved */
-#define XM_TS_READ	0x0130	/* 32 bit ro	TimeStamp Read Regeister */
-#define XM_TS_LOAD	0x0134	/* 32 bit ro	TimeStamp Load Value */
+#define XM_TS_READ		0x0130	/* 32 bit ro	TimeStamp Read Regeister */
+#define XM_TS_LOAD		0x0134	/* 32 bit ro	TimeStamp Load Value */
 	/* 0x0138 - 0x01fe:	reserved */
 #define XM_STAT_CMD	0x0200	/* 16 bit r/w	Statistics Command Register */
 #define	XM_RX_CNT_EV	0x0204	/* 32 bit ro	Rx Counter Event Register */
@@ -210,13 +212,13 @@
 #define XM_RX_EV_MSK	0x020c	/* 32 bit r/w	Rx Counter Event Mask */
 #define XM_TX_EV_MSK	0x0210	/* 32 bit r/w	Tx Counter Event Mask */
 	/* 0x0204 - 0x027e:	reserved */
-#define XM_TXF_OK	0x0280	/* 32 bit ro	Frames Transmitted OK Conuter */
+#define XM_TXF_OK		0x0280	/* 32 bit ro	Frames Transmitted OK Conuter */
 #define XM_TXO_OK_HI	0x0284	/* 32 bit ro	Octets Transmitted OK High Cnt*/
 #define XM_TXO_OK_LO	0x0288	/* 32 bit ro	Octets Transmitted OK Low Cnt */
 #define XM_TXF_BC_OK	0x028c	/* 32 bit ro	Broadcast Frames Xmitted OK */
 #define XM_TXF_MC_OK	0x0290	/* 32 bit ro	Multicast Frames Xmitted OK */
 #define XM_TXF_UC_OK	0x0294	/* 32 bit ro	Unicast Frames Xmitted OK */
-#define XM_TXF_LONG	0x0298	/* 32 bit ro	Tx Long Frame Counter */
+#define XM_TXF_LONG		0x0298	/* 32 bit ro	Tx Long Frame Counter */
 #define XM_TXE_BURST	0x029c	/* 32 bit ro	Tx Burst Event Counter */
 #define XM_TXF_MPAUSE	0x02a0	/* 32 bit ro	Tx Pause MAC Ctrl Frame Cnt */
 #define XM_TXF_MCTRL	0x02a4	/* 32 bit ro	Tx MAC Ctrl Frame Counter */
@@ -224,20 +226,20 @@
 #define XM_TXF_MUL_COL	0x02ac	/* 32 bit ro	Tx Multiple Collision Counter */
 #define XM_TXF_ABO_COL	0x02b0	/* 32 bit ro	Tx aborted due to Exessive Col*/
 #define XM_TXF_LAT_COL	0x02b4	/* 32 bit ro	Tx Late Collision Counter */
-#define XM_TXF_DEF	0x02b8	/* 32 bit ro	Tx Deferred Frame Counter */
+#define XM_TXF_DEF		0x02b8	/* 32 bit ro	Tx Deferred Frame Counter */
 #define XM_TXF_EX_DEF	0x02bc	/* 32 bit ro	Tx Excessive Deferall Counter */
 #define XM_TXE_FIFO_UR	0x02c0	/* 32 bit ro	Tx FIFO Underrun Event Cnt */
 #define XM_TXE_CS_ERR	0x02c4	/* 32 bit ro	Tx Carrier Sence Error Cnt */
-#define XM_TXP_UTIL	0x02c8	/* 32 bit ro	Tx Utilization in % */
+#define XM_TXP_UTIL		0x02c8	/* 32 bit ro	Tx Utilization in % */
 	/* 0x02cc - 0x02ce:	reserved */
-#define XM_TXF_64B	0x02d0	/* 32 bit ro	64 Byte Tx Frame Counter */
-#define XM_TXF_127B	0x02d4	/* 32 bit ro	65-127 Byte Tx Frame Counter */
-#define XM_TXF_255B	0x02d8	/* 32 bit ro	128-255 Byte Tx Frame Counter */
-#define XM_TXF_511B	0x02dc	/* 32 bit ro	256-511 Byte Tx Frame Counter */
+#define XM_TXF_64B		0x02d0	/* 32 bit ro	64 Byte Tx Frame Counter */
+#define XM_TXF_127B		0x02d4	/* 32 bit ro	65-127 Byte Tx Frame Counter */
+#define XM_TXF_255B		0x02d8	/* 32 bit ro	128-255 Byte Tx Frame Counter */
+#define XM_TXF_511B		0x02dc	/* 32 bit ro	256-511 Byte Tx Frame Counter */
 #define XM_TXF_1023B	0x02e0	/* 32 bit ro	512-1023 Byte Tx Frame Counter*/
 #define XM_TXF_MAX_SZ	0x02e4	/* 32 bit ro	1024-MaxSize Byte Tx Frame Cnt*/
 	/* 0x02e8 - 0x02fe:	reserved */
-#define XM_RXF_OK	0x0300	/* 32 bit ro	Frames Received OK */
+#define XM_RXF_OK		0x0300	/* 32 bit ro	Frames Received OK */
 #define XM_RXO_OK_HI	0x0304	/* 32 bit ro	Octets Received OK High Cnt */
 #define XM_RXO_OK_LO	0x0308	/* 32 bit ro	Octets Received OK Low Counter*/
 #define XM_RXF_BC_OK	0x030c	/* 32 bit ro	Broadcast Frames Received OK */
@@ -256,17 +258,17 @@
 #define XM_RXF_LEN_ERR	0x0340	/* 32 bit ro	Rx in Range Length Error */
 #define XM_RXE_SYM_ERR	0x0344	/* 32 bit ro	Rx Symbol Error Counter */
 #define XM_RXE_SHT_ERR	0x0348	/* 32 bit ro	Rx Short Event Error Cnt */
-#define XM_RXE_RUNT	0x034c	/* 32 bit ro	Rx Runt Event Counter */
+#define XM_RXE_RUNT		0x034c	/* 32 bit ro	Rx Runt Event Counter */
 #define XM_RXF_LNG_ERR	0x0350	/* 32 bit ro	Rx Frame too Long Error Cnt */
 #define XM_RXF_FCS_ERR	0x0354	/* 32 bit ro	Rx Frame Check Seq. Error Cnt */
 	/* 0x0358 - 0x035a:	reserved */
 #define XM_RXF_CEX_ERR	0x035c	/* 32 bit ro	Rx Carrier Ext Error Frame Cnt*/
-#define XM_RXP_UTIL	0x0360	/* 32 bit ro	Rx Utilization in % */
+#define XM_RXP_UTIL		0x0360	/* 32 bit ro	Rx Utilization in % */
 	/* 0x0364 - 0x0366:	reserved */
-#define XM_RXF_64B	0x0368	/* 32 bit ro	64 Byte Rx Frame Counter */
-#define XM_RXF_127B	0x036c	/* 32 bit ro	65-127 Byte Rx Frame Counter */
-#define XM_RXF_255B	0x0370	/* 32 bit ro	128-255 Byte Rx Frame Counter */
-#define XM_RXF_511B	0x0374	/* 32 bit ro	256-511 Byte Rx Frame Counter */
+#define XM_RXF_64B		0x0368	/* 32 bit ro	64 Byte Rx Frame Counter */
+#define XM_RXF_127B		0x036c	/* 32 bit ro	65-127 Byte Rx Frame Counter */
+#define XM_RXF_255B		0x0370	/* 32 bit ro	128-255 Byte Rx Frame Counter */
+#define XM_RXF_511B		0x0374	/* 32 bit ro	256-511 Byte Rx Frame Counter */
 #define XM_RXF_1023B	0x0378	/* 32 bit ro	512-1023 Byte Rx Frame Counter*/
 #define XM_RXF_MAX_SZ	0x037c	/* 32 bit ro	1024-MaxSize Byte Rx Frame Cnt*/
 	/* 0x02e8 - 0x02fe:	reserved */
@@ -277,19 +279,19 @@
  * XMAC Bit Definitions
  *
  * If the bit access behaviour differs from the register access behaviour
- * (r/w, ro) this is documented after the bit number. The following bit
+ * (r/w, ro) this is docomented after the bit number. The following bit
  * access behaviours are used:
  *	(sc)	self clearing
  *	(ro)	read only
  */
 
 /*	XM_MMU_CMD	16 bit r/w	MMU Comamnd Register */
-				/* Bit 15..13:	reserved */
+								/* Bit 15..13:	reserved */
 #define XM_MMU_PHY_RDY	(1<<12)	/* Bit 12:	PHY Read Ready */
 #define XM_MMU_PHY_BUSY	(1<<11)	/* Bit 11:	PHY Busy */
 #define XM_MMU_IGN_PF	(1<<10)	/* Bit 10:	Ignore Pause Frame */
 #define XM_MMU_MAC_LB	(1<<9)	/* Bit	9:	Enable MAC Loopback */
-				/* Bit	8:	reserved */
+								/* Bit	8:	reserved */
 #define XM_MMU_FRC_COL	(1<<7)	/* Bit	7:	Force Collision */
 #define XM_MMU_SIM_COL	(1<<6)	/* Bit	6:	Simulate Collision */
 #define XM_MMU_NO_PRE	(1<<5)	/* Bit	5:	No MDIO Preamble */
@@ -301,8 +303,8 @@
 
 
 /*	XM_TX_CMD	16 bit r/w	Transmit Command Register */
-				/* Bit 15..7:	reserved */
-#define XM_TX_BK2BK	(1<<6)	/* Bit	6:	Ignor Carrier Sense (tx Bk2Bk)*/
+								/* Bit 15..7:	reserved */
+#define XM_TX_BK2BK		(1<<6)	/* Bit	6:	Ignor Carrier Sense (tx Bk2Bk)*/
 #define XM_TX_ENC_BYP	(1<<5)	/* Bit	5:	Set Encoder in Bypass Mode */
 #define XM_TX_SAM_LINE	(1<<4)	/* Bit	4: (sc)	Start utilization calculation */
 #define XM_TX_NO_GIG_MD	(1<<3)	/* Bit	3:	Disable Carrier Extension */
@@ -312,28 +314,28 @@
 
 
 /*	XM_TX_RT_LIM	16 bit r/w	Transmit Retry Limit Register */
-				/* Bit 15..5:	reserved */
+								/* Bit 15..5:	reserved */
 #define	XM_RT_LIM_MSK	0x1f	/* Bit	4..0:	Tx Retry Limit */
 
 
 /*	XM_TX_STIME	16 bit r/w	Transmit Slottime Register */
-				/* Bit 15..7:	reserved */
+								/* Bit 15..7:	reserved */
 #define XM_STIME_MSK	0x7f	/* Bit	6..0:	Tx Slottime bits */
 
 
 /*	XM_TX_IPG	16 bit r/w	Transmit Inter Packet Gap */
-				/* Bit 15..8:	reserved */
-#define XM_IPG_MSK	0xff	/* Bit	7..0:	IPG value bits */
+								/* Bit 15..8:	reserved */
+#define XM_IPG_MSK		0xff	/* Bit	7..0:	IPG value bits */
 
 
 /*	XM_RX_CMD	16 bit r/w	Receive Command Register */
-				/* Bit 15..9:	reserved */
+								/* Bit 15..9:	reserved */
 #define XM_RX_LENERR_OK (1<<8)	/* Bit	8	don't set Rx Err bit for */
-				/*		inrange error packets */
+								/*		inrange error packets */
 #define XM_RX_BIG_PK_OK	(1<<7)	/* Bit	7	don't set Rx Err bit for */
-				/*		jumbo packets */
+								/*		jumbo packets */
 #define XM_RX_IPG_CAP	(1<<6)	/* Bit	6	repl. type field with IPG */
-#define XM_RX_TP_MD	(1<<5)	/* Bit	5:	Enable transparent Mode */
+#define XM_RX_TP_MD		(1<<5)	/* Bit	5:	Enable transparent Mode */
 #define XM_RX_STRIP_FCS	(1<<4)	/* Bit	4:	Enable FCS Stripping */
 #define XM_RX_SELF_RX	(1<<3)	/* Bit	3: 	Enable Rx of own packets */
 #define XM_RX_SAM_LINE	(1<<2)	/* Bit	2: (sc)	Start utilization calculation */
@@ -342,24 +344,24 @@
 
 
 /*	XM_PHY_ADDR	16 bit r/w	PHY Address Register */
-				/* Bit 15..5:	reserved */
+								/* Bit 15..5:	reserved */
 #define	XM_PHY_ADDR_SZ	0x1f	/* Bit	4..0:	PHY Address bits */
 
 
 /*	XM_GP_PORT	32 bit r/w	General Purpose Port Register */
-				/* Bit 31..7:	reserved */
-#define	XM_GP_ANIP	(1L<<6)	/* Bit	6: (ro)	Auto Negotiation in Progress */
+								/* Bit 31..7:	reserved */
+#define	XM_GP_ANIP		(1L<<6)	/* Bit	6: (ro)	Auto Negotiation in Progress */
 #define XM_GP_FRC_INT	(1L<<5)	/* Bit	5: (sc)	Force Interrupt */
-				/* Bit	4:	reserved */
+								/* Bit	4:	reserved */
 #define XM_GP_RES_MAC	(1L<<3)	/* Bit	3: (sc)	Reset MAC and FIFOs */
 #define XM_GP_RES_STAT	(1L<<2)	/* Bit	2: (sc)	Reset the statistics module */
-				/* Bit	1:	reserved */
+								/* Bit	1:	reserved */
 #define XM_GP_INP_ASS	(1L<<0)	/* Bit	0: (ro) GP Input Pin asserted */
 
 
 /*	XM_IMSK		16 bit r/w	Interrupt Mask Register */
 /*	XM_ISRC		16 bit ro	Interrupt Status Register */
-				/* Bit 15:	reserved */
+								/* Bit 15:	reserved */
 #define XM_IS_LNK_AE	(1<<14) /* Bit 14:	Link Asynchronous Event */
 #define XM_IS_TX_ABORT	(1<<13) /* Bit 13:	Transmit Abort, late Col. etc */
 #define XM_IS_FRC_INT	(1<<12) /* Bit 12:	Force INT bit set in GP */
@@ -367,7 +369,7 @@
 #define XM_IS_LIPA_RC	(1<<10)	/* Bit 10:	Link Partner requests config */
 #define XM_IS_RX_PAGE	(1<<9)	/* Bit	9:	Page Received */
 #define XM_IS_TX_PAGE	(1<<8)	/* Bit	8:	Next Page Loaded for Transmit */
-#define XM_IS_AND	(1<<7)	/* Bit	7:	Auto Negotiation Done */
+#define XM_IS_AND		(1<<7)	/* Bit	7:	Auto Negotiation Done */
 #define XM_IS_TSC_OV	(1<<6)	/* Bit	6:	Time Stamp Counter Overflow */
 #define XM_IS_RXC_OV	(1<<5)	/* Bit	5:	Rx Counter Event Overflow */
 #define XM_IS_TXC_OV	(1<<4)	/* Bit	4:	Tx Counter Event Overflow */
@@ -377,42 +379,41 @@
 #define XM_IS_RX_COMP	(1<<0)	/* Bit	0:	Frame Rx Complete */
 
 #define XM_DEF_MSK	(~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\
-			XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV |\
-			XM_IS_TXF_UR))
+			XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR))
 
 
 /*	XM_HW_CFG	16 bit r/w	Hardware Config Register */
-				/* Bit 15.. 4:	reserved */
+								/* Bit 15.. 4:	reserved */
 #define	XM_HW_GEN_EOP	(1<<3)	/* Bit	3:	generate End of Packet pulse */
 #define XM_HW_COM4SIG	(1<<2)	/* Bit	2:	use Comma Detect for Sig. Det.*/
-				/* Bit	1:	reserved */
+								/* Bit	1:	reserved */
 #define XM_HW_GMII_MD	(1<<0)	/* Bit	0:	GMII Interface selected */
 
 
 /*	XM_TX_LO_WM	16 bit r/w	Tx FIFO Low Water Mark */
 /*	XM_TX_HI_WM	16 bit r/w	Tx FIFO High Water Mark */
-				/* Bit 15..10	reserved */
+								/* Bit 15..10	reserved */
 #define	XM_TX_WM_MSK	0x01ff	/* Bit	9.. 0	Tx FIFO Watermark bits */
 
 /*	XM_TX_THR	16 bit r/w	Tx Request Threshold */
 /*	XM_HT_THR	16 bit r/w	Host Request Threshold */
 /*	XM_RX_THR	16 bit r/w	Receive Request Threshold */
-				/* Bit 15..11	reserved */
-#define	XM_THR_MSK	0x03ff	/* Bit 10.. 0	Tx FIFO Watermark bits */
+								/* Bit 15..11	reserved */
+#define	XM_THR_MSK		0x03ff	/* Bit 10.. 0	Tx FIFO Watermark bits */
 
 
 /*	XM_TX_STAT	32 bit ro	Tx Status LIFO Register */
-#define XM_ST_VALID	(1UL<<31)	/* Bit 31:	Status Valid */
+#define XM_ST_VALID		(1UL<<31)	/* Bit 31:	Status Valid */
 #define XM_ST_BYTE_CNT	(0x3fffL<<17)	/* Bit 30..17:	Tx frame Length */
 #define XM_ST_RETRY_CNT	(0x1fL<<12)	/* Bit 16..12:	Retry Count */
 #define XM_ST_EX_COL	(1L<<11)	/* Bit 11:	Excessive Collisions */
 #define XM_ST_EX_DEF	(1L<<10)	/* Bit 10:	Excessive Deferral */
-#define XM_ST_BURST	(1L<<9)		/* Bit	9:	p. xmitted in burst md*/
-#define XM_ST_DEFER	(1L<<8)		/* Bit	8:	packet was defered */
-#define XM_ST_BC	(1L<<7)		/* Bit	7:	Broadcast packet */
-#define XM_ST_MC	(1L<<6)		/* Bit	6:	Multicast packet */
-#define XM_ST_UC	(1L<<5)		/* Bit	5:	Unicast packet */
-#define XM_ST_TX_UR	(1L<<4)		/* Bit	4:	FIFO Underrun occurred */
+#define XM_ST_BURST		(1L<<9)		/* Bit	9:	p. xmitted in burst md*/
+#define XM_ST_DEFER		(1L<<8)		/* Bit	8:	packet was defered */
+#define XM_ST_BC		(1L<<7)		/* Bit	7:	Broadcast packet */
+#define XM_ST_MC		(1L<<6)		/* Bit	6:	Multicast packet */
+#define XM_ST_UC		(1L<<5)		/* Bit	5:	Unicast packet */
+#define XM_ST_TX_UR		(1L<<4)		/* Bit	4:	FIFO Underrun occured */
 #define XM_ST_CS_ERR	(1L<<3)		/* Bit	3:	Carrier Sense Error */
 #define XM_ST_LAT_COL	(1L<<2)		/* Bit	2:	Late Collision Error */
 #define XM_ST_MUL_COL	(1L<<1)		/* Bit	1:	Multiple Collisions */
@@ -420,8 +421,8 @@
 
 /*	XM_RX_LO_WM	16 bit r/w	Receive Low Water Mark */
 /*	XM_RX_HI_WM	16 bit r/w	Receive High Water Mark */
-				/* Bit 15..11:	reserved */
-#define	XM_RX_WM_MSK	0x03ff	/* Bit 11.. 0:	Rx FIFO Watermark bits */
+									/* Bit 15..11:	reserved */
+#define	XM_RX_WM_MSK	0x03ff		/* Bit 11.. 0:	Rx FIFO Watermark bits */
 
 
 /*	XM_DEV_ID	32 bit ro	Device ID Register */
@@ -430,25 +431,25 @@
 
 
 /*	XM_MODE		32 bit r/w	Mode Register */
-					/* Bit 31..27:	reserved */
+									/* Bit 31..27:	reserved */
 #define XM_MD_ENA_REJ	(1L<<26)	/* Bit 26:	Enable Frame Reject */
 #define XM_MD_SPOE_E	(1L<<25)	/* Bit 25:	Send Pause on Edge */
-					/* 		extern generated */
+									/* 		extern generated */
 #define XM_MD_TX_REP	(1L<<24)	/* Bit 24:	Transmit Repeater Mode*/
 #define XM_MD_SPOFF_I	(1L<<23)	/* Bit 23:	Send Pause on FIFOfull*/
-					/*		intern generated */
+									/*		intern generated */
 #define XM_MD_LE_STW	(1L<<22)	/* Bit 22:	Rx Stat Word in Lit En*/
 #define XM_MD_TX_CONT	(1L<<21)	/* Bit 21:	Send Continuous */
 #define XM_MD_TX_PAUSE	(1L<<20)	/* Bit 20: (sc)	Send Pause Frame */
-#define XM_MD_ATS	(1L<<19)	/* Bit 19:	Append Time Stamp */
+#define XM_MD_ATS		(1L<<19)	/* Bit 19:	Append Time Stamp */
 #define XM_MD_SPOL_I	(1L<<18)	/* Bit 18:	Send Pause on Low */
-					/*		intern generated */
+									/*		intern generated */
 #define XM_MD_SPOH_I	(1L<<17)	/* Bit 17:	Send Pause on High */
-					/*		intern generated */
-#define XM_MD_CAP	(1L<<16)	/* Bit 16:	Check Address Pair */
+									/*		intern generated */
+#define XM_MD_CAP		(1L<<16)	/* Bit 16:	Check Address Pair */
 #define XM_MD_ENA_HSH	(1L<<15)	/* Bit 15:	Enable Hashing */
-#define XM_MD_CSA	(1L<<14)	/* Bit 14:	Check Station Address */
-#define XM_MD_CAA	(1L<<13)	/* Bit 13:	Check Address Array */
+#define XM_MD_CSA		(1L<<14)	/* Bit 14:	Check Station Address */
+#define XM_MD_CAA		(1L<<13)	/* Bit 13:	Check Address Array */
 #define XM_MD_RX_MCTRL	(1L<<12)	/* Bit 12:	Rx MAC Control Frames */
 #define XM_MD_RX_RUNT	(1L<<11)	/* Bit 11:	Rx Runt Frames */
 #define XM_MD_RX_IRLE	(1L<<10)	/* Bit 10:	Rx in Range Len Err F */
@@ -460,16 +461,15 @@
 #define XM_MD_DIS_BC	(1L<<4)		/* Bit	4:	Disable Rx Boradcast */
 #define XM_MD_ENA_PROM	(1L<<3)		/* Bit	3:	Enable Promiscuous */
 #define XM_MD_ENA_BE	(1L<<2)		/* Bit	2:	Enable Big Endian */
-#define XM_MD_FTF	(1L<<1)		/* Bit	1: (sc)	Flush Tx FIFO */
-#define XM_MD_FRF	(1L<<0)		/* Bit	0: (sc)	Flush Rx FIFO */
+#define XM_MD_FTF		(1L<<1)		/* Bit	1: (sc)	Flush Tx FIFO */
+#define XM_MD_FRF		(1L<<0)		/* Bit	0: (sc)	Flush Rx FIFO */
 
 #define	XM_PAUSE_MODE	(XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
 #define XM_DEF_MODE	(XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
-			 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA |\
-			 XM_MD_CAA)
+			 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
 
 /*	XM_STAT_CMD	16 bit r/w	Statistics Command Register */
-				/* Bit 16..6:	reserved */
+								/* Bit 16..6:	reserved */
 #define XM_SC_SNP_RXC	(1<<5)	/* Bit	5: (sc)	Snap Rx Counters */
 #define XM_SC_SNP_TXC	(1<<4)	/* Bit	4: (sc)	Snap Tx Counters */
 #define XM_SC_CP_RXC	(1<<3)	/* Bit	3: 	Copy Rx Counters Continuously */
@@ -482,28 +482,28 @@
 /*	XM_RX_EV_MSK	32 bit r/w	Rx Counter Event Mask */
 #define	XMR_MAX_SZ_OV	(1UL<<31)	/* Bit 31:	1024-MaxSize Rx Cnt Ov*/
 #define XMR_1023B_OV	(1L<<30)	/* Bit 30:	512-1023Byte Rx Cnt Ov*/
-#define XMR_511B_OV	(1L<<29)	/* Bit 29:	256-511 Byte Rx Cnt Ov*/
-#define XMR_255B_OV	(1L<<28)	/* Bit 28:	128-255 Byte Rx Cnt Ov*/
-#define XMR_127B_OV	(1L<<27)	/* Bit 27:	65-127 Byte Rx Cnt Ov */
-#define XMR_64B_OV	(1L<<26)	/* Bit 26:	64 Byte Rx Cnt Ov */
-#define XMR_UTIL_OV	(1L<<25)	/* Bit 25:	Rx Util Cnt Overflow */
-#define XMR_UTIL_UR	(1L<<24)	/* Bit 24:	Rx Util Cnt Underrun */
+#define XMR_511B_OV		(1L<<29)	/* Bit 29:	256-511 Byte Rx Cnt Ov*/
+#define XMR_255B_OV		(1L<<28)	/* Bit 28:	128-255 Byte Rx Cnt Ov*/
+#define XMR_127B_OV		(1L<<27)	/* Bit 27:	65-127 Byte Rx Cnt Ov */
+#define XMR_64B_OV		(1L<<26)	/* Bit 26:	64 Byte Rx Cnt Ov */
+#define XMR_UTIL_OV		(1L<<25)	/* Bit 25:	Rx Util Cnt Overflow */
+#define XMR_UTIL_UR		(1L<<24)	/* Bit 24:	Rx Util Cnt Underrun */
 #define XMR_CEX_ERR_OV	(1L<<23)	/* Bit 23:	CEXT Err Cnt Ov */
-					/* Bit 22:	reserved */
+									/* Bit 22:	reserved */
 #define XMR_FCS_ERR_OV	(1L<<21)	/* Bit 21:	Rx FCS Error Cnt Ov */
 #define XMR_LNG_ERR_OV	(1L<<20)	/* Bit 20:	Rx too Long Err Cnt Ov*/
-#define XMR_RUNT_OV	(1L<<19)	/* Bit 19:	Runt Event Cnt Ov */
+#define XMR_RUNT_OV		(1L<<19)	/* Bit 19:	Runt Event Cnt Ov */
 #define XMR_SHT_ERR_OV	(1L<<18)	/* Bit 18:	Rx Short Ev Err Cnt Ov*/
 #define XMR_SYM_ERR_OV	(1L<<17)	/* Bit 17:	Rx Sym Err Cnt Ov */
-					/* Bit 16:	reserved */
+									/* Bit 16:	reserved */
 #define XMR_CAR_ERR_OV	(1L<<15)	/* Bit 15:	Rx Carr Ev Err Cnt Ov */
 #define XMR_JAB_PKT_OV	(1L<<14)	/* Bit 14:	Rx Jabb Packet Cnt Ov */
-#define XMR_FIFO_OV	(1L<<13)	/* Bit 13:	Rx FIFO Ov Ev Cnt Ov */
+#define XMR_FIFO_OV		(1L<<13)	/* Bit 13:	Rx FIFO Ov Ev Cnt Ov */
 #define XMR_FRA_ERR_OV	(1L<<12)	/* Bit 12:	Rx Framing Err Cnt Ov */
 #define XMR_FMISS_OV	(1L<<11)	/* Bit 11:	Rx Missed Ev Cnt Ov */
-#define XMR_BURST	(1L<<10)	/* Bit 10:	Rx Burst Event Cnt Ov */
-#define XMR_INV_MOC	(1L<<9)		/* Bit	9:	Rx with inv. MAC OC Ov*/
-#define XMR_INV_MP	(1L<<8)		/* Bit	8:	Rx inv Pause Frame Ov */
+#define XMR_BURST		(1L<<10)	/* Bit 10:	Rx Burst Event Cnt Ov */
+#define XMR_INV_MOC		(1L<<9)		/* Bit	9:	Rx with inv. MAC OC Ov*/
+#define XMR_INV_MP		(1L<<8)		/* Bit	8:	Rx inv Pause Frame Ov */
 #define XMR_MCTRL_OV	(1L<<7)		/* Bit	7:	Rx MAC Ctrl-F Cnt Ov */
 #define XMR_MPAUSE_OV	(1L<<6)		/* Bit	6:	Rx Pause MAC Ctrl-F Ov*/
 #define XMR_UC_OK_OV	(1L<<5)		/* Bit	5:	Rx Unicast Frame CntOv*/
@@ -511,39 +511,39 @@
 #define XMR_BC_OK_OV	(1L<<3)		/* Bit	3:	Rx Broadcast Cnt Ov */
 #define XMR_OK_LO_OV	(1L<<2)		/* Bit	2:	Octets Rx OK Low CntOv*/
 #define XMR_OK_HI_OV	(1L<<1)		/* Bit	1:	Octets Rx OK Hi Cnt Ov*/
-#define XMR_OK_OV	(1L<<0)		/* Bit	0:	Frames Received Ok Ov */
+#define XMR_OK_OV		(1L<<0)		/* Bit	0:	Frames Received Ok Ov */
 
 #define XMR_DEF_MSK	0x00000006L	/* all bits excepting 1 and 2 */
 
 /*	XM_TX_CNT_EV	32 bit ro	Tx Counter Event Register */
 /*	XM_TX_EV_MSK	32 bit r/w	Tx Counter Event Mask */
-					/* Bit 31..26:	reserved */
+									/* Bit 31..26:	reserved */
 #define XMT_MAX_SZ_OV	(1L<<25)	/* Bit 25:	1024-MaxSize Tx Cnt Ov*/
 #define XMT_1023B_OV	(1L<<24)	/* Bit 24:	512-1023Byte Tx Cnt Ov*/
-#define XMT_511B_OV	(1L<<23)	/* Bit 23:	256-511 Byte Tx Cnt Ov*/
-#define XMT_255B_OV	(1L<<22)	/* Bit 22:	128-255 Byte Tx Cnt Ov*/
-#define XMT_127B_OV	(1L<<21)	/* Bit 21:	65-127 Byte Tx Cnt Ov */
-#define XMT_64B_OV	(1L<<20)	/* Bit 20:	64 Byte Tx Cnt Ov */
-#define XMT_UTIL_OV	(1L<<19)	/* Bit 19:	Tx Util Cnt Overflow */
-#define XMT_UTIL_UR	(1L<<18)	/* Bit 18:	Tx Util Cnt Underrun */
+#define XMT_511B_OV		(1L<<23)	/* Bit 23:	256-511 Byte Tx Cnt Ov*/
+#define XMT_255B_OV		(1L<<22)	/* Bit 22:	128-255 Byte Tx Cnt Ov*/
+#define XMT_127B_OV		(1L<<21)	/* Bit 21:	65-127 Byte Tx Cnt Ov */
+#define XMT_64B_OV		(1L<<20)	/* Bit 20:	64 Byte Tx Cnt Ov */
+#define XMT_UTIL_OV		(1L<<19)	/* Bit 19:	Tx Util Cnt Overflow */
+#define XMT_UTIL_UR		(1L<<18)	/* Bit 18:	Tx Util Cnt Underrun */
 #define XMT_CS_ERR_OV	(1L<<17)	/* Bit 17:	Tx Carr Sen Err Cnt Ov*/
 #define XMT_FIFO_UR_OV	(1L<<16)	/* Bit 16:	Tx FIFO Ur Ev Cnt Ov */
 #define XMT_EX_DEF_OV	(1L<<15)	/* Bit 15:	Tx Ex Deferall Cnt Ov */
-#define XMT_DEF		(1L<<14)	/* Bit 14:	Tx Deferred Cnt Ov */
+#define XMT_DEF			(1L<<14)	/* Bit 14:	Tx Deferred Cnt Ov */
 #define XMT_LAT_COL_OV	(1L<<13)	/* Bit 13:	Tx Late Col Cnt Ov */
 #define XMT_ABO_COL_OV	(1L<<12)	/* Bit 12:	Tx abo dueto Ex Col Ov*/
 #define XMT_MUL_COL_OV	(1L<<11)	/* Bit 11:	Tx Mult Col Cnt Ov */
-#define XMT_SNG_COL	(1L<<10)	/* Bit 10:	Tx Single Col Cnt Ov */
+#define XMT_SNG_COL		(1L<<10)	/* Bit 10:	Tx Single Col Cnt Ov */
 #define XMT_MCTRL_OV	(1L<<9)		/* Bit	9:	Tx MAC Ctrl Counter Ov*/
-#define XMT_MPAUSE	(1L<<8)		/* Bit	8:	Tx Pause MAC Ctrl-F Ov*/
-#define XMT_BURST	(1L<<7)		/* Bit	7:	Tx Burst Event Cnt Ov */
-#define XMT_LONG	(1L<<6)		/* Bit	6:	Tx Long Frame Cnt Ov */
+#define XMT_MPAUSE		(1L<<8)		/* Bit	8:	Tx Pause MAC Ctrl-F Ov*/
+#define XMT_BURST		(1L<<7)		/* Bit	7:	Tx Burst Event Cnt Ov */
+#define XMT_LONG		(1L<<6)		/* Bit	6:	Tx Long Frame Cnt Ov */
 #define XMT_UC_OK_OV	(1L<<5)		/* Bit	5:	Tx Unicast Cnt Ov */
 #define XMT_MC_OK_OV	(1L<<4)		/* Bit	4:	Tx Multicast Cnt Ov */
 #define XMT_BC_OK_OV	(1L<<3)		/* Bit	3:	Tx Broadcast Cnt Ov */
 #define XMT_OK_LO_OV	(1L<<2)		/* Bit	2:	Octets Tx OK Low CntOv*/
 #define XMT_OK_HI_OV	(1L<<1)		/* Bit	1:	Octets Tx OK Hi Cnt Ov*/
-#define XMT_OK_OV	(1L<<0)		/* Bit	0:	Frames Tx Ok Ov */
+#define XMT_OK_OV		(1L<<0)		/* Bit	0:	Frames Tx Ok Ov */
 
 #define XMT_DEF_MSK	0x00000006L	/* all bits excepting 1 and 2 */
 
@@ -553,10 +553,10 @@
 #define XMR_FS_LEN	(0x3fffUL<<18)	/* Bit 31..18:	Rx Frame Length */
 #define XMR_FS_2L_VLAN	(1L<<17)	/* Bit 17:	tagged wh 2Lev VLAN ID*/
 #define XMR_FS_1L_VLAN	(1L<<16)	/* Bit 16:	tagged wh 1Lev VLAN ID*/
-#define XMR_FS_BC	(1L<<15)	/* Bit 15:	Broadcast Frame */
-#define XMR_FS_MC	(1L<<14)	/* Bit 14:	Multicast Frame */
-#define XMR_FS_UC	(1L<<13)	/* Bit 13:	Unicast Frame */
-					/* Bit 12:	reserved */
+#define XMR_FS_BC		(1L<<15)	/* Bit 15:	Broadcast Frame */
+#define XMR_FS_MC		(1L<<14)	/* Bit 14:	Multicast Frame */
+#define XMR_FS_UC		(1L<<13)	/* Bit 13:	Unicast Frame */
+									/* Bit 12:	reserved */
 #define XMR_FS_BURST	(1L<<11)	/* Bit 11:	Burst Mode */
 #define XMR_FS_CEX_ERR	(1L<<10)	/* Bit 10:	Carrier Ext. Error */
 #define XMR_FS_802_3	(1L<<9)		/* Bit	9:	802.3 Frame */
@@ -564,10 +564,10 @@
 #define XMR_FS_CAR_ERR	(1L<<7)		/* Bit	7:	Carrier Event Error */
 #define XMR_FS_LEN_ERR	(1L<<6)		/* Bit	6:	In-Range Length Error */
 #define XMR_FS_FRA_ERR	(1L<<5)		/* Bit	5:	Framing Error */
-#define XMR_FS_RUNT	(1L<<4)		/* Bit	4:	Runt Error */
+#define XMR_FS_RUNT		(1L<<4)		/* Bit	4:	Runt Error */
 #define XMR_FS_LNG_ERR	(1L<<3)		/* Bit	3:	Gaint Error */
 #define XMR_FS_FCS_ERR	(1L<<2)		/* Bit	2:	Frame Check Sequ Err */
-#define XMR_FS_ERR	(1L<<1)		/* Bit	1:	Frame Error */
+#define XMR_FS_ERR		(1L<<1)		/* Bit	1:	Frame Error */
 #define XMR_FS_MCTRL	(1L<<0)		/* Bit	0:	MAC Control Packet */
 
 /*
@@ -661,8 +661,8 @@
  */
 #define	PHY_NAT_CTRL		0x00	/* 16 bit r/w	PHY Control Register */
 #define	PHY_NAT_STAT		0x01	/* 16 bit r/w	PHY Status Register */
-#define	PHY_NAT_ID0		0x02	/* 16 bit ro	PHY ID0 Register */
-#define	PHY_NAT_ID1		0x03	/* 16 bit ro	PHY ID1 Register */
+#define	PHY_NAT_ID0			0x02	/* 16 bit ro	PHY ID0 Register */
+#define	PHY_NAT_ID1			0x03	/* 16 bit ro	PHY ID1 Register */
 #define	PHY_NAT_AUNE_ADV	0x04	/* 16 bit r/w	Autonegotiation Advertisement */
 #define	PHY_NAT_AUNE_LP		0x05	/* 16 bit ro	Link Partner Ability Reg */
 #define	PHY_NAT_AUNE_EXP	0x06	/* 16 bit ro	Autonegotiation Expansion Reg */
@@ -695,16 +695,16 @@
 /*****	PHY_BCOM_CTRL	16 bit r/w	PHY Control Register *****/
 /*****	PHY_LONE_CTRL	16 bit r/w	PHY Control Register *****/
 #define	PHY_CT_RESET	(1<<15)	/* Bit 15: (sc)	clear all PHY releated regs */
-#define PHY_CT_LOOP	(1<<14)	/* Bit 14:	enable Loopback over PHY */
+#define PHY_CT_LOOP		(1<<14)	/* Bit 14:	enable Loopback over PHY */
 #define PHY_CT_SPS_LSB	(1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
-#define PHY_CT_ANE	(1<<12)	/* Bit 12:	Autonegotiation Enabled */
+#define PHY_CT_ANE		(1<<12)	/* Bit 12:	Autonegotiation Enabled */
 #define PHY_CT_PDOWN	(1<<11)	/* Bit 11: (BC,L1) Power Down Mode */
-#define PHY_CT_ISOL	(1<<10)	/* Bit 10: (BC,L1) Isolate Mode */
+#define PHY_CT_ISOL		(1<<10)	/* Bit 10: (BC,L1) Isolate Mode */
 #define PHY_CT_RE_CFG	(1<<9)	/* Bit	9: (sc) Restart Autonegotiation */
 #define PHY_CT_DUP_MD	(1<<8)	/* Bit	8:	Duplex Mode */
 #define PHY_CT_COL_TST	(1<<7)	/* Bit	7: (BC,L1) Collsion Test enabled */
 #define PHY_CT_SPS_MSB	(1<<6)	/* Bit	6: (BC,L1) Speed select, upper bit */
-				/* Bit	5..0:	reserved */
+								/* Bit	5..0:	reserved */
 
 #define PHY_B_CT_SP1000	(1<<6)	/* Bit  6:	enable speed of 1000 MBit/s */
 #define PHY_B_CT_SP100	(1<<13)	/* Bit 13:	enable speed of  100 MBit/s */
@@ -718,10 +718,10 @@
 /*****	PHY_XMAC_STAT	16 bit r/w	PHY Status Register *****/
 /*****	PHY_BCOM_STAT	16 bit r/w	PHY Status Register *****/
 /*****	PHY_LONE_STAT	16 bit r/w	PHY Status Register *****/
-				/* Bit 15..9:	reserved */
+								/* Bit 15..9:	reserved */
 				/*	(BC/L1) 100/10 MBit/s cap bits ignored*/
 #define PHY_ST_EXT_ST	(1<<8)	/* Bit	8:	Extended Status Present */
-				/* Bit	7:	reserved */
+								/* Bit	7:	reserved */
 #define PHY_ST_PRE_SUB	(1<<6)	/* Bit	6: (BC/L1) preamble suppression */
 #define PHY_ST_AN_OVER	(1<<5)	/* Bit	5:	Autonegotiation Over */
 #define PHY_ST_REM_FLT	(1<<4)	/* Bit	4:	Remode Fault Condition Occured*/
@@ -734,9 +734,9 @@
 /*	PHY_XMAC_ID1		16 bit ro	PHY ID1 Register */
 /*	PHY_BCOM_ID1		16 bit ro	PHY ID1 Register */
 /*	PHY_LONE_ID1		16 bit ro	PHY ID1 Register */
-#define	PHY_I1_OUI	(0x3f<<10)	/* Bit 15..10:	Organiz. Unique ID */
+#define	PHY_I1_OUI		(0x3f<<10)	/* Bit 15..10:	Organiz. Unique ID */
 #define PHY_I1_MOD_NUM	(0x3f<<4)	/* Bit	9.. 4:	Model Number */
-#define PHY_I1_REV	(0x0f<<0)	/* Bit	3.. 0:	Revision Number */
+#define PHY_I1_REV		(0x0f<<0)	/* Bit	3.. 0:	Revision Number */
 
 
 /*****	PHY_XMAC_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
@@ -744,43 +744,43 @@
 #define PHY_AN_NXT_PG	(1<<15)	/* Bit 15:	Request Next Page */
 #define PHY_X_AN_ACK	(1<<14)	/* Bit 14: (ro)	Acknowledge Received */
 #define PHY_X_AN_RFB	(3<<12)	/* Bit 13..12:	Remode Fault Bits */
-				/* Bit 11.. 9:	reserved */
+								/* Bit 11.. 9:	reserved */
 #define PHY_X_AN_PAUSE	(3<<7)	/* Bit	8.. 7:	Pause Bits */
-#define PHY_X_AN_HD	(1<<6)	/* Bit	6:	Half Duplex */
-#define PHY_X_AN_FD	(1<<5)	/* Bit	5:	Full Duplex */
-				/* Bit	4.. 0:	reserved */
+#define PHY_X_AN_HD		(1<<6)	/* Bit	6:	Half Duplex */
+#define PHY_X_AN_FD		(1<<5)	/* Bit	5:	Full Duplex */
+								/* Bit	4.. 0:	reserved */
 
 /*****	PHY_BCOM_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
 /*****	PHY_BCOM_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
-/*	PHY_AN_NXT_PG	(see XMAC) Bit 15:	Request Next Page */
-				/* Bit 14:	reserved */
-#define PHY_B_AN_RF	(1<<13)	/* Bit 13:	Remote Fault */
-				/* Bit 12:	reserved */
+/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
+								/* Bit 14:	reserved */
+#define PHY_B_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
+								/* Bit 12:	reserved */
 #define PHY_B_AN_ASP	(1<<11)	/* Bit 11:	Asymetric Pause */
-#define PHY_B_AN_PC	(1<<10)	/* Bit 10:	Pause Capable */
-				/* Bit	9..5:	100/10 BT cap bits ingnored */
+#define PHY_B_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
+								/* Bit	9..5:	100/10 BT cap bits ingnored */
 #define PHY_B_AN_SEL	(0x1f<<0)/* Bit 4..0:	Selector Field, 00001=Ethernet*/
 
 /*****	PHY_LONE_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
 /*****	PHY_LONE_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
-/*	PHY_AN_NXT_PG	(see XMAC) Bit 15:	Request Next Page */
-				/* Bit 14:	reserved */
-#define PHY_L_AN_RF	(1<<13)	/* Bit 13:	Remote Fault */
-				/* Bit 12:	reserved */
+/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
+								/* Bit 14:	reserved */
+#define PHY_L_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
+								/* Bit 12:	reserved */
 #define PHY_L_AN_ASP	(1<<11)	/* Bit 11:	Asymetric Pause */
-#define PHY_L_AN_PC	(1<<10)	/* Bit 10:	Pause Capable */
-				/* Bit	9..5:	100/10 BT cap bits ingnored */
+#define PHY_L_AN_PC		(1<<10)	/* Bit 10:	Pause Capable */
+								/* Bit	9..5:	100/10 BT cap bits ingnored */
 #define PHY_L_AN_SEL	(0x1f<<0)/* Bit 4..0:	Selector Field, 00001=Ethernet*/
 
 /*****	PHY_NAT_AUNE_ADV	16 bit r/w	Autoneg Advertisement *****/
 /*****	PHY_NAT_AUNE_LP	16 bit ro	Link Partner Ability Reg *****/
-/*	PHY_AN_NXT_PG	(see XMAC) Bit 15:	Request Next Page */
-				/* Bit 14:	reserved */
-#define PHY_N_AN_RF	(1<<13)	/* Bit 13:	Remote Fault */
-				/* Bit 12:	reserved */
+/*	PHY_AN_NXT_PG		(see XMAC) Bit 15:	Request Next Page */
+								/* Bit 14:	reserved */
+#define PHY_N_AN_RF		(1<<13)	/* Bit 13:	Remote Fault */
+								/* Bit 12:	reserved */
 #define PHY_N_AN_100F	(1<<11)	/* Bit 11:	100Base-T2 FD Support */
 #define PHY_N_AN_100H	(1<<10)	/* Bit 10:	100Base-T2 HD Support */
-				/* Bit	9..5:	100/10 BT cap bits ingnored */
+								/* Bit	9..5:	100/10 BT cap bits ingnored */
 #define PHY_N_AN_SEL	(0x1f<<0)/* Bit 4..0:	Selector Field, 00001=Ethernet*/
 
 /* field type definition for PHY_x_AN_SEL */
@@ -791,22 +791,22 @@
 #define PHY_AN_LP_NP	(1<<3)	/* Bit	3:	Link Partner can Next Page */
 #define PHY_AN_LOC_NP	(1<<2)	/* Bit	2:	Local PHY can Next Page */
 #define PHY_AN_RX_PG	(1<<1)	/* Bit	1:	Page Received */
-				/* Bit	0:	reserved */
+								/* Bit	0:	reserved */
 
 /*****	PHY_BCOM_AUNE_EXP	16 bit ro	Autoneg Expansion Reg *****/
-				/* Bit 15..5:	reserved */
+								/* Bit 15..5:	reserved */
 #define PHY_B_AN_PDF	(1<<4)	/* Bit	4:	Parallel Detection Fault */
-/*	PHY_AN_LP_NP	(see XMAC) Bit	3:	Link Partner can Next Page */
-/*	PHY_AN_LOC_NP	(see XMAC) Bit	2:	Local PHY can Next Page */
-/*	PHY_AN_RX_PG	(see XMAC) Bit	1:	Page Received */
+/*	PHY_AN_LP_NP		(see XMAC) Bit	3:	Link Partner can Next Page */
+/*	PHY_AN_LOC_NP		(see XMAC) Bit	2:	Local PHY can Next Page */
+/*	PHY_AN_RX_PG		(see XMAC) Bit	1:	Page Received */
 #define PHY_B_AN_LP_CAP	(1<<0)	/* Bit	0:	Link Partner Autoneg Cap. */ 	
 
 /*****	PHY_LONE_AUNE_EXP	16 bit ro	Autoneg Expansion Reg *****/
-#define PHY_L_AN_BP	(1<<5)	/* Bit	5:	Base Page Indication */
+#define PHY_L_AN_BP		(1<<5)	/* Bit	5:	Base Page Indication */
 #define PHY_L_AN_PDF	(1<<4)	/* Bit	4:	Parallel Detection Fault */
-/*	PHY_AN_LP_NP	(see XMAC) Bit	3:	Link Partner can Next Page */
-/*	PHY_AN_LOC_NP	(see XMAC) Bit	2:	Local PHY can Next Page */
-/*	PHY_AN_RX_PG	(see XMAC) Bit	1:	Page Received */
+/*	PHY_AN_LP_NP		(see XMAC) Bit	3:	Link Partner can Next Page */
+/*	PHY_AN_LOC_NP		(see XMAC) Bit	2:	Local PHY can Next Page */
+/*	PHY_AN_RX_PG		(see XMAC) Bit	1:	Page Received */
 #define PHY_B_AN_LP_CAP	(1<<0)	/* Bit	0:	Link Partner Autoneg Cap. */ 	
 
 
@@ -816,35 +816,35 @@
 /*****	PHY_XMAC_NEPG_LP	16 bit ro	Next Page Link Partner *****/
 /*****	PHY_BCOM_NEPG_LP	16 bit ro	Next Page Link Partner *****/
 /*****	PHY_LONE_NEPG_LP	16 bit ro	Next Page Link Partner *****/
-#define PHY_NP_MORE	(1<<15)	/* Bit 15:	More, Next Pages to follow */
-#define PHY_NP_ACK1	(1<<14)	/* Bit 14: (ro)	Ack 1, for receiving a message*/
+#define PHY_NP_MORE		(1<<15)	/* Bit 15:	More, Next Pages to follow */
+#define PHY_NP_ACK1		(1<<14)	/* Bit 14: (ro)	Ack 1, for receiving a message*/
 #define PHY_NP_MSG_VAL	(1<<13)	/* Bit 13:	Message Page valid */
-#define PHY_NP_ACK2	(1<<12)	/* Bit 12:	Ack 2, comply with msg content*/
-#define PHY_NP_TOG	(1<<11)	/* Bit 11:	Toggle Bit, ensure sync */
-#define PHY_NP_MSG	0x07ff	/* Bit 10..0:	Message from/to Link Partner */
+#define PHY_NP_ACK2		(1<<12)	/* Bit 12:	Ack 2, comply with msg content*/
+#define PHY_NP_TOG		(1<<11)	/* Bit 11:	Toggle Bit, ensure sync */
+#define PHY_NP_MSG		0x07ff	/* Bit 10..0:	Message from/to Link Partner */
 
 /*
  * XMAC-Specific
  */
 /*****	PHY_XMAC_EXT_STAT	16 bit r/w	Extended Status Register *****/
-#define PHY_X_EX_FD	(1<<15)	/* Bit 15:	Device Supports Full Duplex */
-#define PHY_X_EX_HD	(1<<14)	/* Bit 14:	Device Supports Half Duplex */
-				/* Bit 13..0:	reserved */
+#define PHY_X_EX_FD		(1<<15)	/* Bit 15:	Device Supports Full Duplex */
+#define PHY_X_EX_HD		(1<<14)	/* Bit 14:	Device Supports Half Duplex */
+								/* Bit 13..0:	reserved */
 
 /*****	PHY_XMAC_RES_ABI	16 bit ro	PHY Resolved Ability *****/
-				/* Bit 15..9:	reserved */
+								/* Bit 15..9:	reserved */
 #define PHY_X_RS_PAUSE	(3<<7)	/* Bit	8..7:	selected Pause Mode */
-#define PHY_X_RS_HD	(1<<6)	/* Bit	6:	Half Duplex Mode selected */
-#define PHY_X_RS_FD	(1<<5)	/* Bit	5:	Full Duplex Mode selected */
+#define PHY_X_RS_HD		(1<<6)	/* Bit	6:	Half Duplex Mode selected */
+#define PHY_X_RS_FD		(1<<5)	/* Bit	5:	Full Duplex Mode selected */
 #define PHY_X_RS_ABLMIS (1<<4)	/* Bit	4:	duplex or pause cap mismatch */
 #define PHY_X_RS_PAUMIS (1<<3)	/* Bit	3:	pause capability missmatch */
-				/* Bit	2..0:	reserved */
+								/* Bit	2..0:	reserved */
 /*
  * Remote Fault Bits (PHY_X_AN_RFB) encoding
  */
-#define X_RFB_OK	(0<<12)	/* Bit 12..13	No errors, Link OK */
-#define X_RFB_LF	(1<<12)	/* Bit 12..13	Link Failure */
-#define X_RFB_OFF	(2<<12)	/* Bit 12..13	Offline */
+#define X_RFB_OK		(0<<12)	/* Bit 12..13	No errors, Link OK */
+#define X_RFB_LF		(1<<12)	/* Bit 12..13	Link Failure */
+#define X_RFB_OFF		(2<<12)	/* Bit 12..13	Offline */
 #define X_RFB_AN_ERR	(3<<12)	/* Bit 12..13	Autonegotiation Error */
 
 /*
@@ -866,7 +866,7 @@
 #define PHY_B_1000C_RD		(1<<10)	/* Bit	10:	Repeater/DTE */
 #define PHY_B_1000C_AFD		(1<<9)	/* Bit	9:	Advertise Full Duplex */
 #define PHY_B_1000C_AHD		(1<<8)	/* Bit	8:	Advertise Half Duplex */
-					/* Bit	7..0:	reserved */
+									/* Bit	7..0:	reserved */
 
 /***** PHY_BCOM_1000T_STAT	16 bit ro	1000Base-T Status Reg *****/
 #define PHY_B_1000S_MSF		(1<<15)	/* Bit	15:	Master/Slave Fault */
@@ -875,7 +875,7 @@
 #define PHY_B_1000S_RRS		(1<<12)	/* Bit	12:	Remote Receiver Status */
 #define PHY_B_1000S_LP_FD	(1<<11)	/* Bit	11:	Link Partner can FD */
 #define PHY_B_1000S_LP_HD	(1<<10)	/* Bit	10:	Link Partner can HD */
-					/* Bit	9..8:	reserved */
+									/* Bit	9..8:	reserved */
 #define PHY_B_1000S_IEC		(255<<0)/* Bit	7..0:	Idle Error Count */
 
 /*****	PHY_BCOM_EXT_STAT	16 bit ro	Extended Status Register *****/
@@ -883,7 +883,7 @@
 #define PHY_B_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
 #define PHY_B_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
 #define PHY_B_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
-					/* Bit 11..0:	reserved */
+									/* Bit 11..0:	reserved */
 
 /*****	PHY_BCOM_P_EXT_CTRL	16 bit r/w	PHY Extended Control Reg *****/
 #define PHY_B_PEC_MAC_PHY	(1<<15)	/* Bit 15:	10BIT/GMI-Interface */
@@ -892,36 +892,36 @@
 #define PHY_B_PEC_INT_DIS	(1<<12)	/* Bit 12:	Interrupts Disabled */
 #define PHY_B_PEC_F_INT		(1<<11)	/* Bit 11:	Force Interrupt */
 #define PHY_B_PEC_BY_45		(1<<10)	/* Bit 10:	Bypass 4B5B-Decoder */
-#define PHY_B_PEC_BY_SCR	(1<<9)	/* Bit 9:	Bypass Scrambler */
-#define PHY_B_PEC_BY_MLT3	(1<<8)	/* Bit 8:	Bypass MLT3 Encoder */
-#define PHY_B_PEC_BY_RXA	(1<<7)	/* Bit 7:	Bypass Rx Alignm. */
-#define PHY_B_PEC_RES_SCR	(1<<6)	/* Bit 6:	Reset Scrambler */
-#define PHY_B_PEC_EN_LTR	(1<<5)	/* Bit 5:	Ena LED Traffic Mode */
-#define PHY_B_PEC_LED_ON	(1<<4)	/* Bit 4:	Force LED's on */
-#define PHY_B_PEC_LED_OFF	(1<<3)	/* Bit 3:	Force LED's off */
-#define PHY_B_PEC_EX_IPG	(1<<2)	/* Bit 2:	Extend Tx IPG Mode */
-#define PHY_B_PEC_3_LED		(1<<1)	/* Bit 1:	Three Link LED mode */
-#define PHY_B_PEC_HIGH_LA	(1<<0)	/* Bit 0:	GMII Fifo Elasticy */
+#define PHY_B_PEC_BY_SCR	(1<<9)	/* Bit  9:	Bypass Scrambler */
+#define PHY_B_PEC_BY_MLT3	(1<<8)	/* Bit  8:	Bypass MLT3 Encoder */
+#define PHY_B_PEC_BY_RXA	(1<<7)	/* Bit  7:	Bypass Rx Alignm. */
+#define PHY_B_PEC_RES_SCR	(1<<6)	/* Bit  6:	Reset Scrambler */
+#define PHY_B_PEC_EN_LTR	(1<<5)	/* Bit  5:	Ena LED Traffic Mode */
+#define PHY_B_PEC_LED_ON	(1<<4)	/* Bit  4:	Force LED's on */
+#define PHY_B_PEC_LED_OFF	(1<<3)	/* Bit  3:	Force LED's off */
+#define PHY_B_PEC_EX_IPG	(1<<2)	/* Bit  2:	Extend Tx IPG Mode */
+#define PHY_B_PEC_3_LED		(1<<1)	/* Bit  1:	Three Link LED mode */
+#define PHY_B_PEC_HIGH_LA	(1<<0)	/* Bit  0:	GMII Fifo Elasticy */
 
 /*****	PHY_BCOM_P_EXT_STAT	16 bit ro	PHY Extended Status Reg *****/
-					/* Bit 15..14:	reserved */
+									/* Bit 15..14:	reserved */
 #define PHY_B_PES_CROSS_STAT	(1<<13)	/* Bit 13:	MDI Crossover Status */
 #define PHY_B_PES_INT_STAT	(1<<12)	/* Bit 12:	Interrupt Status */
 #define PHY_B_PES_RRS		(1<<11)	/* Bit 11:	Remote Receiver Stat. */
 #define PHY_B_PES_LRS		(1<<10)	/* Bit 10:	Local Receiver Stat. */
-#define PHY_B_PES_LOCKED	(1<<9)	/* Bit 9:	Locked */
-#define PHY_B_PES_LS		(1<<8)	/* Bit 8:	Link Status */
-#define PHY_B_PES_RF		(1<<7)	/* Bit 7:	Remote Fault */
-#define PHY_B_PES_CE_ER		(1<<6)	/* Bit 6:	Carrier Ext Error */
-#define PHY_B_PES_BAD_SSD	(1<<5)	/* Bit 5:	Bad SSD */
-#define PHY_B_PES_BAD_ESD	(1<<4)	/* Bit 4:	Bad ESD */
-#define PHY_B_PES_RX_ER		(1<<3)	/* Bit 3:	Receive Error */
-#define PHY_B_PES_TX_ER		(1<<2)	/* Bit 2:	Transmit Error */
-#define PHY_B_PES_LOCK_ER	(1<<1)	/* Bit 1:	Lock Error */
-#define PHY_B_PES_MLT3_ER	(1<<0)	/* Bit 0:	MLT3 code Error */
+#define PHY_B_PES_LOCKED	(1<<9)	/* Bit  9:	Locked */
+#define PHY_B_PES_LS		(1<<8)	/* Bit  8:	Link Status */
+#define PHY_B_PES_RF		(1<<7)	/* Bit  7:	Remote Fault */
+#define PHY_B_PES_CE_ER		(1<<6)	/* Bit  6:	Carrier Ext Error */
+#define PHY_B_PES_BAD_SSD	(1<<5)	/* Bit  5:	Bad SSD */
+#define PHY_B_PES_BAD_ESD	(1<<4)	/* Bit  4:	Bad ESD */
+#define PHY_B_PES_RX_ER		(1<<3)	/* Bit  3:	Receive Error */
+#define PHY_B_PES_TX_ER		(1<<2)	/* Bit  2:	Transmit Error */
+#define PHY_B_PES_LOCK_ER	(1<<1)	/* Bit  1:	Lock Error */
+#define PHY_B_PES_MLT3_ER	(1<<0)	/* Bit  0:	MLT3 code Error */
 
 /*****	PHY_BCOM_FC_CTR		16 bit r/w	False Carrier Counter *****/
-					/* Bit 15..8:	reserved */
+									/* Bit 15..8:	reserved */
 #define PHY_B_FC_CTR		(255<<0)/* Bit 7..0:	False Carrier Counter */
 
 /*****	PHY_BCOM_RNO_CTR	16 bit r/w	Receive NOT_OK Counter *****/
@@ -932,15 +932,15 @@
 #define PHY_B_AC_L_SQE		(1<<15)	/* Bit 15:	Low Squelch */
 #define PHY_B_AC_LONG_PACK	(1<<14)	/* Bit 14:	Rx Long Packets */
 #define PHY_B_AC_ER_CTRL	(3<<12)	/* Bit 13..12:	Edgerate Control */
-					/* Bit 11:	reserved */
+									/* Bit 11:	reserved */
 #define PHY_B_AC_TX_TST		(1<<10) /* Bit 10:	tx test bit, always 1 */
-					/* Bit  9.. 8:	reserved */
+									/* Bit  9.. 8:	reserved */
 #define PHY_B_AC_DIS_PRF	(1<<7)	/* Bit  7:	dis part resp filter */
-					/* Bit  6:	reserved */
+									/* Bit  6:	reserved */
 #define PHY_B_AC_DIS_PM		(1<<5)	/* Bit  5:	dis power management */
-					/* Bit  4:	reserved */
+									/* Bit  4:	reserved */
 #define PHY_B_AC_DIAG		(1<<3)	/* Bit  3:	Diagnostic Mode */
-					/* Bit  2.. 0:	reserved */
+									/* Bit  2.. 0:	reserved */
 
 /*****	PHY_BCOM_AUX_STAT	16 bit ro	Auxiliary Status Reg *****/
 #define PHY_B_AS_AN_C		(1<<15)	/* Bit 15:	AutoNeg complete */
@@ -949,37 +949,36 @@
 #define PHY_B_AS_ANAB_D		(1<<12)	/* Bit 12:	AN Ability Detect */
 #define PHY_B_AS_NPW		(1<<11)	/* Bit 11:	AN Next Page Wait */
 #define PHY_B_AS_AN_RES		(7<<8)	/* Bit 10..8:	AN HDC */
-#define PHY_B_AS_PDF		(1<<7)	/* Bit 7:	Parallel Detect. Fault*/
-#define PHY_B_AS_RF		(1<<6)	/* Bit 6:	Remote Fault */
-#define PHY_B_AS_ANP_R		(1<<5)	/* Bit 5:	AN Page Received */
-#define PHY_B_AS_LP_ANAB	(1<<4)	/* Bit 4:	LP AN Ability */
-#define PHY_B_AS_LP_NPAB	(1<<3)	/* Bit 3:	LP Next Page Ability */
-#define PHY_B_AS_LS		(1<<2)	/* Bit 2:	Link Status */
-#define PHY_B_AS_PRR		(1<<1)	/* Bit 1:	Pause Resolution-Rx */
-#define PHY_B_AS_PRT		(1<<0)	/* Bit 0:	Pause Resolution-Tx */
+#define PHY_B_AS_PDF		(1<<7)	/* Bit  7:	Parallel Detect. Fault*/
+#define PHY_B_AS_RF			(1<<6)	/* Bit  6:	Remote Fault */
+#define PHY_B_AS_ANP_R		(1<<5)	/* Bit  5:	AN Page Received */
+#define PHY_B_AS_LP_ANAB	(1<<4)	/* Bit  4:	LP AN Ability */
+#define PHY_B_AS_LP_NPAB	(1<<3)	/* Bit  3:	LP Next Page Ability */
+#define PHY_B_AS_LS			(1<<2)	/* Bit  2:	Link Status */
+#define PHY_B_AS_PRR		(1<<1)	/* Bit  1:	Pause Resolution-Rx */
+#define PHY_B_AS_PRT		(1<<0)	/* Bit  0:	Pause Resolution-Tx */
 
 /*****	PHY_BCOM_INT_STAT	16 bit ro	Interrupt Status Reg *****/
 /*****	PHY_BCOM_INT_MASK	16 bit r/w	Interrupt Mask Reg *****/
-					/* Bit 15:	reserved */
+									/* Bit 15:	reserved */
 #define PHY_B_IS_PSE		(1<<14)	/* Bit 14:	Pair Swap Error */
 #define PHY_B_IS_MDXI_SC	(1<<13)	/* Bit 13:	MDIX Status Change */
 #define PHY_B_IS_HCT		(1<<12)	/* Bit 12:	counter above 32k */
-#define PHY_B_IS_LCT		(1<<11)	/* Bit 11:	all counter below 128 */
+#define PHY_B_IS_LCT		(1<<11)	/* Bit 11:	counter above 128 */
 #define PHY_B_IS_AN_PR		(1<<10)	/* Bit 10:	Page Received */
-#define PHY_B_IS_NO_HDCL	(1<<9)	/* Bit 9:	No HCD Link */
-#define PHY_B_IS_NO_HDC		(1<<8)	/* Bit 8:	No HCD */
-#define PHY_B_IS_NEG_USHDC	(1<<7)	/* Bit 7:	Negotiated Unsup. HCD */
-#define PHY_B_IS_SCR_S_ER	(1<<6)	/* Bit 6:	Scrambler Sync Error */
-#define PHY_B_IS_RRS_CHANGE	(1<<5)	/* Bit 5:	Remote Rx Stat Change */
-#define PHY_B_IS_LRS_CHANGE	(1<<4)	/* Bit 4:	Local Rx Stat Change */
-#define PHY_B_IS_DUP_CHANGE	(1<<3)	/* Bit 3:	Duplex Mode Change */
-#define PHY_B_IS_LSP_CHANGE	(1<<2)	/* Bit 2:	Link Speed Change */
-#define PHY_B_IS_LST_CHANGE	(1<<1)	/* Bit 1:	Link Status Changed */
-#define PHY_B_IS_CRC_ER		(1<<0)	/* Bit 0:	CRC Error */
+#define PHY_B_IS_NO_HDCL	(1<<9)	/* Bit  9:	No HCD Link */
+#define PHY_B_IS_NO_HDC		(1<<8)	/* Bit  8:	No HCD */
+#define PHY_B_IS_NEG_USHDC	(1<<7)	/* Bit  7:	Negotiated Unsup. HCD */
+#define PHY_B_IS_SCR_S_ER	(1<<6)	/* Bit  6:	Scrambler Sync Error */
+#define PHY_B_IS_RRS_CHANGE	(1<<5)	/* Bit  5:	Remote Rx Stat Change */
+#define PHY_B_IS_LRS_CHANGE	(1<<4)	/* Bit  4:	Local Rx Stat Change */
+#define PHY_B_IS_DUP_CHANGE	(1<<3)	/* Bit  3:	Duplex Mode Change */
+#define PHY_B_IS_LSP_CHANGE	(1<<2)	/* Bit  2:	Link Speed Change */
+#define PHY_B_IS_LST_CHANGE	(1<<1)	/* Bit  1:	Link Status Changed */
+#define PHY_B_IS_CRC_ER		(1<<0)	/* Bit  0:	CRC Error */
 
 #define PHY_B_DEF_MSK	(~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
 
-
 /*
  * Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding
  */
@@ -1005,7 +1004,7 @@
 #define PHY_L_1000C_RD		(1<<10)	/* Bit	10:	Repeater/DTE */
 #define PHY_L_1000C_AFD		(1<<9)	/* Bit	9:	Advertise Full Duplex */
 #define PHY_L_1000C_AHD		(1<<8)	/* Bit	8:	Advertise Half Duplex */
-					/* Bit	7..0:	reserved */
+									/* Bit	7..0:	reserved */
 
 /*****	PHY_LONE_1000T_STAT	16 bit ro	1000Base-T Status Reg *****/
 #define PHY_L_1000S_MSF		(1<<15)	/* Bit	15:	Master/Slave Fault */
@@ -1014,7 +1013,7 @@
 #define PHY_L_1000S_RRS		(1<<12)	/* Bit	12:	Remote Receiver Status*/
 #define PHY_L_1000S_LP_FD	(1<<11)	/* Bit	11:	Link Partner can FD */
 #define PHY_L_1000S_LP_HD	(1<<10)	/* Bit	10:	Link Partner can HD */
-					/* Bit	9..8:	reserved */
+									/* Bit	9..8:	reserved */
 #define PHY_B_1000S_IEC		(255<<0)/* Bit	7..0:	Idle Error Count */
 
 /*****	PHY_LONE_EXT_STAT	16 bit ro	Extended Status Register *****/
@@ -1022,11 +1021,11 @@
 #define PHY_L_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
 #define PHY_L_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
 #define PHY_L_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
-					/* Bit 11..0:	reserved */
+									/* Bit 11..0:	reserved */
 
 /*****	PHY_LONE_PORT_CFG	16 bit r/w	Port Configuration Reg *****/
 #define PHY_L_PC_REP_MODE	(1<<15)	/* Bit 15:	Repeater Mode */
-					/* Bit 14:	reserved */
+									/* Bit 14:	reserved */
 #define PHY_L_PC_TX_DIS		(1<<13)	/* Bit 13:	Tx output Disabled */
 #define PHY_L_PC_BY_SCR		(1<<12)	/* Bit 12:	Bypass Scrambler */
 #define PHY_L_PC_BY_45		(1<<11)	/* Bit 11:	Bypass 4B5B-Decoder */
@@ -1049,7 +1048,7 @@
 #define PHY_L_QS_COL_STAT	(1<<11)	/* Bit 11:	Collision */
 #define PHY_L_QS_L_STAT		(1<<10)	/* Bit 10:	Link is up */
 #define PHY_L_QS_DUP_MOD	(1<<9)	/* Bit 9:	Full/Half Duplex */
-#define PHY_L_QS_AN		(1<<8)	/* Bit 8:	AutoNeg is On */
+#define PHY_L_QS_AN			(1<<8)	/* Bit 8:	AutoNeg is On */
 #define PHY_L_QS_AN_C		(1<<7)	/* Bit 7:	AN is Complete */
 #define PHY_L_QS_LLE		(7<<4)	/* Bit 6:	Line Length Estim. */
 #define PHY_L_QS_PAUSE		(1<<3)	/* Bit 3:	LP advertised Pause */
@@ -1059,24 +1058,24 @@
 
 /*****	PHY_LONE_INT_ENAB	16 bit r/w	Interrupt Enable Reg *****/
 /*****	PHY_LONE_INT_STAT	16 bit ro	Interrupt Status Reg *****/
-					/* Bit 15..14:	reserved */
+									/* Bit 15..14:	reserved */
 #define PHY_L_IS_AN_F		(1<<13)	/* Bit 13:	Autoneg fault */
-					/* Bit 12:	not described */
+									/* Bit 12:	not described */
 #define PHY_L_IS_CROSS		(1<<11)	/* Bit 11:	Crossover used */
 #define PHY_L_IS_POL		(1<<10)	/* Bit 10:	Polarity correct. used*/
-#define PHY_L_IS_SS		(1<<9)	/* Bit 9:	Smart Speed Downgrade*/
+#define PHY_L_IS_SS			(1<<9)	/* Bit 9:	Smart Speed Downgrade*/
 #define PHY_L_IS_CFULL		(1<<8)	/* Bit 8:	Counter Full */
 #define PHY_L_IS_AN_C		(1<<7)	/* Bit 7:	AutoNeg Complete */
 #define PHY_L_IS_SPEED		(1<<6)	/* Bit 6:	Speed Changed */
 #define PHY_L_IS_DUP		(1<<5)	/* Bit 5:	Duplex Changed */
-#define PHY_L_IS_LS		(1<<4)	/* Bit 4:	Link Status Changed */
+#define PHY_L_IS_LS			(1<<4)	/* Bit 4:	Link Status Changed */
 #define PHY_L_IS_ISOL		(1<<3)	/* Bit 3:	Isolate Occured */
 #define PHY_L_IS_MDINT		(1<<2)	/* Bit 2: (ro)	STAT: MII Int Pending */
 #define PHY_L_IS_INTEN		(1<<1)	/* Bit 1:	ENAB: Enable IRQs */
 #define PHY_L_IS_FORCE		(1<<0)	/* Bit 0:	ENAB: Force Interrupt */
 
-#define PHY_L_DEF_MSK		(PHY_L_IS_LS | PHY_L_IS_ISOL | \
-				PHY_L_IS_INTEN)	/* int. mask */
+/* int. mask */
+#define PHY_L_DEF_MSK		(PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
 
 /*****	PHY_LONE_LED_CFG	16 bit r/w	LED Configuration Reg *****/
 #define PHY_L_LC_LEDC		(3<<14)	/* Bit 15..14:	Col/Blink/On/Off */
@@ -1091,12 +1090,12 @@
 
 /*****	PHY_LONE_PORT_CTRL	16 bit r/w	Port Control Reg *****/
 #define PHY_L_PC_TX_TCLK	(1<<15)	/* Bit 15:	Enable TX_TCLK */
-					/* Bit 14:	reserved */
+									/* Bit 14:	reserved */
 #define PHY_L_PC_ALT_NP		(1<<13)	/* Bit 14:	Alternate Next Page */
 #define PHY_L_PC_GMII_ALT	(1<<12)	/* Bit 13:	Alternate GMII driver */
-					/* Bit 11:	reserved */
+									/* Bit 11:	reserved */
 #define PHY_L_PC_TEN_CRS	(1<<10)	/* Bit 10:	Extend CRS*/
-					/* Bit 9..0:	not described */
+									/* Bit 9..0:	not described */
 
 /*****	PHY_LONE_CIM		16 bit ro	CIM Reg *****/
 #define PHY_L_CIM_ISOL		(255<<8)/* Bit 15..8:	Isolate Count */
@@ -1123,7 +1122,7 @@
 #define PHY_N_1000C_AFD		(1<<9)	/* Bit	9:	Advertise Full Duplex */
 #define PHY_N_1000C_AHD		(1<<8)	/* Bit	8:	Advertise Half Duplex */
 #define PHY_N_1000C_APC		(1<<7)	/* Bit	7:	Asymetric Pause Cap. */
-					/* Bit	6..0:	reserved */
+									/* Bit	6..0:	reserved */
 
 /***** PHY_NAT_1000T_STAT	16 bit ro	1000Base-T Status Reg *****/
 #define PHY_N_1000S_MSF		(1<<15)	/* Bit	15:	Master/Slave Fault */
@@ -1133,7 +1132,7 @@
 #define PHY_N_1000S_LP_FD	(1<<11)	/* Bit	11:	Link Partner can FD */
 #define PHY_N_1000S_LP_HD	(1<<10)	/* Bit	10:	Link Partner can HD */
 #define PHY_N_1000C_LP_APC	(1<<9)	/* Bit	9:	LP Asym. Pause Cap. */
-					/* Bit	8:	reserved */
+									/* Bit	8:	reserved */
 #define PHY_N_1000S_IEC		(255<<0)/* Bit	7..0:	Idle Error Count */
 
 /*****	PHY_NAT_EXT_STAT	16 bit ro	Extended Status Register *****/
@@ -1141,7 +1140,7 @@
 #define PHY_N_ES_X_HD_CAP	(1<<14)	/* Bit 14:	1000Base-X HD capable */
 #define PHY_N_ES_T_FD_CAP	(1<<13)	/* Bit 13:	1000Base-T FD capable */
 #define PHY_N_ES_T_HD_CAP	(1<<12)	/* Bit 12:	1000Base-T HD capable */
-					/* Bit 11..0:	reserved */
+									/* Bit 11..0:	reserved */
 
 /* todo: those are still missing */
 /*****	PHY_NAT_EXT_CTRL1	16 bit ro	Extended Control Reg1 *****/
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)