patch-2.4.7 linux/arch/mips64/mm/r4xx0.c

• Lines: 143
• Date: Wed Jul 4 11:50:39 2001
• Orig file: v2.4.6/linux/arch/mips64/mm/r4xx0.c
• Orig date: Sun Feb 4 21:48:46 2001

diff -u --recursive --new-file v2.4.6/linux/arch/mips64/mm/r4xx0.c linux/arch/mips64/mm/r4xx0.c
@@ -6,7 +6,7 @@
  * r4xx0.c: R4000 processor variant specific MMU/Cache routines.
  *
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1997, 1998, 1999, 2000, 2001 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
 #include <linux/init.h>
@@ -377,7 +377,7 @@
 		"ld\t%3,-8(%1)\n\t"
 		"sd\t%2,-16(%0)\n\t"
 		"bne\t$1,%0,1b\n\t"
-		" sd\t%4,-8(%0)\n\t"
+		" sd\t%3,-8(%0)\n\t"
 		".set\tat\n\t"
 		".set\treorder"
 		:"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2)
@@ -1017,7 +1017,7 @@
 	struct vm_area_struct *vma;
 	unsigned long flags;
 
-	if (CPU_CONTEXT(smp_processor_id(), mm) != 0) {
+	if (CPU_CONTEXT(smp_processor_id(), mm) != 0)
 		return;
 
 	start &= PAGE_MASK;
@@ -1747,15 +1747,15 @@
 	unsigned long end, a;
 	unsigned int flags;
 
-	if (size >= dcache_size) {
+	if (size >= (unsigned long)dcache_size) {
 		flush_cache_l1();
 	} else {
 		/* Workaround for R4600 bug.  See comment above. */
 		__save_and_cli(flags);
 		*(volatile unsigned long *)KSEG1;
 
-		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		a = addr & ~((unsigned long)dc_lsize - 1);
+		end = (addr + size) & ~((unsigned long)dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -1771,13 +1771,13 @@
 {
 	unsigned long end, a;
 
-	if (size >= scache_size) {
+	if (size >= (unsigned long)scache_size) {
 		flush_cache_l1();
 		return;
 	}
 
-	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	a = addr & ~((unsigned long)sc_lsize - 1);
+	end = (addr + size) & ~((unsigned long)sc_lsize - 1);
 	while (1) {
 		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */
 		if (a == end) break;
@@ -1791,15 +1791,15 @@
 	unsigned long end, a;
 	unsigned int flags;
 
-	if (size >= dcache_size) {
+	if (size >= (unsigned long)dcache_size) {
 		flush_cache_l1();
 	} else {
 		/* Workaround for R4600 bug.  See comment above. */
 		__save_and_cli(flags);
 		*(volatile unsigned long *)KSEG1;
 
-		a = addr & ~(dc_lsize - 1);
-		end = (addr + size) & ~(dc_lsize - 1);
+		a = addr & ~((unsigned long)dc_lsize - 1);
+		end = (addr + size) & ~((unsigned long)dc_lsize - 1);
 		while (1) {
 			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
 			if (a == end) break;
@@ -1816,13 +1816,13 @@
 {
 	unsigned long end, a;
 
-	if (size >= scache_size) {
+	if (size >= (unsigned long)scache_size) {
 		flush_cache_l1();
 		return;
 	}
 
-	a = addr & ~(sc_lsize - 1);
-	end = (addr + size) & ~(sc_lsize - 1);
+	a = addr & ~((unsigned long)sc_lsize - 1);
+	end = (addr + size) & ~((unsigned long)sc_lsize - 1);
 	while (1) {
 		flush_scache_line(a); /* Hit_Writeback_Inv_SD */
 		if (a == end) break;
@@ -1845,11 +1845,11 @@
 {
 	unsigned long daddr, iaddr;
 
-	daddr = addr & ~(dc_lsize - 1);
+	daddr = addr & ~((unsigned long)dc_lsize - 1);
 	__asm__ __volatile__("nop;nop;nop;nop");	/* R4600 V1.7 */
 	protected_writeback_dcache_line(daddr);
 	protected_writeback_dcache_line(daddr + dc_lsize);
-	iaddr = addr & ~(ic_lsize - 1);
+	iaddr = addr & ~((unsigned long)ic_lsize - 1);
 	protected_flush_icache_line(iaddr);
 	protected_flush_icache_line(iaddr + ic_lsize);
 }
@@ -1859,7 +1859,7 @@
 	unsigned long daddr, iaddr;
 	unsigned int flags;
 
-	daddr = addr & ~(dc_lsize - 1);
+	daddr = addr & ~((unsigned long)dc_lsize - 1);
 	__save_and_cli(flags);
 
 	/* Clear internal cache refill buffer */
@@ -1867,7 +1867,7 @@
 
 	protected_writeback_dcache_line(daddr);
 	protected_writeback_dcache_line(daddr + dc_lsize);
-	iaddr = addr & ~(ic_lsize - 1);
+	iaddr = addr & ~((unsigned long)ic_lsize - 1);
 	protected_flush_icache_line(iaddr);
 	protected_flush_icache_line(iaddr + ic_lsize);
 	__restore_flags(flags);
@@ -2384,7 +2384,11 @@
 
 	printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
 
+#ifdef CONFIG_MIPS_UNCACHED
+	set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+#else
 	set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
+#endif /* UNCACHED */
 
 	probe_icache(config);
 	probe_dcache(config);