patch-2.4.22 linux-2.4.22/arch/mips/vr41xx/common/giu.c

• Lines: 73
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/mips/vr41xx/common/giu.c
• Orig date: 2002-11-28 15:53:10.000000000 -0800

diff -urN linux-2.4.21/arch/mips/vr41xx/common/giu.c linux-2.4.22/arch/mips/vr41xx/common/giu.c
@@ -89,7 +89,7 @@
 	return res;
 }
 
-void vr41xx_enable_giuint(u8 pin)
+void vr41xx_enable_giuint(int pin)
 {
 	if (pin < 16)
 		set_giuint(GIUINTENL, (u16)1 << pin);
@@ -97,7 +97,7 @@
 		set_giuint(GIUINTENH, (u16)1 << (pin - 16));
 }
 
-void vr41xx_disable_giuint(u8 pin)
+void vr41xx_disable_giuint(int pin)
 {
 	if (pin < 16)
 		clear_giuint(GIUINTENL, (u16)1 << pin);
@@ -105,15 +105,15 @@
 		clear_giuint(GIUINTENH, (u16)1 << (pin - 16));
 }
 
-void vr41xx_clear_giuint(u8 pin)
+void vr41xx_clear_giuint(int pin)
 {
 	if (pin < 16)
-		write_giuint(GIUINTSTATL, (u16)1 << pin);
+		write_giuint((u16)1 << pin, GIUINTSTATL);
 	else
-		write_giuint(GIUINTSTATH, (u16)1 << (pin - 16));
+		write_giuint((u16)1 << (pin - 16), GIUINTSTATH);
 }
 
-void vr41xx_set_irq_trigger(u8 pin, u8 trigger, u8 hold)
+void vr41xx_set_irq_trigger(int pin, int trigger, int hold)
 {
 	u16 mask;
 
@@ -146,7 +146,7 @@
 	vr41xx_clear_giuint(pin);
 }
 
-void vr41xx_set_irq_level(u8 pin, u8 level)
+void vr41xx_set_irq_level(int pin, int level)
 {
 	u16 mask;
 
@@ -167,7 +167,6 @@
 	vr41xx_clear_giuint(pin);
 }
 
-#define GIUINT_CASCADE_IRQ	16
 #define GIUINT_NR_IRQS		32
 
 enum {
@@ -212,8 +211,6 @@
 	return retval;
 }
 
-extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
-
 unsigned int giuint_do_IRQ(int pin, struct pt_regs *regs)
 {
 	struct vr41xx_giuint_cascade *cascade;
@@ -242,7 +239,7 @@
 {
 	int i;
 
-	switch (mips_cpu.cputype) {
+	switch (current_cpu_data.cputype) {
 	case CPU_VR4111:
 	case CPU_VR4121:
 		vr41xx_giu_base = VR4111_GIUIOSELL;