patch-2.4.22 linux-2.4.22/arch/mips/mm/c-r3k.c

• Lines: 215
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/mips/mm/c-r3k.c
• Orig date: 2002-11-28 15:53:10.000000000 -0800

diff -urN linux-2.4.21/arch/mips/mm/c-r3k.c linux-2.4.22/arch/mips/mm/c-r3k.c
@@ -7,6 +7,7 @@
  * Tx39XX R4k style caches added. HK
  * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
+ * Copyright (C) 2001  Maciej W. Rozycki
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -22,6 +23,9 @@
 #include <asm/bootinfo.h>
 #include <asm/cpu.h>
 
+void r3k_clear_page(void * page);
+void r3k_copy_page(void * to, void * from);
+
 static unsigned long icache_size, dcache_size;		/* Size in bytes */
 static unsigned long icache_lsize, dcache_lsize;	/* Size in bytes */
 
@@ -34,14 +38,14 @@
 
 	p = (volatile unsigned long *) KSEG0;
 
-	flags = read_32bit_cp0_register(CP0_STATUS);
+	flags = read_c0_status();
 
 	/* isolate cache space */
-	write_32bit_cp0_register(CP0_STATUS, (ca_flags|flags)&~ST0_IEC);
+	write_c0_status((ca_flags|flags)&~ST0_IEC);
 
 	*p = 0xa5a55a5a;
 	dummy = *p;
-	status = read_32bit_cp0_register(CP0_STATUS);
+	status = read_c0_status();
 
 	if (dummy != 0xa5a55a5a || (status & ST0_CM)) {
 		size = 0;
@@ -57,7 +61,7 @@
 			size = 0;
 	}
 
-	write_32bit_cp0_register(CP0_STATUS, flags);
+	write_c0_status(flags);
 
 	return size * sizeof(*p);
 }
@@ -69,24 +73,24 @@
 
 	p = (volatile unsigned long *) KSEG0;
 
-	flags = read_32bit_cp0_register(CP0_STATUS);
+	flags = read_c0_status();
 
 	/* isolate cache space */
-	write_32bit_cp0_register(CP0_STATUS, (ca_flags|flags)&~ST0_IEC);
+	write_c0_status((ca_flags|flags)&~ST0_IEC);
 
 	for (i = 0; i < 128; i++)
 		*(p + i) = 0;
 	*(volatile unsigned char *)p = 0;
 	for (lsize = 1; lsize < 128; lsize <<= 1) {
 		*(p + lsize);
-		status = read_32bit_cp0_register(CP0_STATUS);
+		status = read_c0_status();
 		if (!(status & ST0_CM))
 			break;
 	}
 	for (i = 0; i < 128; i += lsize)
 		*(volatile unsigned char *)(p + i) = 0;
 
-	write_32bit_cp0_register(CP0_STATUS, flags);
+	write_c0_status(flags);
 
 	return lsize * sizeof(*p);
 }
@@ -97,7 +101,6 @@
 	if (dcache_size)
 		dcache_lsize = r3k_cache_lsize(ST0_ISC);
 
-
 	icache_size = r3k_cache_size(ST0_ISC|ST0_SWC);
 	if (icache_size)
 		icache_lsize = r3k_cache_lsize(ST0_ISC|ST0_SWC);
@@ -115,10 +118,10 @@
 	}
 	p = (char *)start;
 
-	flags = read_32bit_cp0_register(CP0_STATUS);
+	flags = read_c0_status();
 
 	/* isolate cache space */
-	write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
+	write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
 
 	for (i = 0; i < size; i += 0x080) {
 		asm ( 	"sb\t$0, 0x000(%0)\n\t"
@@ -157,7 +160,7 @@
 		p += 0x080;
 	}
 
-	write_32bit_cp0_register(CP0_STATUS, flags);
+	write_c0_status(flags);
 }
 
 static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
@@ -172,10 +175,10 @@
 	}
 	p = (char *)start;
 
-	flags = read_32bit_cp0_register(CP0_STATUS);
+	flags = read_c0_status();
 
 	/* isolate cache space */
-	write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|flags)&~ST0_IEC);
+	write_c0_status((ST0_ISC|flags)&~ST0_IEC);
 
 	for (i = 0; i < size; i += 0x080) {
 		asm ( 	"sb\t$0, 0x000(%0)\n\t"
@@ -214,7 +217,7 @@
 		p += 0x080;
 	}
 
-	write_32bit_cp0_register(CP0_STATUS,flags);
+	write_c0_status(flags);
 }
 
 static inline unsigned long get_phys_page (unsigned long addr,
@@ -241,6 +244,7 @@
 
 static inline void r3k___flush_cache_all(void)
 {
+	r3k_flush_dcache_range(KSEG0, KSEG0 + dcache_size);
 	r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);
 }
 
@@ -258,11 +262,8 @@
 {
 }
 
-static void r3k_flush_page_to_ram(struct page * page)
+static void r3k_flush_data_cache_page(unsigned long addr)
 {
-	/*
-	 * Nothing to be done
-	 */
 }
 
 static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page)
@@ -270,14 +271,14 @@
 	struct mm_struct *mm = vma->vm_mm;
 	unsigned long physpage;
 
-	if (mm->context == 0)
+	if (cpu_context(smp_processor_id(), mm) == 0)
 		return;
 
 	if (!(vma->vm_flags & VM_EXEC))
 		return;
 
 #ifdef DEBUG_CACHE
-	printk("cpage[%d,%08lx]", (int)mm->context, page);
+	printk("cpage[%d,%08lx]", cpu_context(smp_processor_id(), mm), page);
 #endif
 
 	physpage = (unsigned long) page_address(page);
@@ -293,22 +294,22 @@
 	printk("csigtramp[%08lx]", addr);
 #endif
 
-	flags = read_32bit_cp0_register(CP0_STATUS);
+	flags = read_c0_status();
 
-	write_32bit_cp0_register(CP0_STATUS, flags&~ST0_IEC);
+	write_c0_status(flags&~ST0_IEC);
 
 	/* Fill the TLB to avoid an exception with caches isolated. */
 	asm ( 	"lw\t$0, 0x000(%0)\n\t"
 		"lw\t$0, 0x004(%0)\n\t"
 		: : "r" (addr) );
 
-	write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
+	write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
 
 	asm ( 	"sb\t$0, 0x000(%0)\n\t"
 		"sb\t$0, 0x004(%0)\n\t"
 		: : "r" (addr) );
 
-	write_32bit_cp0_register(CP0_STATUS, flags);
+	write_c0_status(flags);
 }
 
 static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
@@ -331,16 +332,16 @@
 	_flush_cache_mm = r3k_flush_cache_mm;
 	_flush_cache_range = r3k_flush_cache_range;
 	_flush_cache_page = r3k_flush_cache_page;
-	_flush_cache_sigtramp = r3k_flush_cache_sigtramp;
-	_flush_page_to_ram = r3k_flush_page_to_ram;
 	_flush_icache_page = r3k_flush_icache_page;
 	_flush_icache_range = r3k_flush_icache_range;
 
-	_dma_cache_wback_inv = r3k_dma_cache_wback_inv;
+	_flush_cache_sigtramp = r3k_flush_cache_sigtramp;
+	_flush_data_cache_page = r3k_flush_data_cache_page;
 
-	printk("Primary instruction cache %dkb, linesize %d bytes\n",
-		(int) (icache_size >> 10), (int) icache_lsize);
-	printk("Primary data cache %dkb, linesize %d bytes\n",
-		(int) (dcache_size >> 10), (int) dcache_lsize);
+	_dma_cache_wback_inv = r3k_dma_cache_wback_inv;
 
+	printk("Primary instruction cache %ldkB, linesize %ld bytes.\n",
+		icache_size >> 10, icache_lsize);
+	printk("Primary data cache %ldkB, linesize %ld bytes.\n",
+		dcache_size >> 10, dcache_lsize);
 }