patch-2.4.22 linux-2.4.22/arch/mips/gt64120/momenco_ocelot/setup.c

• Lines: 157
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/mips/gt64120/momenco_ocelot/setup.c
• Orig date: 2002-08-02 17:39:43.000000000 -0700

diff -urN linux-2.4.21/arch/mips/gt64120/momenco_ocelot/setup.c linux-2.4.22/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -59,6 +59,7 @@
 #include <asm/ptrace.h>
 #include <asm/reboot.h>
 #include <asm/mc146818rtc.h>
+#include <asm/traps.h>
 #include <linux/version.h>
 #include <linux/bootmem.h>
 #include <linux/blk.h>
@@ -83,25 +84,9 @@
 
 static void __init setup_l3cache(unsigned long size);
 
-void __init momenco_ocelot_setup(void)
+/* setup code for a handoff from a version 1 PMON 2000 PROM */
+void PMON_v1_setup()
 {
-	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
-	unsigned int tmpword;
-
-	board_time_init = gt64120_time_init;
-
-	_machine_restart = momenco_ocelot_restart;
-	_machine_halt = momenco_ocelot_halt;
-	_machine_power_off = momenco_ocelot_power_off;
-
-	/*
-	 * initrd_start = (ulong)ocelot_initrd_start;
-	 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
-	 * initrd_below_start_ok = 1;
-	 */
-	rtc_ops = &no_rtc_ops;
-
-
 	/* A wired TLB entry for the GT64120A and the serial port. The
 	   GT64120A is going to be hit on every IRQ anyway - there's
 	   absolutely no point in letting it be a random TLB entry, as
@@ -122,12 +107,11 @@
 		Ocelot PLD (CS0)	0x2c000000	0xe0020000
 		NVRAM			0x2c800000	0xe0030000
 	*/
-		
-	add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
 
+	add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
 
 	/* Relocate the CS3/BootCS region */
-  	GT_WRITE( GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
+  	GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
 
 	/* Relocate CS[012] */
  	GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
@@ -142,19 +126,75 @@
 	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
 	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
 	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
+}
 
-	/* Relocate PCI0 I/O and Mem0 */
-	GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
-	GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
+/* setup code for a handoff from a version 2 PMON 2000 PROM */
+void PMON_v2_setup()
+{
+	/* A wired TLB entry for the GT64120A and the serial port. The
+	   GT64120A is going to be hit on every IRQ anyway - there's
+	   absolutely no point in letting it be a random TLB entry, as
+	   it'll just cause needless churning of the TLB. And we use
+	   the other half for the serial port, which is just a PITA
+	   otherwise :)
 
-	/* Relocate PCI0 Mem1 */
-	GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
+		Device			Physical	Virtual
+		GT64120 Internal Regs	0xf4000000	0xe0000000
+		UARTs (CS2)		0xfd000000	0xe0001000
+	*/
+	add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
+
+	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
+	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
+	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
+
+		Ocelot PLD (CS0)	0xfc000000	0xe0020000
+		NVRAM			0xfc800000	0xe0030000
+	*/
+	add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
+
+	gt64120_base = 0xe0000000;
+}
+
+void __init momenco_ocelot_setup(void)
+{
+	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
+	unsigned int tmpword;
+
+	board_time_init = gt64120_time_init;
+
+	_machine_restart = momenco_ocelot_restart;
+	_machine_halt = momenco_ocelot_halt;
+	_machine_power_off = momenco_ocelot_power_off;
+
+	/*
+	 * initrd_start = (ulong)ocelot_initrd_start;
+	 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
+	 * initrd_below_start_ok = 1;
+	 */
+	rtc_ops = &no_rtc_ops;
+
+	/* do handoff reconfiguration */
+	if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
+		PMON_v1_setup();
+	else
+		PMON_v2_setup();
+
+	/* Turn off the Bit-Error LED */
+	OCELOT_PLD_WRITE(0x80, INTCLR);
 
 	/* Relocate all the PCI1 stuff, not that we use it */
 	GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
 	GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
 	GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
 
+	/* Relocate PCI0 I/O and Mem0 */
+	GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
+	GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
+
+	/* Relocate PCI0 Mem1 */
+	GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
+
 	/* For the initial programming, we assume 512MB configuration */
 	/* Relocate the CPU's view of the RAM... */
 	GT_WRITE(GT_SCS10LD_OFS, 0);
@@ -283,19 +323,19 @@
 {
 	int register i;
 	unsigned long tmp;
-	
+
 	printk("Enabling L3 cache...");
 
 	/* Enable the L3 cache in the GT64120A's CPU Configuration register */
-	GT_READ(0, &tmp);
+	tmp = GT_READ(0);
 	GT_WRITE(0, tmp | (1<<14));
 
 	/* Enable the L3 cache in the CPU */
-	set_cp0_config(1<<12 /* CONF_TE */);
+	set_c0_config(1<<12 /* CONF_TE */);
 
 	/* Clear the cache */
-	set_taglo(0);
-	set_taghi(0);
+	write_c0_taglo(0);
+	write_c0_taghi(0);
 
 	for (i=0; i < size; i+= 4096) {
 		__asm__ __volatile__ (