patch-2.4.22 linux-2.4.22/arch/arm/mm/proc-arm922.S
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- Lines: 129
- Date:
2003-08-25 04:44:39.000000000 -0700
- Orig file:
linux-2.4.21/arch/arm/mm/proc-arm922.S
- Orig date:
2002-08-02 17:39:42.000000000 -0700
diff -urN linux-2.4.21/arch/arm/mm/proc-arm922.S linux-2.4.22/arch/arm/mm/proc-arm922.S
@@ -130,9 +130,7 @@
*/
.align 5
ENTRY(cpu_arm922_do_idle)
-#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
-#endif
mov pc, lr
/* ================================= CACHE ================================ */
@@ -151,7 +149,7 @@
mov r2, #1
cpu_arm922_cache_clean_invalidate_all_r2:
mov ip, #0
-#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
/*
@@ -189,7 +187,7 @@
cmp r3, #MAX_AREA_SIZE
bgt cpu_arm922_cache_clean_invalidate_all_r2
1: teq r2, #0
-#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE
@@ -220,7 +218,7 @@
.align 5
ENTRY(cpu_arm922_flush_ram_page)
mov r1, #PAGESIZE
-#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
@@ -406,6 +404,10 @@
*/
.align 5
ENTRY(cpu_arm922_tlb_invalidate_range)
+ sub r3, r1, r0
+ cmp r3, #256 * PAGESIZE @ arbitary, should be tuned
+ bhi cpu_arm922_tlb_invalidate_all
+
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 @ drain WB
@@ -450,7 +452,7 @@
.align 5
ENTRY(cpu_arm922_set_pgd)
mov ip, #0
-#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
@@ -483,7 +485,7 @@
*/
.align 5
ENTRY(cpu_arm922_set_pmd)
-#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit
@@ -517,7 +519,7 @@
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0
-#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b
biceq r2, r2, #4
@@ -529,19 +531,14 @@
mov pc, lr
-cpu_manu_name:
- .asciz "ARM/ALTERA"
ENTRY(cpu_arm922_name)
.ascii "Arm922T"
-#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
- .ascii "s"
-#endif
-#if defined(CONFIG_CPU_ARM922_I_CACHE_ON)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
-#if defined(CONFIG_CPU_ARM922_D_CACHE_ON)
+#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
-#if defined(CONFIG_CPU_ARM922_WRITETHROUGH)
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
@@ -575,10 +572,10 @@
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
-#ifdef CONFIG_CPU_ARM922_D_CACHE_ON
+#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
-#ifdef CONFIG_CPU_ARM922_I_CACHE_ON
+#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
mov pc, lr
@@ -626,7 +623,7 @@
.type cpu_arm922_info, #object
cpu_arm922_info:
- .long cpu_manu_name
+ .long 0
.long cpu_arm922_name
.size cpu_arm922_info, . - cpu_arm922_info
@@ -651,7 +648,7 @@
b __arm922_setup
.long cpu_arch_name
.long cpu_elf_name
- .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
+ .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
.long cpu_arm922_info
.long arm922_processor_functions
.size __arm922_proc_info, . - __arm922_proc_info
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)