patch-2.4.21 linux-2.4.21/drivers/pci/pci.c
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- Lines: 106
- Date:
2003-06-13 07:51:35.000000000 -0700
- Orig file:
linux-2.4.20/drivers/pci/pci.c
- Orig date:
2002-11-28 15:53:14.000000000 -0800
diff -urN linux-2.4.20/drivers/pci/pci.c linux-2.4.21/drivers/pci/pci.c
@@ -163,6 +163,8 @@
* %PCI_CAP_ID_MSI Message Signalled Interrupts
*
* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
+ *
+ * %PCI_CAP_ID_PCIX PCI-X
*/
int
pci_find_capability(struct pci_dev *dev, int cap)
@@ -930,14 +932,13 @@
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cache_size);
cache_size <<= 2;
if (cache_size != SMP_CACHE_BYTES) {
- printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly "
- "(%i bytes) by BIOS/FW, ",
+ printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly (%i bytes) by BIOS/FW.\n",
dev->slot_name, cache_size);
if (cache_size > SMP_CACHE_BYTES) {
- printk("expecting %i\n", SMP_CACHE_BYTES);
+ printk("PCI: %s cache line size too large - expecting %i.\n", dev->slot_name, SMP_CACHE_BYTES);
rc = -EINVAL;
} else {
- printk("correcting to %i\n", SMP_CACHE_BYTES);
+ printk("PCI: %s PCI cache line size corrected to %i.\n", dev->slot_name, SMP_CACHE_BYTES);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
SMP_CACHE_BYTES >> 2);
}
@@ -1037,13 +1038,20 @@
}
/*
- * Find the extent of a PCI decode..
+ * Find the extent of a PCI decode, do sanity checks.
*/
-static u32 pci_size(u32 base, unsigned long mask)
+static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
{
- u32 size = mask & base; /* Find the significant bits */
+ u32 size = mask & maxbase; /* Find the significant bits */
+ if (!size)
+ return 0;
size = size & ~(size-1); /* Get the lowest of them to find the decode size */
- return size-1; /* extent = size - 1 */
+ size -= 1; /* extent = size - 1 */
+ if (base == maxbase && ((base | size) & mask) != mask)
+ return 0; /* base == maxbase can be valid only
+ if the BAR has been already
+ programmed with all 1s */
+ return size;
}
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
@@ -1066,13 +1074,17 @@
if (l == 0xffffffff)
l = 0;
if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
+ sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
+ if (!sz)
+ continue;
res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
- sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
} else {
+ sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
+ if (!sz)
+ continue;
res->start = l & PCI_BASE_ADDRESS_IO_MASK;
res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
- sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
}
res->end = res->start + (unsigned long) sz;
res->flags |= pci_calc_resource_flags(l);
@@ -1102,6 +1114,7 @@
if (rom) {
dev->rom_base_reg = rom;
res = &dev->resource[PCI_ROM_RESOURCE];
+ res->name = dev->name;
pci_read_config_dword(dev, rom, &l);
pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
pci_read_config_dword(dev, rom, &sz);
@@ -1109,13 +1122,14 @@
if (l == 0xffffffff)
l = 0;
if (sz && sz != 0xffffffff) {
+ sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
+ if (!sz)
+ return;
res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
res->start = l & PCI_ROM_ADDRESS_MASK;
- sz = pci_size(sz, PCI_ROM_ADDRESS_MASK);
res->end = res->start + (unsigned long) sz;
}
- res->name = dev->name;
}
}
@@ -2153,6 +2167,8 @@
EXPORT_SYMBOL(pci_do_scan_bus);
EXPORT_SYMBOL(pci_scan_slot);
EXPORT_SYMBOL(pci_scan_bus);
+EXPORT_SYMBOL(pci_scan_device);
+EXPORT_SYMBOL(pci_read_bridge_bases);
#ifdef CONFIG_PROC_FS
EXPORT_SYMBOL(pci_proc_attach_device);
EXPORT_SYMBOL(pci_proc_detach_device);
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)