patch-2.4.21 linux-2.4.21/arch/ia64/sn/kernel/sn1/sn1_smp.c
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- Lines: 145
- Date:
2003-06-13 07:51:31.000000000 -0700
- Orig file:
linux-2.4.20/arch/ia64/sn/kernel/sn1/sn1_smp.c
- Orig date:
2002-08-02 17:39:43.000000000 -0700
diff -urN linux-2.4.20/arch/ia64/sn/kernel/sn1/sn1_smp.c linux-2.4.21/arch/ia64/sn/kernel/sn1/sn1_smp.c
@@ -59,11 +59,16 @@
* to other cpus for flushing TLB ranges.
*/
typedef struct {
- unsigned long start;
- unsigned long end;
- unsigned long nbits;
- unsigned int rid;
- atomic_t unfinished_count;
+ union {
+ struct {
+ unsigned long start;
+ unsigned long end;
+ unsigned long nbits;
+ unsigned int rid;
+ atomic_t unfinished_count;
+ } ptc;
+ char pad[SMP_CACHE_BYTES];
+ };
} ptc_params_t;
#define NUMPTC 512
@@ -149,11 +154,11 @@
return;
do {
- start = ptcParams->start;
+ start = ptcParams->ptc.start;
saved_rid = (unsigned int) ia64_get_rr(start);
- end = ptcParams->end;
- nbits = ptcParams->nbits;
- rid = ptcParams->rid;
+ end = ptcParams->ptc.end;
+ nbits = ptcParams->ptc.nbits;
+ rid = ptcParams->ptc.rid;
if (saved_rid != rid) {
ia64_set_rr(start, (unsigned long)rid);
@@ -167,7 +172,7 @@
ia64_srlz_i();
- result = atomic_dec(&ptcParams->unfinished_count);
+ result = atomic_dec(&ptcParams->ptc.unfinished_count);
#ifdef PTCDEBUG
{
int i = ptcParams-&ptcParamArray[0];
@@ -256,7 +261,7 @@
/* check the current pointer to the beginning */
ptr = params;
while(--ptr >= &ptcParamArray[0]) {
- if (atomic_read(&ptr->unfinished_count) == 0)
+ if (atomic_read(&ptr->ptc.unfinished_count) == 0)
break;
++backlog;
}
@@ -265,7 +270,7 @@
/* check the end of the array */
ptr = &ptcParamArray[NUMPTC];
while (--ptr > params) {
- if (atomic_read(&ptr->unfinished_count) == 0)
+ if (atomic_read(&ptr->ptc.unfinished_count) == 0)
break;
++backlog;
}
@@ -275,12 +280,12 @@
#endif /* PTCDEBUG */
/* wait for the next entry to clear...should be rare */
- if (atomic_read(&next->unfinished_count) > 0) {
+ if (atomic_read(&next->ptc.unfinished_count) > 0) {
#ifdef PTCDEBUG
ptcParamsAllBusy++;
- if (atomic_read(&nextnext->unfinished_count) == 0) {
- if (atomic_read(&next->unfinished_count) > 0) {
+ if (atomic_read(&nextnext->ptc.unfinished_count) == 0) {
+ if (atomic_read(&next->ptc.unfinished_count) > 0) {
panic("\nnonzero next zero nextnext %lx %lx\n",
(long)next, (long)nextnext);
}
@@ -293,16 +298,16 @@
local_irq_restore(irqflags);
/* now we know it's not this cpu, so just wait */
- while (atomic_read(&next->unfinished_count) > 0) {
+ while (atomic_read(&next->ptc.unfinished_count) > 0) {
barrier();
}
}
- params->start = start;
- params->end = end;
- params->nbits = nbits;
- params->rid = (unsigned int) ia64_get_rr(start);
- atomic_set(¶ms->unfinished_count, smp_num_cpus);
+ params->ptc.start = start;
+ params->ptc.end = end;
+ params->ptc.nbits = nbits;
+ params->ptc.rid = (unsigned int) ia64_get_rr(start);
+ atomic_set(¶ms->ptc.unfinished_count, smp_num_cpus);
/* The atomic_set above can hit memory *after* the update
* to ptcParamsEmpty below, which opens a timing window
@@ -335,13 +340,11 @@
* shouldn't be using user TLB entries. To change this to wait
* for all the flushes to complete, enable the following code.
*/
-#ifdef SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE
+#if defined(SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE) || defined(BUS_INT_WAR)
/* this code is not tested */
/* wait for the flush to complete */
- while (atomic_read(¶ms.unfinished_count) > 1)
+ while (atomic_read(¶ms->ptc.unfinished_count) > 0)
barrier();
-
- atomic_set(¶ms->unfinished_count, 0);
#endif
}
@@ -369,18 +372,17 @@
static int off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
+#ifdef BUS_INT_WAR
+ if (vector != ap_wakeup_vector) {
+ return;
+ }
+#endif
+
nasid = cpu_physical_id_to_nasid(physid);
slice = cpu_physical_id_to_slice(physid);
p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
-#if defined(ZZZBRINGUP)
- {
- static int count=0;
- if (count++ < 10) printk("ZZ sendIPI 0x%x vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
- smp_processor_id(), vector, nasid, slice, (long)p);
- }
-#endif
mb();
*p = (delivery_mode << 8) | (vector & 0xff);
}
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