patch-2.4.21 linux-2.4.21/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c

• Lines: 280
• Date: 2003-06-13 07:51:30.000000000 -0700
• Orig file: linux-2.4.20/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
• Orig date: 2002-08-02 17:39:43.000000000 -0700

diff -urN linux-2.4.20/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c linux-2.4.21/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
@@ -44,24 +44,6 @@
 #endif
 
 
-#ifdef LATER
-#if (PCIBR_FREEZE_TIME) || PCIBR_ATE_DEBUG
-LOCAL struct reg_desc   ate_bits[] =
-{
-    {0xFFFF000000000000ull, -48, "RMF", "%x"},
-    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
-     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
-    {0x0000000000000F00ull, -8, "port", "%x"},
-    {0x0000000000000010ull, 0, "Barrier"},
-    {0x0000000000000008ull, 0, "Prefetch"},
-    {0x0000000000000004ull, 0, "Precise"},
-    {0x0000000000000002ull, 0, "Coherent"},
-    {0x0000000000000001ull, 0, "Valid"},
-    {0}
-};
-#endif
-#endif	/* LATER */
-
 #ifndef LOCAL
 #define LOCAL           static
 #endif
@@ -79,7 +61,7 @@
 	   			unsigned *freeze_time_ptr,
 #endif
 	   			unsigned *cmd_regs);
-void 	  ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+void 	  ate_write(pcibr_soft_t pcibr_soft, bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
 void ate_thaw(pcibr_dmamap_t pcibr_dmamap,
 	 			int ate_index,
 #if PCIBR_FREEZE_TIME
@@ -119,26 +101,73 @@
     int                     i, j;
     bridgereg_t             old_enable, new_enable;
     int                     s;
+    int			    this_is_pic = is_pic(bridge);
 
     /* Probe SSRAM to determine its size. */
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-    bridge->b_int_enable = new_enable;
+    if ( this_is_pic ) {
+	old_enable = bridge->b_int_enable;
+	new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+	bridge->b_int_enable = new_enable;
+    }
+    else {
+	if (io_get_sh_swapper(NASID_GET(bridge))) {
+		old_enable = BRIDGE_REG_GET32((&bridge->b_int_enable));
+		new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+		BRIDGE_REG_SET32((&bridge->b_int_enable)) = new_enable;
+	}
+	else {
+		old_enable = bridge->b_int_enable;
+		new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+		bridge->b_int_enable = new_enable;
+	}
+    }
 
     for (i = 1; i < ATE_NUM_SIZES; i++) {
 	/* Try writing a value */
-	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+	if ( this_is_pic ) {
+		bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+	}
+	else {
+		if (io_get_sh_swapper(NASID_GET(bridge)))
+			bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = __swab64(ATE_PROBE_VALUE);
+		else
+			bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+	}
 
 	/* Guard against wrap */
 	for (j = 1; j < i; j++)
 	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
 
 	/* See if value was written */
-	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
-	    largest_working_size = i;
+	if ( this_is_pic ) {
+		if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+				largest_working_size = i;
+	}
+	else {
+		if (io_get_sh_swapper(NASID_GET(bridge))) {
+			if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == __swab64(ATE_PROBE_VALUE))
+					largest_working_size = i;
+			else {
+				if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+					largest_working_size = i;
+			}
+		}
+	}
+    }
+    if ( this_is_pic ) {
+	bridge->b_int_enable = old_enable;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    else {
+	if (io_get_sh_swapper(NASID_GET(bridge))) {
+		BRIDGE_REG_SET32((&bridge->b_int_enable)) = old_enable;
+		BRIDGE_REG_GET32((&bridge->b_wid_tflush));   /* wait until Bridge PIO complete */
+	}
+	else {
+		bridge->b_int_enable = old_enable;
+		bridge->b_wid_tflush;               /* wait until Bridge PIO complete */
+	}
     }
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
 
     /*
      * ensure that we write and read without any interruption.
@@ -146,20 +175,41 @@
      */
 
     s = splhi();
-    bridge->b_wid_control = (bridge->b_wid_control
-	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
-	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
-    bridge->b_wid_control;		/* inval addr bug war */
+    if ( this_is_pic ) {
+	bridge->b_wid_control = (bridge->b_wid_control
+			& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+			| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+	bridge->b_wid_control;		/* inval addr bug war */
+    }
+    else {
+	if (io_get_sh_swapper(NASID_GET(bridge))) {
+		BRIDGE_REG_SET32((&(bridge->b_wid_control))) = 
+				__swab32((BRIDGE_REG_GET32((&bridge->b_wid_control))
+					& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+					| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size));
+		BRIDGE_REG_GET32((&bridge->b_wid_control));/* inval addr bug war */
+	}
+	else {
+		bridge->b_wid_control = (bridge->b_wid_control & ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+				| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+		bridge->b_wid_control;              /* inval addr bug war */
+	}
+    }
     splx(s);
 
     num_entries = ATE_NUM_ENTRIES(largest_working_size);
 
-#if PCIBR_ATE_DEBUG
-    if (num_entries)
-	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
-    else
-	printk("bridge at 0x%x: no external ATE RAM found\n", bridge);
-#endif
+    if (pcibr_debug_mask & PCIBR_DEBUG_ATE) {
+	if (num_entries) {
+	    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATE, NULL,
+			"bridge at 0x%x: clearing %d external ATEs\n",
+			bridge, num_entries));
+	} else {
+	    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATE, NULL,
+			"bridge at 0x%x: no external ATE RAM found\n",
+			bridge));
+	}
+    }
 
     /* Initialize external mapping entries */
     for (entry = 0; entry < num_entries; entry++)
@@ -339,7 +389,8 @@
 #endif
 
     cmd_lwa = 0;
-    for (slot = 0; slot < 8; ++slot)
+    for (slot = pcibr_soft->bs_min_slot; 
+		slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot)
 	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
 	    cmd_reg = pcibr_soft->
 		bs_slot[slot].
@@ -366,28 +417,54 @@
 	    cmd_lwa[0];
 
 	    /* Flush all the write buffers in the bridge */
-	    for (slot = 0; slot < 8; ++slot)
+	    for (slot = pcibr_soft->bs_min_slot; 
+				slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) {
 		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
 			    /* Flush the write buffer associated with this
 			     * PCI device which might be using dma map RAM.
 			     */
-			    bridge->b_wr_req_buf[slot].reg;
+			if ( is_pic(bridge) ) {
+				bridge->b_wr_req_buf[slot].reg;
+			}
+			else {
+				if (io_get_sh_swapper(NASID_GET(bridge)) ) {
+					BRIDGE_REG_GET32((&bridge->b_wr_req_buf[slot].reg));
+				}
+				else
+					bridge->b_wr_req_buf[slot].reg;
+			}
 		    }
+	    }
     }
     return s;
 }
 
-#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
-
 void
-ate_write(bridge_ate_p ate_ptr,
+ate_write(pcibr_soft_t pcibr_soft,
+	  bridge_ate_p ate_ptr,
 	  int ate_count,
 	  bridge_ate_t ate)
 {
-    while (ate_count-- > 0) {
-	*ate_ptr++ = ate;
-	ate += IOPGSIZE;
-    }
+	if (IS_PIC_SOFT(pcibr_soft) ) {
+    		while (ate_count-- > 0) {
+			*ate_ptr++ = ate;
+			ate += IOPGSIZE;
+		}
+	}
+	else {
+		if (io_get_sh_swapper(NASID_GET(ate_ptr))) {
+    			while (ate_count-- > 0) {
+				*ate_ptr++ = __swab64(ate);
+				ate += IOPGSIZE;
+			}
+		}
+		else {
+    			while (ate_count-- > 0) {
+				*ate_ptr++ = ate;
+				ate += IOPGSIZE;
+			}
+		}
+	}
 }
 
 #if PCIBR_FREEZE_TIME
@@ -425,10 +502,24 @@
 	return;
 
     /* restore cmd regs */
-    for (slot = 0; slot < 8; ++slot)
-	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
-	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
-
+    for (slot = pcibr_soft->bs_min_slot; 
+		slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) {
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER) {
+		if ( IS_PIC_SOFT(pcibr_soft) ) {
+			pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
+		}
+		else {
+			if (io_get_sh_swapper(NASID_GET(bridge))) {
+				bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = __swab32(cmd_reg);
+			}
+			else {
+//				BUG(); /* Does this really work if called when io_get_sh_swapper = 0? */
+//				bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+				pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
+			}
+		}
+	}
+    }
     pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
     atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
 
@@ -442,7 +533,7 @@
 	if (max_ate_total < ate_total)
 	    max_ate_total = ate_total;
 	pcibr_unlock(pcibr_soft, s);
-	printk("%s: pci freeze time %d usec for %d ATEs\n"
+	printk( "%s: pci freeze time %d usec for %d ATEs\n"
 		"\tfirst ate: %R\n",
 		pcibr_soft->bs_name,
 		freeze_time * 1000 / 1250,