patch-2.4.20 linux-2.4.20/arch/mips/mm/tlb-r4k.c

• Lines: 78
• Date: Thu Nov 28 15:53:10 2002
• Orig file: linux-2.4.19/arch/mips/mm/tlb-r4k.c
• Orig date: Fri Aug 2 17:39:43 2002

diff -urN linux-2.4.19/arch/mips/mm/tlb-r4k.c linux-2.4.20/arch/mips/mm/tlb-r4k.c
@@ -119,12 +119,11 @@
 				idx = get_index();
 				set_entrylo0(0);
 				set_entrylo1(0);
-				set_entryhi(KSEG0);
 				if (idx < 0)
 					continue;
-				BARRIER;
 				/* Make sure all entries differ. */
-				set_entryhi(KSEG0+idx*0x2000);
+				set_entryhi(KSEG0 + idx*0x2000);
+				BARRIER;
 				tlb_write_indexed();
 				BARRIER;
 			}
@@ -271,19 +270,19 @@
 	wired = get_wired();
 	set_wired(wired + 1);
 	set_index(wired);
-	BARRIER;    
+	BARRIER;
 	set_pagemask(pagemask);
 	set_entryhi(entryhi);
 	set_entrylo0(entrylo0);
 	set_entrylo1(entrylo1);
-	BARRIER;    
+	BARRIER;
 	tlb_write_indexed();
-	BARRIER;    
-    
+	BARRIER;
+
 	set_entryhi(old_ctx);
-	BARRIER;    
+	BARRIER;
 	set_pagemask(old_pagemask);
-	local_flush_tlb_all();    
+	local_flush_tlb_all();
 	__restore_flags(flags);
 }
 
@@ -316,17 +315,17 @@
 	}
 
 	set_index(temp_tlb_entry);
-	BARRIER;    
+	BARRIER;
 	set_pagemask(pagemask);
 	set_entryhi(entryhi);
 	set_entrylo0(entrylo0);
 	set_entrylo1(entrylo1);
-	BARRIER;    
+	BARRIER;
 	tlb_write_indexed();
-	BARRIER;    
-    
+	BARRIER;
+
 	set_entryhi(old_ctx);
-	BARRIER;    
+	BARRIER;
 	set_pagemask(old_pagemask);
 out:
 	__restore_flags(flags);
@@ -339,11 +338,11 @@
 
 	prid = read_32bit_cp0_register(CP0_PRID) & 0xff00;
 	if (prid == PRID_IMP_RM7000 || !(config & (1 << 31)))
-		/* 
+		/*
 		 * Not a MIPS32 complianant CPU.  Config 1 register not
 		 * supported, we assume R4k style.  Cpu probing already figured
 		 * out the number of tlb entries.
-		 */  
+		 */
 		return;
 
 	config1 = read_mips32_cp0_config1();