patch-2.4.20 linux-2.4.20/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S

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diff -urN linux-2.4.19/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S linux-2.4.20/arch/mips/galileo-boards/ev64120/compressed/sbdreset_evb64120A.S
@@ -1,7 +1,7 @@
 /*
  * Copyright 1997 Algorithmics Ltd
  *	All Rights Reserved
- *	
+ *
  * gal9/sbdreset.sx -- low level board dependent routines
  */
 
@@ -23,29 +23,29 @@
 
 #include "gt64011.h"
 #include "ns16550.h"
-			
+
 #ifdef GALILEO_PORT // miniBios crack
 #define C0_CONFIG CP0_CONFIG
 #define C0_STATUS CP0_STATUS
 #define C0_TLBLO0 CP0_ENTRYLO0
 #define C0_TLBLO1 CP0_ENTRYLO1
 #define C0_PGMASK CP0_PAGEMASK
-#define C0_TLBHI CP0_ENTRYHI 
+#define C0_TLBHI CP0_ENTRYHI
 #define C0_INX CP0_INDEX
 #define NTLBENTRIES     48
-        
-        
+
+
 #define CFG_IB CONF_IB
 #define CFG_DB CONF_DB
 #define CFG_C_NONCOHERENT CONF_CM_CACHABLE_NONCOHERENT
-#define C0_SR CP0_STATUS        
+#define C0_SR CP0_STATUS
 #define SR_DE ST0_DE
 
-        
+
         #define SLEAF(x) LEAF(x)
         #define SEND(x) END(x)
         #define XLEAF(x) LEAF(x)
-        #define SBD_DISPLAY(a,b,c,d,e) ; 
+        #define SBD_DISPLAY(a,b,c,d,e) ;
 
 #define K0BASE          0x80000000
 #define K0SIZE          0x20000000
@@ -70,7 +70,7 @@
 #endif
 
 #define MB	0x100000
-				
+
 #define MemTypeNone		0x8000
 #define MemRasMask		0x0f00
 #define MemRasShift		8
@@ -85,7 +85,7 @@
 #define bank3	s5
 #define memtop	s6
 #define membase	s7
-	
+
 /*#if #endian(big)	*/
 #ifdef __MIPSEB__
 
@@ -104,9 +104,9 @@
 #else
 #define HTOLL(sr,tr)
 #endif
-				
+
 #undef DBGSBD
-	
+
 #ifdef DBGSBD
 #define DBG(s) \
 	.rdata ; \
@@ -114,7 +114,7 @@
 	.text ; \
 	la	a0, 88b ; \
 	jal	_dbgmsg
-	
+
 LEAF(_dbgmsg)
 	.set noat
 	li	AT,PHYS_TO_K1(NS16550_CHANB)
@@ -123,13 +123,13 @@
 	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
 	and	v1,LSR_TXRDY
 	beqz	v1,waitrdy
-	
+
 	lbu	v1,(a0)
 	addu	a0,1
 	beqz	v1,9f
 	sb	v1,DATA(AT)
 	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
-	b	waitrdy	
+	b	waitrdy
 9:	j	ra
 	.set at
 END(_dbgmsg)
@@ -142,7 +142,7 @@
 	.set noreorder;	nop; nop; nop; nop; nop; nop; nop; nop; .set reorder
 	and	t1,LSR_TXRDY
 	beqz	t1,1b
-	
+
 	srl	t1,a0,28
 	addu	t1,'0'
 	ble	t1,'9',2f
@@ -153,11 +153,11 @@
 	sll	a0,4
 	sub	t0,1
 	bnez	t0,1b
-		
+
 	j	ra
 	.set at
 END(_dbghex)
-	
+
 	.rdata
 initb_str:
 	.byte	9,0x40	/* Reset CH B */
@@ -171,7 +171,7 @@
 	.byte	0,0x10
 	.byte	14,0x01	/* enable baud rate gen. */
 	.byte	15,0x00	/* known state for reg 15 */
-	
+
 	.byte	14,0x00	/* disable baud rate gen. */
 	.byte	12,0x0a /* 0x0a	= 9600 baud time const. - lower 8 bits */
 	.byte	13,0x00	/* 9600 buad time const. - upper 8 bits */
@@ -179,7 +179,7 @@
 	.byte	0xff
 
 	.text
-	
+
 SLEAF(_dbginit)
         /*
         li	v0,PHYS_TO_K1(NS16550_CHANB)
@@ -194,27 +194,27 @@
         */
         jal     init_ns16550_chan_b # Debug channel
 	j	ra
-SEND(_dbginit)		
+SEND(_dbginit)
 #else
-#define DBG(s)		
+#define DBG(s)
 #endif
-		
+
 LEAF(sbdreset)
 	move	rasave,ra
 
 	/* if launched by ITROM, leave Config alone */
-#ifndef ITBASE	
+#ifndef ITBASE
 	/* set config register for 32b/32b cachelines, kseg0 cacheable */
 	mfc0	t1,C0_CONFIG
 	and	t1,~0x3f		# set bits 5..0 only
 	or	t1,CFG_IB | CFG_DB | CFG_C_NONCOHERENT
 	mtc0	t1,C0_CONFIG
-#endif	
+#endif
+
+       /* Initialize stack pointer to 6MB address */
+         li sp,0xa0600000
 
-       /* Initialize stack pointer to 6MB address */        
-         li sp,0xa0600000 
 
-        
         /*
 	 * slight amount of kludgery here to stop RAM resident
 	 * program from overwriting itself...
@@ -248,23 +248,23 @@
 #define GT_INTERNAL_REG_BASE 0xb4000000
 
         li      p64011, PA_TO_KVA1(GT64011_BASE)
-         
+
         li  v0,0xb400046c       /* Boot Device */
         lw  t0,0(v0)
         and t0,0x00003000       /* Keep the correct boot size */
 	or  t0,htoll(0x3847de70)
 	sw  t0,0(v0)
-        
+
         li  v0,0xb4000468       /* CS3 Device - 16 bit FLASH memory */
         li  t0,htoll(0x3859e6e8)
 	sw  t0,0(v0)
-        
-                
+
+
         li  v0,0xb4000c84       /* PCI 1 timeout register */
         li  t0,htoll(0xffff)
 	sw  t0,0(v0)
-        
-                
+
+
         li  v0,0xb4000c3c       /* Enable I/O response on PCI0 */
         li  t0,htoll(0x7)
 	sw  t0,0(v0)
@@ -274,14 +274,14 @@
 	sw  t0,0(v0)
 
         /* GT-64120 Initialization */
-        
-        li      p64011, PA_TO_KVA1(GT64011_BASE)	
+
+        li      p64011, PA_TO_KVA1(GT64011_BASE)
 
         /*********************************************************************/
         /************************* SDRAM initializing ************************/
         /******************************* START *******************************/
-        
-        
+
+
                                         /* SDRAM banks 0,1,2,3 parameters               */
         li      t0,htoll(0x01908200)    /* - Standard Monitor: Interleave enabled       */
         li      v0,0xb4000448           /* - Registered SDRAM (Bit 23)                  */
@@ -292,76 +292,76 @@
                                         /* - No ECC                                     */
                                         /* - No ByPass                                  */
                                         /* - Burst length: 8                            */
-        
+
         /* Detect whether we have a 16,64,128 or 256 Mbit SDRAM on DIMM0 */
         /* Set bank0`s range to: 0 - 0x10000000 (256 MByte)     */
 _DIMM0:
-        li  v0,0xb4000008      
+        li  v0,0xb4000008
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        
-        li  v0,0xb4000010      
+
+        li  v0,0xb4000010
 	li  t0,htoll(0x7f)
 	sw  t0,0(v0)
-        
+
         /* Close banks 2 and 3 */
-        li  v0,0xb4000018      
+        li  v0,0xb4000018
 	li  t0,htoll(0x7ff)
 	sw  t0,0(v0)
-        li  v0,0xb4000020      
+        li  v0,0xb4000020
 	li  t0,htoll(0x00)
 	sw  t0,0(v0)
-        
+
         /* Extend bank0 to 0x10000000 and Close bank1,2 and 3 */
         DBG("Extend bank0 to 0x10000000 and Close bank1,2 and 3...\r\n")
-        li  v0,0xb4000400      
+        li  v0,0xb4000400
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        li  v0,0xb4000404      
+        li  v0,0xb4000404
 	li  t0,htoll(0xff)
 	sw  t0,0(v0)
-        li  v0,0xb4000408      
+        li  v0,0xb4000408
 	li  t0,htoll(0xff)
-	sw  t0,0(v0)   
-        li  v0,0xb400040c      
+	sw  t0,0(v0)
+        li  v0,0xb400040c
 	li  t0,htoll(0x00)
 	sw  t0,0(v0)
-        li  v0,0xb4000410      
+        li  v0,0xb4000410
 	li  t0,htoll(0xff)
-	sw  t0,0(v0)   
-        li  v0,0xb4000414      
+	sw  t0,0(v0)
+        li  v0,0xb4000414
 	li  t0,htoll(0x00)
 	sw  t0,0(v0)
-        li  v0,0xb4000418      
+        li  v0,0xb4000418
 	li  t0,htoll(0xff)
-	sw  t0,0(v0)   
-        li  v0,0xb400041c      
+	sw  t0,0(v0)
+        li  v0,0xb400041c
 	li  t0,htoll(0x00)
-	sw  t0,0(v0)        
+	sw  t0,0(v0)
 
         /* Configure bank0 to 256 Mbit */
         DBG("Configure bank0 to 256 Mbit...\r\n")
-        li  v0,0xb400044c      
+        li  v0,0xb400044c
 	li  t0,htoll(0x00004c69)
         sw  t0,0(v0)
-        
+
         /* Config the SDRAM banks decode system */
-	li  v0,0xb400047c      
+	li  v0,0xb400047c
 	li  t0,htoll(2)
 	sw  t0,0(v0)
- 
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x3)
 	sw  t0,0(v0)
-        
+
         li  v0,0xa0000000
         li  t0,0
         sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x0)
-	sw  t0,0(v0)      
-        
+	sw  t0,0(v0)
+
         /* Write to address 0x2000000 and check if 0x00000000 is being written too */
         DBG("Write to address 0x2000000 and check if 0x00000000 is being written too...\r\n")
         li  v0,0xa0000000
@@ -372,7 +372,7 @@
         bne t1,v0,1b
 
         /* The address should activate Dadr12 */
-        li  v0,0xa2000000      
+        li  v0,0xa2000000
 	li  t0,0x11111111
         sw  t0,0(v0)
         li  v0,0xa0000010
@@ -387,7 +387,7 @@
         li    v0,0x11111111
         lw    t0,(t0)
         bne   t0,v0,_256MBIT
-        
+
         /* Write to address 0x1000 and check if 0x00000000 is being written too */
         DBG("Write to address 0x1000 and check if 0x00000000 is being written too...\r\n")
         li  v0,0xa0000000
@@ -398,7 +398,7 @@
         bne t1,v0,1b
 
         /* The address should activate bank select1*/
-        li  v0,0xa0001000      
+        li  v0,0xa0001000
 	li  t0,0x11111111
         sw  t0,0(v0)
         li  v0,0xa0000010
@@ -425,7 +425,7 @@
 
         /* The address should activate Dadr9 which on the column cycle is in active with 64 Mbit
            device */
-        li  v0,0xa8000000      
+        li  v0,0xa8000000
 	li  t0,0x11111111
         sw  t0,0(v0)
         li  v0,0xa0000010
@@ -441,11 +441,11 @@
         lw    t0,(t0)
         beq   t0,v0,_64MBIT
         b     _128MBIT
-        
+
 _16MBIT:
         DBG("16 Mbit SDRAM detected...\r\n")
         /* In 16 Mbit SDRAM we must use 2 way bank interleaving!!! */
-        li  v0,0xb4000810      
+        li  v0,0xb4000810
 	li  t0,htoll(16)
 	sw  t0,0(v0)
         li  t1,htoll(0x00000449)
@@ -454,7 +454,7 @@
 _64MBIT:
         DBG("64 Mbit SDRAM detected...\r\n")
         /* In 64 Mbit SDRAM we must use 4 way bank interleaving!!! */
-        li  v0,0xb4000810      
+        li  v0,0xb4000810
 	li  t0,htoll(64)
 	sw  t0,0(v0)
         li  t1,htoll(0x00000c69)
@@ -463,7 +463,7 @@
 _128MBIT:
         DBG("128 Mbit SDRAM detected...\r\n")
         /* In 128 Mbit SDRAM we must use 4 way bank interleaving!!! */
-        li  v0,0xb4000810      
+        li  v0,0xb4000810
 	li  t0,htoll(128)
 	sw  t0,0(v0)
         li  t1,htoll(0x00000c69)
@@ -472,85 +472,85 @@
 _256MBIT:
         DBG("256 Mbit SDRAM detected...\r\n")
         /* In 256 Mbit SDRAM we must use 4 way bank interleaving!!! */
-        li  v0,0xb4000810      
+        li  v0,0xb4000810
 	li  t0,htoll(256)
 	sw  t0,0(v0)
         li  t1,htoll(0x00004c69)
         b   _DIMM1
-        
-_DIMM1:        
+
+_DIMM1:
         li  v0,0xb400044c
         sw  t1,0(v0)  # Bank0
-        sw  t1,4(v0)  # Bank1           
-        
+        sw  t1,4(v0)  # Bank1
+
         /* Detect whether we have a 16,64,128 or 256 Mbit SDRAM on DIMM1 */
         /* Close banks 0 and 1 */
-        li  v0,0xb4000008      
+        li  v0,0xb4000008
 	li  t0,htoll(0xff)
 	sw  t0,0(v0)
-        
-        li  v0,0xb4000010      
+
+        li  v0,0xb4000010
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        
+
         /* Set bank2`s range to: 0 - 0x10000000 (256 MByte)     */
-        li  v0,0xb4000018      
+        li  v0,0xb4000018
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        li  v0,0xb4000020      
+        li  v0,0xb4000020
 	li  t0,htoll(0x7f)
 	sw  t0,0(v0)
-        
+
         /* Extend bank2 to 0x10000000 and Close bank0,1 and 3 */
         DBG("Extend bank2 to 0x10000000 and Close banks 0,1 and 3...\r\n")
-        li  v0,0xb4000400      
+        li  v0,0xb4000400
 	li  t0,htoll(0xff)
 	sw  t0,0(v0)
-        li  v0,0xb4000404      
+        li  v0,0xb4000404
 	li  t0,htoll(0x00)
 	sw  t0,0(v0)
-        li  v0,0xb4000408      
+        li  v0,0xb4000408
 	li  t0,htoll(0xff)
-	sw  t0,0(v0)   
-        li  v0,0xb400040c      
+	sw  t0,0(v0)
+        li  v0,0xb400040c
 	li  t0,htoll(0x00)
 	sw  t0,0(v0)
-        li  v0,0xb4000410      
+        li  v0,0xb4000410
 	li  t0,htoll(0x00)
-	sw  t0,0(v0)   
-        li  v0,0xb4000414      
+	sw  t0,0(v0)
+        li  v0,0xb4000414
 	li  t0,htoll(0xff)
 	sw  t0,0(v0)
-        li  v0,0xb4000418      
+        li  v0,0xb4000418
 	li  t0,htoll(0xff)
-	sw  t0,0(v0)   
-        li  v0,0xb400041c      
+	sw  t0,0(v0)
+        li  v0,0xb400041c
 	li  t0,htoll(0x00)
-	sw  t0,0(v0)        
+	sw  t0,0(v0)
 
         /* Configure bank2 to 256 Mbit */
         DBG("Configure bank2 to 256 Mbit...\r\n")
-        li  v0,0xb4000454      
+        li  v0,0xb4000454
 	li  t0,htoll(0x00004c69)
         sw  t0,0(v0)
-        
+
         /* Config the SDRAM banks decode system */
-	li  v0,0xb400047c      
+	li  v0,0xb400047c
 	li  t0,htoll(2)
 	sw  t0,0(v0)
- 
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x3)
 	sw  t0,0(v0)
-        
+
         li  v0,0xa0000000
         li  t0,0
         sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x0)
-	sw  t0,0(v0)      
-        
+	sw  t0,0(v0)
+
         /* Write to address 0x2000000 and check if 0x00000000 is being written too */
         DBG("Write to address 0x2000000 and check if 0x00000000 is being written too...\r\n")
         li  v0,0xa0000000
@@ -561,7 +561,7 @@
         bne t1,v0,1b
 
         /* The address should activate Dadr12 */
-        li  v0,0xa2000000      
+        li  v0,0xa2000000
 	li  t0,0x11111111
         sw  t0,0(v0)
         li  v0,0xa0000010
@@ -576,7 +576,7 @@
         li    v0,0x11111111
         lw    t0,(t0)
         bne   t0,v0,_256MBIT2
-        
+
         /* Write to address 0x1000 and check if 0x00000000 is being written too */
         DBG("Write to address 0x1000 and check if 0x00000000 is being written too...\r\n")
         li  v0,0xa0000000
@@ -587,7 +587,7 @@
         bne t1,v0,1b
 
         /* The address should activate bank select1*/
-        li  v0,0xa0001000      
+        li  v0,0xa0001000
 	li  t0,0x11111111
         sw  t0,0(v0)
         li  v0,0xa0000010
@@ -614,7 +614,7 @@
 
         /* The address should activate Dadr9 which on the column cycle is in active with 64 Mbit
            device */
-        li  v0,0xa8000000      
+        li  v0,0xa8000000
 	li  t0,0x11111111
         sw  t0,0(v0)
         li  v0,0xa0000010
@@ -630,11 +630,11 @@
         lw    t0,(t0)
         beq   t0,v0,_64MBIT2
         b     _128MBIT2
-        
+
 _16MBIT2:
         DBG("16 Mbit SDRAM detected...\r\n")
         /* In 16 Mbit SDRAM we must use 2 way bank interleaving!!! */
-        li  v0,0xb4000814      
+        li  v0,0xb4000814
 	li  t0,htoll(16)
 	sw  t0,0(v0)
         li  t1,htoll(0x00000449)
@@ -643,7 +643,7 @@
 _64MBIT2:
         DBG("64 Mbit SDRAM detected...\r\n")
         /* In 64 Mbit SDRAM we must use 4 way bank interleaving!!! */
-        li  v0,0xb4000814      
+        li  v0,0xb4000814
 	li  t0,htoll(64)
 	sw  t0,0(v0)
         li  t1,htoll(0x00000c69)
@@ -652,7 +652,7 @@
 _128MBIT2:
         DBG("128 Mbit SDRAM detected...\r\n")
         /* In 128 Mbit SDRAM we must use 4 way bank interleaving!!! */
-        li  v0,0xb4000814      
+        li  v0,0xb4000814
 	li  t0,htoll(128)
 	sw  t0,0(v0)
         li  t1,htoll(0x00000c69)
@@ -661,104 +661,104 @@
 _256MBIT2:
         DBG("256 Mbit SDRAM detected...\r\n")
         /* In 256 Mbit SDRAM we must use 4 way bank interleaving!!! */
-        li  v0,0xb4000814      
+        li  v0,0xb4000814
 	li  t0,htoll(256)
 	sw  t0,0(v0)
         li  t1,htoll(0x00004c69)
         b   _INIT_SDRAM
 
-_INIT_SDRAM:        
+_INIT_SDRAM:
         /* Restore defaults */
         DBG("Restoring defaults...\r\n")
-        li  v0,0xb4000404      
+        li  v0,0xb4000404
 	li  t0,htoll(0x07)
 	sw  t0,0(v0)
-        li  v0,0xb4000408      
+        li  v0,0xb4000408
 	li  t0,htoll(0x08)
 	sw  t0,0(v0)
-        li  v0,0xb400040c      
+        li  v0,0xb400040c
 	li  t0,htoll(0x0f)
 	sw  t0,0(v0)
-        li  v0,0xb4000410      
+        li  v0,0xb4000410
 	li  t0,htoll(0x10)
-	sw  t0,0(v0)   
-        li  v0,0xb4000414      
+	sw  t0,0(v0)
+        li  v0,0xb4000414
 	li  t0,htoll(0x17)
 	sw  t0,0(v0)
-        li  v0,0xb4000418      
+        li  v0,0xb4000418
 	li  t0,htoll(0x18)
-	sw  t0,0(v0)   
-        li  v0,0xb400041c      
+	sw  t0,0(v0)
+        li  v0,0xb400041c
 	li  t0,htoll(0x1f)
 	sw  t0,0(v0)
-        li  v0,0xb4000010      
+        li  v0,0xb4000010
 	li  t0,htoll(0x07)
 	sw  t0,0(v0)
-        li  v0,0xb4000018      
+        li  v0,0xb4000018
 	li  t0,htoll(0x008)
 	sw  t0,0(v0)
-        li  v0,0xb4000020      
+        li  v0,0xb4000020
 	li  t0,htoll(0x0f)
-	sw  t0,0(v0)        
-        
+	sw  t0,0(v0)
+
         li  v0,0xb400044c
         sw  t1,8(v0)  # Bank2
         sw  t1,12(v0) # Bank3
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x3)
 	sw  t0,0(v0)
-        
+
         li  v0,0xa0000000
         li  t0,0
         sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x3)
 	sw  t0,0(v0)
-        
+
         li  v0,0xa0800000
         li  t0,0
         sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x3)
 	sw  t0,0(v0)
-        
+
         li  v0,0xa1000000
         li  t0,0
         sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x3)
 	sw  t0,0(v0)
-        
+
         li  v0,0xa1800000
         li  t0,0
         sw  t0,0(v0)
-        
-        li  v0,0xb4000474        
+
+        li  v0,0xb4000474
 	li  t0,htoll(0x0)
 	sw  t0,0(v0)
-        
+
         /*********************************************************************/
         /************************* SDRAM initializing ************************/
         /******************************* END *********************************/
-        
+
         li      p64011, PA_TO_KVA1(GT64011_BASE)
-        
+
         li      t0,htoll(0x00000000)    /* RAS[1:0] low decode address */
         sw      t0,0x008(p64011)
 
@@ -794,8 +794,8 @@
 
         li      t0,htoll(0x0000001f)    /* RAS[3] High Decode Address <<<<<< 1*/
         sw      t0,0x41c(p64011)
-	
-#ifdef DBGSBD	
+
+#ifdef DBGSBD
 #define DREG(str,rname) \
 	DBG(str); \
 	DBG(":\t") ;			\
@@ -803,7 +803,7 @@
 	HTOLL(a0,t0) ;			\
 	jal	_dbghex ;		\
 	DBG("\r\n")
-	
+
 	DBG("GT-64120 settings:\r\n")
         DREG("DRAMPAR_BANK0   (44c)",GT_DRAMPAR_BANK0)
         DREG("DRAMPAR_BANK1   (450)",GT_DRAMPAR_BANK1)
@@ -828,7 +828,7 @@
         DREG("GT_DEVPAR_BANK3 (468)",GT_DEVPAR_BANK3)
         DREG("GT_IPCI_TOR     (c04)",GT_IPCI_TOR)
 #endif
-		
+
 	/* we can now initialise the caches for a fast clear_mem */
 	SBD_DISPLAY ('C','A','C','H',CHKPNT_CACH)
 	DBG("init_cache\r\n")
@@ -839,7 +839,7 @@
 	/* initialise tlb */
 	SBD_DISPLAY ('I','T','L','B', CHKPNT_ITLB)
 	DBG("init_tlb\r\n")
-//	bal	init_tlb 
+//	bal	init_tlb
 
 //	DBG("sbdreset completed\r\n")
 //	move	ra,rasave
@@ -928,7 +928,7 @@
 
 LEAF(sbdberrenb)
 	mfc0	v0,C0_SR
-	li	t0,SR_DE	
+	li	t0,SR_DE
 	bnez	a0,1f
 	or	t1,v0,t0	# disable cache/parity errors (SR_DE = 1)
 	b	2f
@@ -966,7 +966,7 @@
 1:	mul	a0,t1
 	subu	a0,15		# approx number of loops so far
 
-	.set	noreorder	
+	.set	noreorder
 	.set	nomacro
 	nop
 2:	bgtz	a0,2b
@@ -981,7 +981,7 @@
 
 
 LEAF(mips_cycle)
-	.set	noreorder	
+	.set	noreorder
 	.set	nomacro
 1:	bgtz	a0,1b
 	subu	a0,1
@@ -992,7 +992,7 @@
 
 LEAF(init_ns16550_chan_b)
 	# enable 16550 fifo if it is there
-        li      a0,NS16550_CHANB 
+        li      a0,NS16550_CHANB
         li	t0,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
 	sb	t0,FIFO(a0)
 
@@ -1002,25 +1002,25 @@
 	li	t0,CFCR_DLAB			# select brtc divisor
 	sb	t0,CFCR(a0)
 	sb	t2,DATA(a0)			# store divisor lsb
-	srl	t2,8	
+	srl	t2,8
 	sb	t2,IER(a0)			# store divisor msb
 
 	li	t0,CFCR_8BITS			# set 8N1 mode
 	sb	t0,CFCR(a0)
 
-	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS 
+	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS
   	sb	t0,MCR(a0)
- 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!) 
+ 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!)
 	sb	t0,IER(a0)
 
 	move	v0,zero				# indicate success
 	j	ra
-	
+
 END(init_ns16550_chan_b)
 
 LEAF(init_ns16550_chan_a)
 	# enable 16550 fifo if it is there
-        li      a0,NS16550_CHANA 
+        li      a0,NS16550_CHANA
         li	t0,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
 	sb	t0,FIFO(a0)
 
@@ -1030,20 +1030,20 @@
 	li	t0,CFCR_DLAB			# select brtc divisor
 	sb	t0,CFCR(a0)
 	sb	t2,DATA(a0)			# store divisor lsb
-	srl	t2,8	
+	srl	t2,8
 	sb	t2,IER(a0)			# store divisor msb
 
 	li	t0,CFCR_8BITS			# set 8N1 mode
 	sb	t0,CFCR(a0)
 
-	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS 
+	li	t0,MCR_DTR|MCR_RTS # Galileo |MCR_IENABLE	# enable DTR & RTS
   	sb	t0,MCR(a0)
- 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!) 
+ 	li	t0,0 # Galileo IER_ERXRDY			# enable receive interrupt(!)
 	sb	t0,IER(a0)
 
 	move	v0,zero				# indicate success
 	j	ra
-	
+
 END(init_ns16550_chan_a)
 
 #endif /* EVB64120A */

FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)