patch-2.4.2 linux/arch/i386/kernel/setup.c

• Lines: 96
• Date: Fri Feb 16 16:02:37 2001
• Orig file: v2.4.1/linux/arch/i386/kernel/setup.c
• Orig date: Sat Feb 3 19:51:22 2001

diff -u --recursive --new-file v2.4.1/linux/arch/i386/kernel/setup.c linux/arch/i386/kernel/setup.c
@@ -71,7 +71,7 @@
 #include <linux/stddef.h>
 #include <linux/unistd.h>
 #include <linux/ptrace.h>
-#include <linux/malloc.h>
+#include <linux/slab.h>
 #include <linux/user.h>
 #include <linux/a.out.h>
 #include <linux/tty.h>
@@ -1104,6 +1104,9 @@
 /*
  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
  * order to identify the Cyrix CPU model after we're out of setup.c
+ *
+ * Actually since bugs.h doesnt even reference this perhaps someone should
+ * fix the documentation ???
  */
 unsigned char Cx86_dir0_msb __initdata = 0;
 
@@ -1129,6 +1132,8 @@
  * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
  * BIOSes for compatability with DOS games.  This makes the udelay loop
  * work correctly, and improves performance.
+ *
+ * FIXME: our newer udelay uses the tsc. We dont need to frob with SLOP
  */
 
 extern void calibrate_delay(void) __init;
@@ -1401,6 +1406,7 @@
 					wrmsr (0x1107, lo, hi);
 
 					set_bit(X86_FEATURE_CX8, &c->x86_capability);
+					set_bit(X86_FEATURE_3DNOW, &c->x86_capability);
 
 					get_model_name(c);
 					display_cacheinfo(c);
@@ -1565,12 +1571,10 @@
 				case 4:
 					if ( c->x86 > 6 && dl ) {
 						/* P4 family */
-						if ( dl ) {
-							/* L3 cache */
-							cs = 128 << (dl-1);
-							l3 += cs;
-							break;
-						}
+						/* L3 cache */
+						cs = 128 << (dl-1);
+						l3 += cs;
+						break;
 					}
 					/* else same as 8 - fall through */
 				case 8:
@@ -1870,8 +1874,34 @@
 
 	/* Detect Cyrix with disabled CPUID */
 	if ( c->x86 == 4 && test_cyrix_52div() ) {
+		unsigned char dir0, dir1;
+		
 		strcpy(c->x86_vendor_id, "CyrixInstead");
 	        c->x86_vendor = X86_VENDOR_CYRIX;
+	        
+	        /* Actually enable cpuid on the older cyrix */
+	    
+	    	/* Retrieve CPU revisions */
+	    	
+		do_cyrix_devid(&dir0, &dir1);
+
+		dir0>>=4;		
+		
+		/* Check it is an affected model */
+		
+   	        if (dir0 == 5 || dir0 == 3)
+   	        {
+			unsigned char ccr3, ccr4;
+
+			printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
+			cli();
+			ccr3 = getCx86(CX86_CCR3);
+			setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
+			ccr4 = getCx86(CX86_CCR4);
+			setCx86(CX86_CCR4, ccr4 | 0x80);          /* enable cpuid  */
+			setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
+			sti();
+		}
 	} else
 
 	/* Detect NexGen with old hypercode */
@@ -1914,7 +1944,6 @@
 		      (int *)&c->x86_vendor_id[4]);
 		
 		get_cpu_vendor(c);
-
 		/* Initialize the standard set of capabilities */
 		/* Note that the vendor-specific code below might override */