patch-2.4.19 linux-2.4.19/drivers/mtd/maps/l440gx.c
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- Lines: 148
- Date:
Fri Aug 2 17:39:44 2002
- Orig file:
linux-2.4.18/drivers/mtd/maps/l440gx.c
- Orig date:
Thu Oct 4 15:14:59 2001
diff -urN linux-2.4.18/drivers/mtd/maps/l440gx.c linux-2.4.19/drivers/mtd/maps/l440gx.c
@@ -1,7 +1,9 @@
/*
- * $Id: l440gx.c,v 1.7 2001/10/02 15:05:14 dwmw2 Exp $
+ * $Id: l440gx.c,v 1.8 2002/01/10 20:27:40 eric Exp $
*
* BIOS Flash chip on Intel 440GX board.
+ *
+ * Bugs this currently does not work under linuxBIOS.
*/
#include <linux/module.h>
@@ -12,12 +14,14 @@
#include <linux/mtd/map.h>
#include <linux/config.h>
+#define PIIXE_IOBASE_RESOURCE 11
#define WINDOW_ADDR 0xfff00000
#define WINDOW_SIZE 0x00100000
#define BUSWIDTH 1
-#define IOBASE 0xc00
+static u32 iobase;
+#define IOBASE iobase
#define TRIBUF_PORT (IOBASE+0x37)
#define VPP_PORT (IOBASE+0x28)
@@ -66,12 +70,17 @@
memcpy_toio(map->map_priv_1 + to, from, len);
}
+/* Is this really the vpp port? */
void l440gx_set_vpp(struct map_info *map, int vpp)
{
unsigned long l;
l = inl(VPP_PORT);
- l = vpp?(l | 1):(l & ~1);
+ if (vpp) {
+ l |= 1;
+ } else {
+ l &= ~1;
+ }
outl(l, VPP_PORT);
}
@@ -87,44 +96,86 @@
write16: l440gx_write16,
write32: l440gx_write32,
copy_to: l440gx_copy_to,
+#if 0
+ /* FIXME verify that this is the
+ * appripriate code for vpp enable/disable
+ */
set_vpp: l440gx_set_vpp
+#endif
};
static int __init init_l440gx(void)
{
- struct pci_dev *dev;
- unsigned char b;
- __u16 w;
+ struct pci_dev *dev, *pm_dev;
+ struct resource *pm_iobase;
+ __u16 word;
+
+ dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_0, NULL);
- dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
- NULL);
- if (!dev) {
+ pm_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
+
+ if (!dev || !pm_dev) {
printk(KERN_NOTICE "L440GX flash mapping: failed to find PIIX4 ISA bridge, cannot continue\n");
return -ENODEV;
}
- l440gx_map.map_priv_1 = (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE);
+ l440gx_map.map_priv_1 = (unsigned long)ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
if (!l440gx_map.map_priv_1) {
- printk("Failed to ioremap L440GX flash region\n");
+ printk(KERN_WARNING "Failed to ioremap L440GX flash region\n");
return -ENOMEM;
}
+ printk(KERN_NOTICE "window_addr = 0x%08lx\n", (unsigned long)l440gx_map.map_priv_1);
+
+ /* Setup the pm iobase resource
+ * This code should move into some kind of generic bridge
+ * driver but for the moment I'm content with getting the
+ * allocation correct.
+ */
+ pm_iobase = &pm_dev->resource[PIIXE_IOBASE_RESOURCE];
+ if (!(pm_iobase->flags & IORESOURCE_IO)) {
+ pm_iobase->name = "pm iobase";
+ pm_iobase->start = 0;
+ pm_iobase->end = 63;
+ pm_iobase->flags = IORESOURCE_IO;
+
+ /* Put the current value in the resource */
+ pci_read_config_dword(pm_dev, 0x40, &iobase);
+ iobase &= ~1;
+ pm_iobase->start += iobase & ~1;
+ pm_iobase->end += iobase & ~1;
+
+ /* Allocate the resource region */
+ if (pci_assign_resource(pm_dev, PIIXE_IOBASE_RESOURCE) != 0) {
+ printk(KERN_WARNING "Could not allocate pm iobase resource\n");
+ iounmap((void *)l440gx_map.map_priv_1);
+ return -ENXIO;
+ }
+ }
+ /* Set the iobase */
+ iobase = pm_iobase->start;
+ pci_write_config_dword(pm_dev, 0x40, iobase | 1);
+
+
/* Set XBCS# */
- pci_read_config_word(dev, 0x4e, &w);
- w |= 0x4;
- pci_write_config_word(dev, 0x4e, w);
+ pci_read_config_word(dev, 0x4e, &word);
+ word |= 0x4;
+ pci_write_config_word(dev, 0x4e, word);
+
+ /* Supply write voltage to the chip */
+ l440gx_set_vpp(&l440gx_map, 1);
/* Enable the gate on the WE line */
- b = inb(TRIBUF_PORT);
- b |= 1;
- outb(b, TRIBUF_PORT);
+ outb(inb(TRIBUF_PORT) & ~1, TRIBUF_PORT);
printk(KERN_NOTICE "Enabled WE line to L440GX BIOS flash chip.\n");
- mymtd = do_map_probe("jedec", &l440gx_map);
+ mymtd = do_map_probe("jedec_probe", &l440gx_map);
if (!mymtd) {
printk(KERN_NOTICE "JEDEC probe on BIOS chip failed. Using ROM\n");
mymtd = do_map_probe("map_rom", &l440gx_map);
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