patch-2.4.19 linux-2.4.19/arch/mips/mips-boards/generic/mipsIRQ.S

• Lines: 60
• Date: Fri Aug 2 17:39:43 2002
• Orig file: linux-2.4.18/arch/mips/mips-boards/generic/mipsIRQ.S
• Orig date: Fri Apr 13 20:26:07 2001

diff -urN linux-2.4.18/arch/mips/mips-boards/generic/mipsIRQ.S linux-2.4.19/arch/mips/mips-boards/generic/mipsIRQ.S
@@ -56,6 +56,10 @@
  *             6        Hardware (ignored)
  *             7        R4k timer (what we use)
  *
+ * Note: On the SEAD board thing are a little bit different.
+ *       Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
+ *       wired to UART1.
+ *	
  * We handle the IRQ according to _our_ priority which is:
  *
  * Highest ----     R4k Timer
@@ -90,14 +94,21 @@
 	 nop
 
 1:
+#if defined(CONFIG_MIPS_SEAD) 	
 	beq	a0, zero, 1f
-	 nop
-
+	 andi	a0, s0, CAUSEF_IP3	# delay slot, check hw1 interrupt
+#else
+	beq	a0, zero, 1f		# delay slot, check hw3 interrupt
+ 	 andi	a0, s0, CAUSEF_IP5	
+#endif
+	
 	/* Wheee, combined hardware level zero interrupt. */
 #if defined(CONFIG_MIPS_ATLAS)
 	jal	atlas_hw0_irqdispatch
 #elif defined(CONFIG_MIPS_MALTA)
 	jal	malta_hw0_irqdispatch
+#elif defined(CONFIG_MIPS_SEAD)
+	jal	sead_hw0_irqdispatch
 #else
 #error "MIPS board not supported\n"	
 #endif
@@ -107,6 +118,24 @@
 	 nop				# delay slot
 
 1:
+#if defined(CONFIG_MIPS_SEAD) 	
+	beq	a0, zero, 1f
+	 andi	a0, s0, CAUSEF_IP5	# delay slot, check hw3 interrupt
+	jal	sead_hw1_irqdispatch
+	 move	a0, sp			# delay slot	
+	j	ret_from_irq
+	 nop				# delay slot
+1:	
+#endif	
+
+	beq	a0, zero, 1f            # check hw3 (coreHI) interrupt
+	 nop
+	jal	corehi_irqdispatch
+	 move	a0, sp			
+	j	ret_from_irq
+	 nop				
+1:	
+
 	/*
 	 * Here by mistake?  This is possible, what can happen is that by the
 	 * time we take the exception the IRQ pin goes low, so just leave if