patch-2.4.19 linux-2.4.19/arch/mips/ddb5xxx/ddb5477/pci_ops.c

• Lines: 164
• Date: Fri Aug 2 17:39:43 2002
• Orig file: linux-2.4.18/arch/mips/ddb5xxx/ddb5477/pci_ops.c
• Orig date: Sun Sep 9 10:43:01 2001

diff -urN linux-2.4.18/arch/mips/ddb5xxx/ddb5477/pci_ops.c linux-2.4.19/arch/mips/ddb5xxx/ddb5477/pci_ops.c
@@ -26,7 +26,8 @@
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
+
 #include <asm/ddb5xxx/ddb5xxx.h>
 
 /*
@@ -72,14 +73,11 @@
         u32 virt_addr = swap->config_base;
 	u32 option;
 
-	/* [jsun] hack for testing */
-	// if (slot_num == 4) slot_num = 0;
-
 	/* minimum pdar (window) size is 2MB */
-	MIPS_ASSERT(swap->config_size >= (2 << 20));
+	db_assert(swap->config_size >= (2 << 20));
 
-	MIPS_ASSERT(slot_num < (1 << 5));
-	MIPS_ASSERT(bus < (1 << 8));
+	db_assert(slot_num < (1 << 5));
+	db_assert(bus < (1 << 8));
 
 	/* backup registers */
 	swap->pdar_backup = ddb_in32(swap->pdar);
@@ -103,7 +101,6 @@
 	} else {
 		/* type 1 config */
 		pci_addr = (bus << 16) | (slot_num << 11);
-		panic("ddb_access_config_base: we don't support type 1 config Yet");
 	}
 
 	/*
@@ -115,7 +112,7 @@
 		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
 		pciinit_offset = 0;
 	} else {
-		MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
+		db_assert( (pci_addr & (swap->config_size - 1)) == 0);
 		virt_addr = KSEG1ADDR(swap->config_base);
 		pciinit_offset = pci_addr;
 	}
@@ -142,13 +139,13 @@
 	u32 bus, slot_num, func_num;
 	u32 base;
 
-	MIPS_ASSERT((where & 3) == 0);
-	MIPS_ASSERT(where < (1 << 8));
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));
 
 	/* check if the bus is top-level */
 	if (dev->bus->parent != NULL) {
 		bus = dev->bus->number;
-		MIPS_ASSERT(bus != 0);
+		db_assert(bus != 0);
 	} else {
 		bus = 0;
 	}
@@ -169,7 +166,7 @@
         int status;
         u32 result;
 
-	MIPS_ASSERT((where & 1) == 0);
+	db_assert((where & 1) == 0);
 
         status = read_config_dword(swap, dev, where & ~3, &result);
         if (where & 2) result >>= 16;
@@ -200,13 +197,13 @@
 	u32 bus, slot_num, func_num;
 	u32 base;
 
-	MIPS_ASSERT((where & 3) == 0);
-	MIPS_ASSERT(where < (1 << 8));
+	db_assert((where & 3) == 0);
+	db_assert(where < (1 << 8));
 
 	/* check if the bus is top-level */
 	if (dev->bus->parent != NULL) {
 		bus = dev->bus->number;
-		MIPS_ASSERT(bus != 0);
+		db_assert(bus != 0);
 	} else {
 		bus = 0;
 	}
@@ -227,7 +224,7 @@
 	int status, shift=0;
 	u32 result;
 
-	MIPS_ASSERT((where & 1) == 0);
+	db_assert((where & 1) == 0);
 
 	status = read_config_dword(swap, dev, where & ~3, &result);
 	if (status != PCIBIOS_SUCCESSFUL) return status;
@@ -303,7 +300,7 @@
 	iopci_write_config_dword
 };
 
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
 void jsun_scan_pci_bus(void)
 {
 	struct pci_bus bus;
@@ -332,26 +329,26 @@
 			int i;
 
 			dev.devfn = devfn;
-			MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
-				    == PCIBIOS_SUCCESSFUL);
+			db_verify(pci_read_config_dword(&dev, 0, &temp),
+				  == PCIBIOS_SUCCESSFUL);
 			if (temp == 0xffffffff) continue;
 
 			printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8);
 
 			/* verify read word and byte */
-			MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
-				    == PCIBIOS_SUCCESSFUL);
-			MIPS_ASSERT(temp16 == (temp >> 16));
-			MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
-				    == PCIBIOS_SUCCESSFUL);
-			MIPS_ASSERT(temp8 == (temp >> 24));
-			MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
-				    == PCIBIOS_SUCCESSFUL);
-			MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));
+			db_verify(pci_read_config_word(&dev, 2, &temp16),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp16 == (temp >> 16));
+			db_verify(pci_read_config_byte(&dev, 3, &temp8),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp8 == (temp >> 24));
+			db_verify(pci_read_config_byte(&dev, 1, &temp8),
+				  == PCIBIOS_SUCCESSFUL);
+			db_assert(temp8 == ((temp >> 8) & 0xff));
 
 			for (i=0; i < 16; i++) {
-				MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
-					    == PCIBIOS_SUCCESSFUL);
+				db_verify(pci_read_config_dword(&dev, i*4, &temp),
+					  == PCIBIOS_SUCCESSFUL);
 				printk("\t%08X", temp);
 				if ((i%4) == 3) printk("\n");
 			}
@@ -374,7 +371,7 @@
 	/* for slot 5 (ext pci 1) eepro card */
 	dev.devfn = 5*8;
 	pci_read_config_dword(&dev, 0, &temp);
-	MIPS_ASSERT(temp == 0x12298086);
+	db_assert(temp == 0x12298086);
 
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE);
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0);
@@ -396,7 +393,7 @@
 	/* for slot 4 on board ether chip */
 	dev.devfn = 4*8;
 	pci_read_config_dword(&dev, 0, &temp);
-	MIPS_ASSERT(temp == 0x00191011);
+	db_assert(temp == 0x00191011);
 
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000);
 	pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE);