patch-2.4.18 linux/include/asm-ppc/heathrow.h

• Lines: 43
• Date: Wed Dec 26 16:36:12 2001
• Orig file: linux.orig/include/asm-ppc/heathrow.h
• Orig date: Mon Feb 18 20:18:40 2002

diff -Naur -X /home/marcelo/lib/dontdiff linux.orig/include/asm-ppc/heathrow.h linux/include/asm-ppc/heathrow.h
@@ -1,5 +1,5 @@
 /*
- * BK Id: SCCS/s.heathrow.h 1.7 05/17/01 18:14:24 cort
+ * BK Id: SCCS/s.heathrow.h 1.10 12/01/01 20:09:11 benh
  */
 /*
  * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
@@ -17,7 +17,9 @@
 #define HEATHROW_CONTRAST_CNTL		0x33
 
 /* offset from ohare base for feature control register */
-#define HEATHROW_FEATURE_REG		0x38
+#define HEATHROW_MBCR			0x34	/* Media bay control */
+#define HEATHROW_FCR			0x38	/* Feature control */
+#define HEATHROW_AUX_CNTL_REG		0x3c	/* Aux control */
 
 /*
  * Bits in feature control register.
@@ -30,6 +32,7 @@
 #define HRW_BAY_FLOPPY_ENABLE	0x00000010
 #define HRW_IDE0_ENABLE		0x00000020
 #define HRW_IDE0_RESET_N	0x00000040
+#define HRW_BAY_DEV_MASK	0x0000001c
 #define HRW_BAY_RESET_N		0x00000080
 #define HRW_IOBUS_ENABLE	0x00000100	/* Internal IDE ? */
 #define HRW_SCC_ENABLE		0x00000200
@@ -45,7 +48,7 @@
 #define HRW_SWIM_CLONE_FLOPPY	0x00080000	/* ??? (0) */
 #define HRW_AUD_RUN22		0x00100000	/* ??? (1) */
 #define HRW_SCSI_LINK_MODE	0x00200000	/* Read ??? (1) */
-#define HRW_ARB_BYPASS		0x00400000	/* ??? (0 on main, 1 on gatwick) */
+#define HRW_ARB_BYPASS		0x00400000	/* Disable internal PCI arbitrer */
 #define HRW_IDE1_RESET_N	0x00800000	/* Media bay */
 #define HRW_SLOW_SCC_PCLK	0x01000000	/* ??? (0) */
 #define HRW_MODEM_POWER_N	0x02000000	/* Used by internal modem on wallstreet */
@@ -60,3 +63,7 @@
 /* Those seem to be different on paddington */
 #define PADD_MODEM_POWER_N	0x00000001	/* modem power on paddington */
 #define PADD_RESET_SCC		0x02000000	/* check this please */
+
+/* Looks like Heathrow has some sort of GPIOs as well... */
+#define HRW_GPIO_MODEM_RESET	0x6d
+