patch-2.4.14 linux/drivers/scsi/cpqfcTSstructs.h

• Lines: 154
• Date: Thu Oct 25 13:53:50 2001
• Orig file: v2.4.13/linux/drivers/scsi/cpqfcTSstructs.h
• Orig date: Mon Aug 27 12:41:44 2001

diff -u --recursive --new-file v2.4.13/linux/drivers/scsi/cpqfcTSstructs.h linux/drivers/scsi/cpqfcTSstructs.h
@@ -28,10 +28,12 @@
 #define DbgDelay(secs) { int wait_time; printk( " DbgDelay %ds ", secs); \
                          for( wait_time=jiffies + (secs*HZ); \
 		         wait_time > jiffies ;) ; }
+
 #define CPQFCTS_DRIVER_VER(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
+// don't forget to also change MODULE_DESCRIPTION in cpqfcTSinit.c
 #define VER_MAJOR 2
-#define VER_MINOR 0
-#define VER_SUBMINOR 5
+#define VER_MINOR 1
+#define VER_SUBMINOR 1
 
 // Macros for kernel (esp. SMP) tracing using a PCI analyzer
 // (e.g. x86).
@@ -413,11 +415,23 @@
                          // struct is sized for largest expected cmnd (LOGIN)
 } TachLiteERQ;
 
+// for now, just 32 bit DMA, eventually 40something, with code changes
+#define CPQFCTS_DMA_MASK ((unsigned long) (0x00000000FFFFFFFF))
+
+#define TL_MAX_SG_ELEM_LEN 0x7ffff  // Max buffer length a single S/G entry
+				// may represent (a hardware limitation).  The
+				// only reason to ever change this is if you
+				// want to exercise very-hard-to-reach code in
+				// cpqfcTSworker.c:build_SEST_sglist().
+
+#define TL_DANGER_SGPAGES 7  // arbitrary high water mark for # of S/G pages
+				// we must exceed to elicit a warning indicative
+				// of EXTREMELY large data transfers or 
+				// EXTREME memory fragmentation.
+				// (means we just used up 2048 S/G elements,
+				// Never seen this is real life, only in 
+				// testing with tricked up driver.)
 
-#define TL_MAX_SGPAGES 4  // arbitrary limit to # of TL Ext. S/G pages
-                          // stores array of allocated page blocks used
-                          // in extended S/G lists.  Affects amount of static
-                          // memory consumed by driver.
 #define TL_EXT_SG_PAGE_COUNT 256  // Number of Extended Scatter/Gather a/l PAIRS
                                   // Tachyon register (IOBaseU 0x68)
                                   // power-of-2 value ONLY!  4 min, 256 max
@@ -435,6 +449,8 @@
   ULONG RSP_Len;
   ULONG RSP_Addr;
   ULONG Buff_Off;
+#define USES_EXTENDED_SGLIST(this_sest, x_ID) \
+	(!((this_sest)->u[ x_ID ].IWE.Buff_Off & 0x80000000))
   ULONG Link;
   ULONG RX_ID;
   ULONG Data_Len;
@@ -514,12 +530,14 @@
   ULONG GAddr3;
 } TachLiteTRE;
 
-typedef struct
+typedef struct ext_sg_page_ptr_t *PSGPAGES;
+typedef struct ext_sg_page_ptr_t 
 {
-  void *PoolPage[TL_MAX_SGPAGES];
-} SGPAGES, *PSGPAGES; // linked list of S/G pairs, by Exchange
-
-
+  unsigned char page[TL_EXT_SG_PAGE_BYTELEN * 2]; // 2x for alignment
+  dma_addr_t busaddr; 	// need the bus addresses and
+  unsigned int maplen;  // lengths for later pci unmapping.
+  PSGPAGES next;
+} SGPAGES; // linked list of S/G pairs, by Exchange
 
 typedef struct                  // SCSI Exchange State Table
 {
@@ -533,7 +551,7 @@
 
   TachFCHDR DataHDR[TACH_SEST_LEN]; // for SEST FCP_DATA frame hdr (no pl)
   TachFCHDR_RSP RspHDR[TACH_SEST_LEN]; // space for SEST FCP_RSP frame
-  SGPAGES sgPages[TACH_SEST_LEN]; // array of Pool-allocations
+  PSGPAGES sgPages[TACH_SEST_LEN]; // head of linked list of Pool-allocations
   ULONG length;          // Length register
   ULONG base;            // copy of base ptr for debug
 } TachSEST;
@@ -642,6 +660,8 @@
 {
   void *BaseAllocated;  // address as allocated from O/S;
   unsigned long AlignedAddress; // aligned address (used by Tachyon DMA)
+  dma_addr_t dma_handle;
+  size_t size;
 } ALIGNED_MEM;
 
 
@@ -785,6 +805,8 @@
   TachLiteSFQ *SFQ;          // Single Frame Queue
   TachSEST *SEST;            // SCSI Exchange State Table
 
+  dma_addr_t exch_dma_handle;
+
   // these function pointers are for "generic" functions, which are
   // replaced with Host Bus Adapter types at
   // runtime.
@@ -834,8 +856,9 @@
 // define misc functions 
 int cpqfcTSGetLPSM( PTACHYON fcChip, char cErrorString[]);
 int cpqfcTSDecodeGBICtype( PTACHYON fcChip, char cErrorString[]);
-void* fcMemManager( ALIGNED_MEM *dyn_mem_pair, ULONG n_alloc, ULONG ab,
-                   ULONG ulAlignedAddress);
+void* fcMemManager( struct pci_dev *pdev,
+		ALIGNED_MEM *dyn_mem_pair, ULONG n_alloc, ULONG ab,
+                   ULONG ulAlignedAddress, dma_addr_t *dma_handle);
 
 void BigEndianSwap(  UCHAR *source, UCHAR *dest,  USHORT cnt);
 
@@ -903,6 +926,7 @@
   ALIGNED_MEM dynamic_mem[DYNAMIC_ALLOCATIONS];
 
   struct pci_dev *PciDev;
+  dma_addr_t fcLQ_dma_handle;
 
   Scsi_Cmnd *LinkDnCmnd[CPQFCTS_REQ_QUEUE_LEN]; // collects Cmnds during LDn
                                                 // (for Acceptable targets)
@@ -964,6 +988,7 @@
   LONG ExchangeID );
 
 void cpqfcTSCompleteExchange( 
+       struct pci_dev *pcidev,
        PTACHYON fcChip, 
        ULONG exchange_ID);
 
@@ -993,9 +1018,10 @@
 void fcSestReset(
    CPQFCHBA *);
 
-
-
-
+void cpqfc_pci_unmap(struct pci_dev *pcidev, 
+	Scsi_Cmnd *cmd, 
+	PTACHYON fcChip, 
+	ULONG x_ID);
 
 extern const UCHAR valid_al_pa[];
 extern const int number_of_al_pa;
@@ -1376,6 +1402,12 @@
 
 	ULONG	s_id;
 } ADISC_PAYLOAD;
+
+struct ext_sg_entry_t {
+	__u32 len:18;		/* buffer length, bits 0-17 */
+	__u32 uba:13;		/* upper bus address bits 18-31 */
+	__u32 lba;		/* lower bus address bits 0-31 */
+}; 
 
 // J. McCarty's LINK.H
 //