patch-2.4.14 linux/arch/arm/mm/proc-arm920.S

• Lines: 247
• Date: Thu Oct 25 13:53:46 2001
• Orig file: v2.4.13/linux/arch/arm/mm/proc-arm920.S
• Orig date: Mon Aug 27 12:41:38 2001

diff -u --recursive --new-file v2.4.13/linux/arch/arm/mm/proc-arm920.S linux/arch/arm/mm/proc-arm920.S
@@ -73,7 +73,7 @@
 	sbc	r1, r1, r1			@ r1 = C - 1
 	and	r3, r3, #255
 	mov	pc, lr
-
+	
 /*
  * cpu_arm920_check_bugs()
  */
@@ -150,7 +150,7 @@
 	mov	r2, #1
 cpu_arm920_cache_clean_invalidate_all_r2:
 	mov	ip, #0
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
 #else
 /*
@@ -180,21 +180,33 @@
  * end:   Area end address
  * flags: nonzero for I cache as well
  */
-	.align	5
+		.align	5
 ENTRY(cpu_arm920_cache_clean_invalidate_range)
 	bic	r0, r0, #DCACHELINESIZE - 1	@ && added by PGM
+	bic	r1, r1, #DCACHELINESIZE - 1     @ && added by DHM
 	sub	r3, r1, r0
 	cmp	r3, #MAX_AREA_SIZE
 	bgt	cpu_arm920_cache_clean_invalidate_all_r2
-1:	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+1:	teq	r2, #0
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
+	add	r0, r0, #DCACHELINESIZE
+#else
+	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
 	add	r0, r0, #DCACHELINESIZE
 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
+	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
 	add	r0, r0, #DCACHELINESIZE
+#endif
 	cmp	r0, r1
 	blt	1b
-	teq	r2, #0
-	movne	r0, #0
-	mcrne	p15, 0, r0, c7, c5, 0		@ invalidate I cache
+
+	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
 /*
@@ -207,10 +219,17 @@
 	.align	5
 ENTRY(cpu_arm920_flush_ram_page)
 	mov	r1, #PAGESIZE
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
+1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
+	add	r0, r0, #DCACHELINESIZE
+#else
 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
 	add	r0, r0, #DCACHELINESIZE
 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
 	add	r0, r0, #DCACHELINESIZE
+#endif
 	subs	r1, r1, #2 * DCACHELINESIZE
 	bne	1b
 	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
@@ -231,11 +250,14 @@
  */
 	.align	5
 ENTRY(cpu_arm920_dcache_invalidate_range)
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
 	tst	r0, #DCACHELINESIZE - 1
-	bic	r0, r0, #DCACHELINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
 	tst	r1, #DCACHELINESIZE - 1
 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
+#endif		@ clean D entry
+	bic	r0, r0, #DCACHELINESIZE - 1
+	bic	r1, r1, #DCACHELINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
 	add	r0, r0, #DCACHELINESIZE
 	cmp	r0, r1
@@ -254,18 +276,21 @@
  */
 	.align	5
 ENTRY(cpu_arm920_dcache_clean_range)
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
 	bic	r0, r0, #DCACHELINESIZE - 1
 	sub	r1, r1, r0
 	cmp	r1, #MAX_AREA_SIZE
 	mov	r2, #0
 	bgt	cpu_arm920_cache_clean_invalidate_all_r2
 
+	bic	r1, r1, #DCACHELINESIZE -1
+	add	r1, r1, #DCACHELINESIZE
+
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #DCACHELINESIZE
-	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
-	add	r0, r0, #DCACHELINESIZE
-	subs	r1, r1, #2 * DCACHELINESIZE
+	subs	r1, r1, #DCACHELINESIZE
 	bpl	1b
+#endif
 	mcr	p15, 0, r2, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
@@ -284,7 +309,7 @@
  */
 	.align	5
 ENTRY(cpu_arm920_dcache_clean_page)
-#ifndef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
 	mov	r1, #PAGESIZE
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #DCACHELINESIZE
@@ -305,7 +330,7 @@
  */
 	.align	5
 ENTRY(cpu_arm920_dcache_clean_entry)
-#ifndef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 #endif
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
@@ -318,22 +343,44 @@
  *
  * invalidate a range of virtual addresses from the Icache
  *
+ * This is a little misleading, it is not intended to clean out
+ * the i-cache but to make sure that any data written to the
+ * range is made consistant.  This means that when we execute code
+ * in that region, everything works as we expect.
+ *
+ * This generally means writing back data in the Dcache and
+ * write buffer and flushing the Icache over that region
+ *
  * start: virtual start address
  * end:   virtual end address
+ *
+ * NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to
+ * loop twice, once for i-cache, once for d-cache)
  */
 	.align	5
 ENTRY(cpu_arm920_icache_invalidate_range)
-1:	mcr	p15, 0, r0, c7, c10, 1		@ Clean D entry
-	add	r0, r0, #DCACHELINESIZE
-	cmp	r0, r1
-	blo	1b
+	bic	r0, r0, #ICACHELINESIZE - 1	@ Safety check
+	sub	r1, r1, r0
+	cmp	r1, #MAX_AREA_SIZE
+	bgt	cpu_arm920_cache_clean_invalidate_all_r2
+
+	bic	r1, r1, #ICACHELINESIZE - 1
+	add	r1, r1, #ICACHELINESIZE
+
+1:	mcr	p15, 0, r0, c7, c5, 1		@ Clean I entry
+	mcr	p15, 0, r0, c7, c10, 1		@ Clean D entry
+	add	r0, r0, #ICACHELINESIZE
+	subs	r1, r1, #ICACHELINESIZE
+	bne	1b
+
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
+	mov	pc, lr
+
 ENTRY(cpu_arm920_icache_invalidate_page)
 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
 	mov	pc, lr
 
-
 /* ================================== TLB ================================= */
 
 /*
@@ -360,6 +407,12 @@
 ENTRY(cpu_arm920_tlb_invalidate_range)
 	mov	r3, #0
 	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
+
+	mov	r3, #PAGESIZE
+	sub	r3, r3, #1
+	bic 	r0, r0, r3
+	bic	r1, r1, r3
+
 1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
 	mcr	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
 	add	r0, r0, #PAGESIZE
@@ -396,7 +449,7 @@
 	.align	5
 ENTRY(cpu_arm920_set_pgd)
 	mov	ip, #0
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
 	/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
 #else
@@ -429,7 +482,7 @@
  */
 	.align	5
 ENTRY(cpu_arm920_set_pmd)
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
 	eor	r2, r1, #0x0a			@ C & Section
 	tst	r2, #0x0b
 	biceq	r1, r1, #4			@ clear bufferable bit
@@ -463,8 +516,8 @@
 	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
 	movne	r2, #0
 
-#ifdef CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH
-	eor	r3, r1, #0x0a			@ C & small page?
+#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
+	eor	r3, r2, #0x0a			@ C & small page?
 	tst	r3, #0x0b
 	biceq	r2, r2, #4
 #endif
@@ -476,9 +529,9 @@
 
 
 cpu_manu_name:
-	.asciz	"ARM/VLSI"
+	.asciz	"ARM/CIRRUS"
 ENTRY(cpu_arm920_name)
-	.ascii	"Arm920"
+	.ascii	"Arm920T"
 #if defined(CONFIG_CPU_ARM920_CPU_IDLE)
 	.ascii	"s"
 #endif
@@ -487,7 +540,7 @@
 #endif
 #if defined(CONFIG_CPU_ARM920_D_CACHE_ON)
 	.ascii	"d"
-#if defined(CONFIG_CPU_ARM920_FORCE_WRITE_THROUGH)
+#if defined(CONFIG_CPU_ARM920_WRITETHROUGH)
 	.ascii	"(wt)"
 #else
 	.ascii	"(wb)"