patch-2.4.10 linux/arch/mips/dec/int-handler.S

• Lines: 142
• Date: Sun Sep 9 10:43:01 2001
• Orig file: v2.4.9/linux/arch/mips/dec/int-handler.S
• Orig date: Fri Jun 25 17:40:12 1999

diff -u --recursive --new-file v2.4.9/linux/arch/mips/dec/int-handler.S linux/arch/mips/dec/int-handler.S
@@ -2,6 +2,7 @@
  * arch/mips/dec/int-handler.S
  *
  * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
+ * Copyright (C) 2000  Maciej W. Rozycki
  *
  * Written by Ralf Baechle and Andreas Busse, modified for DECStation
  * support by Paul Antoine and Harald Koerfgen.
@@ -16,6 +17,11 @@
 #include <asm/stackframe.h>
 #include <asm/addrspace.h>
 
+#include <asm/dec/kn01.h>
+#include <asm/dec/kn02.h>
+#include <asm/dec/kn02xa.h>
+#include <asm/dec/kn03.h>
+#include <asm/dec/ioasic_addrs.h>
 #include <asm/dec/interrupts.h>
 
 
@@ -24,8 +30,6 @@
 /*
  * decstation_handle_int: Interrupt handler for DECStations
  *
- * FIXME: Detection of spurious interrupts not yet implemented!
- *
  * We follow the model in the Indy interrupt code by David Miller, where he
  * says: a lot of complication here is taken away because:
  *
@@ -139,12 +143,12 @@
 		la	t1,cpu_mask_tbl
 		and	t0,t2			# isolate allowed ones
 
-		/* insert detection of spurious interrupts here */
+		beqz	t0,spurious
 
 		/*
 		 * Find irq with highest priority
 		 */
-1:		lw	t2,(t1)
+1:		 lw	t2,(t1)
 		move	t3,t0
 		and	t3,t2
 		beq	t3,zero,1b
@@ -156,18 +160,18 @@
 		lw	a0,%lo(cpu_irq_nr-cpu_mask_tbl-PTRSIZE)(t1)
 		lw	t0,%lo(cpu_ivec_tbl-cpu_mask_tbl-PTRSIZE)(t1)
 		bgez	a0, handle_it		# irq_nr >= 0?
-						# irq_nr < 0: a0 contains an address
-		nop
+						# irq_nr < 0: t0 contains an address
+		 nop
 		jr	t0
 		 nop				# delay slot
 
 /*
  * Handle "IRQ Controller" Interrupts
  * Masked Interrupts are still visible and have to be masked "by hand".
- * %hi(KN02_CSR_ADDR) does not work so all addresses are hardcoded :-(.
  */
 		EXPORT(kn02_io_int)
-kn02_io_int:	lui	t0,0xbff0		# get interrupt status and mask
+kn02_io_int:					# 3max
+		lui	t0,KN02_CSR_ADDR>>16	# get interrupt status and mask
 		lw	t0,(t0)
 		la	t1,asic_mask_tbl
 		move	t3,t0
@@ -176,27 +180,32 @@
 		 and	t0,t3			# mask out allowed ones
 
 		EXPORT(kn03_io_int)
-kn03_io_int:	lui	t2,0xbf84		# upper part of IOASIC Address
-		lw	t0,0x0110(t2)		# get status: IOASIC isr
-		lw	t3,0x0120(t2)		# get mask:   IOASIC isrm
+kn03_io_int:					# 3max+
+		lui	t2,KN03_IOASIC_BASE>>16	# upper part of IOASIC Address
+		lw	t0,SIR(t2)		# get status: IOASIC isr
+		lw	t3,SIMR(t2)		# get mask:   IOASIC isrm
 		la	t1,asic_mask_tbl
 		b	find_int
 		 and	t0,t3			# mask out allowed ones
 
-		EXPORT(kn02ba_io_int)
-kn02ba_io_int:	lui	t2,0xbc04		
-		lw	t0,0x0110(t2)		# IOASIC isr, works for maxine also
-		lw	t3,0x0120(t2)		# IOASIC isrm
+		EXPORT(kn02xa_io_int)
+kn02xa_io_int:					# 3min/maxine
+		lui	t2,KN02XA_IOASIC_BASE>>16		
+						# upper part of IOASIC Address
+		lw	t0,SIR(t2)		# get status: IOASIC isr
+		lw	t3,SIMR(t2)		# get mask:   IOASIC isrm
 		la	t1,asic_mask_tbl
 		and	t0,t3
 
 		/*
 		 * Find irq with highest priority
 		 */
-find_int:	lw	t2,(t1)
+find_int:	beqz	t0,spurious
+
+1:		 lw	t2,(t1)
 		move	t3,t0
 		and	t3,t2
-		beq	zero,t3,find_int
+		beq	zero,t3,1b
 		 addu	t1,PTRSIZE		# delay slot
 
 		/*
@@ -209,7 +218,10 @@
 		 move	a1,sp
 		j	ret_from_irq
 		 nop
-		
+
+spurious:
+		j	spurious_interrupt
+		 nop
 		END(decstation_handle_int)
 /*
   * Interrupt routines common to all DECStations first.
@@ -218,14 +230,6 @@
 dec_intr_fpu:	PANIC("Unimplemented FPU interrupt handler")
 
 /*
- * Halt interrupt
- */
-		EXPORT(intr_halt)
-intr_halt:	la	k0,0xbc000000
-		jr	k0
-		 nop
-
-/*
  * Generic unimplemented interrupt routines - ivec_tbl is initialised to
  * point all interrupts here.  The table is then filled in by machine-specific
  * initialisation in dec_setup().
@@ -358,5 +362,3 @@
 		.word	0
 		.word	0
 		.word	0xffffffff		# EOL
-
-