patch-2.3.99-pre2 linux/include/asm-alpha/core_cia.h
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- Lines: 650
- Date:
Sun Mar 19 10:26:21 2000
- Orig file:
v2.3.99-pre1/linux/include/asm-alpha/core_cia.h
- Orig date:
Thu Feb 10 17:11:19 2000
diff -u --recursive --new-file v2.3.99-pre1/linux/include/asm-alpha/core_cia.h linux/include/asm-alpha/core_cia.h
@@ -4,12 +4,18 @@
/* Define to experiment with fitting everything into one 512MB HAE window. */
#define CIA_ONE_HAE_WINDOW 1
+#include <linux/config.h>
#include <linux/types.h>
#include <asm/compiler.h>
/*
- * CIA is the internal name for the 2117x chipset which provides
+ * CIA is the internal name for the 21171 chipset which provides
* memory controller and PCI access for the 21164 chip based systems.
+ * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
+ *
+ * The lineage is a bit confused, since the 21174 was reportedly started
+ * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
+ * in 21171 Pass 2 and 21172, but it also contains additional features.
*
* This file is based on:
*
@@ -22,24 +28,8 @@
*
*/
-/*------------------------------------------------------------------------**
-** **
-** EB164 I/O procedures **
-** **
-** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
-** inportbxt: 8 bits only **
-** inport: alias of inportw **
-** outport: alias of outportw **
-** **
-** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
-** inmembxt: 8 bits only **
-** inmem: alias of inmemw **
-** outmem: alias of outmemw **
-** **
-**------------------------------------------------------------------------*/
-
-
-/* CIA ADDRESS BIT DEFINITIONS
+/*
+ * CIA ADDRESS BIT DEFINITIONS
*
* 3333 3333 3322 2222 2222 1111 1111 11
* 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
@@ -78,91 +68,168 @@
#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
/*
- * 21171-CA Control and Status Registers (p4-1)
- */
-#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
-#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
-#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
-#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
-#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
-#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
-#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
-#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
-
-/*
- * 21171-CA Diagnostic Registers (p4-2)
- */
-#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
-#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
-
-/*
- * 21171-CA Performance Monitor registers (p4-3)
- */
-#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
-#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
-
-/*
- * 21171-CA Error registers (p4-3)
- */
-#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
-#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
-#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
-#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
-#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
-#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
-#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
-#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
-#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
-#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
-#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
-
-/*
- * 2117A-CA PCI Address Translation Registers.
- */
-#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
-
-#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
-#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
-#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
-
-#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
-#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
-#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
-
-#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
-#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
-#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
-
-#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
-#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
-#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
-
-/*
- * 21171-CA System configuration registers (p4-3)
+ * 21171-CA Control and Status Registers
*/
-#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
-#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
-#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
-#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
-#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
-#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
-#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
-#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
-#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
-#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
-#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
-#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
+#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
+# define CIA_REV_MASK 0xff
+#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
+#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
+# define CIA_CTRL_PCI_EN (1 << 0)
+# define CIA_CTRL_PCI_LOCK_EN (1 << 1)
+# define CIA_CTRL_PCI_LOOP_EN (1 << 2)
+# define CIA_CTRL_FST_BB_EN (1 << 3)
+# define CIA_CTRL_PCI_MST_EN (1 << 4)
+# define CIA_CTRL_PCI_MEM_EN (1 << 5)
+# define CIA_CTRL_PCI_REQ64_EN (1 << 6)
+# define CIA_CTRL_PCI_ACK64_EN (1 << 7)
+# define CIA_CTRL_ADDR_PE_EN (1 << 8)
+# define CIA_CTRL_PERR_EN (1 << 9)
+# define CIA_CTRL_FILL_ERR_EN (1 << 10)
+# define CIA_CTRL_MCHK_ERR_EN (1 << 11)
+# define CIA_CTRL_ECC_CHK_EN (1 << 12)
+# define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
+# define CIA_CTRL_COM_IDLE_BC (1 << 14)
+# define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
+# define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
+# define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
+# define CIA_CTRL_ARB_CPU_EN (1 << 18)
+# define CIA_CTRL_EN_ARB_LINK (1 << 19)
+# define CIA_CTRL_RD_TYPE_SHIFT 20
+# define CIA_CTRL_RL_TYPE_SHIFT 24
+# define CIA_CTRL_RM_TYPE_SHIFT 28
+# define CIA_CTRL_EN_DMA_RD_PERF (1 << 31)
+#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
+# define CIA_CNFG_IOA_BWEN (1 << 0)
+# define CIA_CNFG_PCI_MWEN (1 << 4)
+# define CIA_CNFG_PCI_DWEN (1 << 5)
+# define CIA_CNFG_PCI_WLEN (1 << 8)
+#define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
+#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
+#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
+#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
+#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
+# define CIA_CACK_EN_LOCK_EN (1 << 0)
+# define CIA_CACK_EN_MB_EN (1 << 1)
+# define CIA_CACK_EN_SET_DIRTY_EN (1 << 2)
+# define CIA_CACK_EN_BC_VICTIM_EN (1 << 3)
+
+
+/*
+ * 21171-CA Diagnostic Registers
+ */
+#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
+#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
+
+/*
+ * 21171-CA Performance Monitor registers
+ */
+#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
+#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
+
+/*
+ * 21171-CA Error registers
+ */
+#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
+#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
+#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
+# define CIA_ERR_COR_ERR (1 << 0)
+# define CIA_ERR_UN_COR_ERR (1 << 1)
+# define CIA_ERR_CPU_PE (1 << 2)
+# define CIA_ERR_MEM_NEM (1 << 3)
+# define CIA_ERR_PCI_SERR (1 << 4)
+# define CIA_ERR_PERR (1 << 5)
+# define CIA_ERR_PCI_ADDR_PE (1 << 6)
+# define CIA_ERR_RCVD_MAS_ABT (1 << 7)
+# define CIA_ERR_RCVD_TAR_ABT (1 << 8)
+# define CIA_ERR_PA_PTE_INV (1 << 9)
+# define CIA_ERR_FROM_WRT_ERR (1 << 10)
+# define CIA_ERR_IOA_TIMEOUT (1 << 11)
+# define CIA_ERR_LOST_CORR_ERR (1 << 16)
+# define CIA_ERR_LOST_UN_CORR_ERR (1 << 17)
+# define CIA_ERR_LOST_CPU_PE (1 << 18)
+# define CIA_ERR_LOST_MEM_NEM (1 << 19)
+# define CIA_ERR_LOST_PERR (1 << 21)
+# define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22)
+# define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23)
+# define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24)
+# define CIA_ERR_LOST_PA_PTE_INV (1 << 25)
+# define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26)
+# define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27)
+# define CIA_ERR_VALID (1 << 31)
+#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
+#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
+#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
+#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
+#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
+#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
+#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
+#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
+
+/*
+ * 21171-CA System configuration registers
+ */
+#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
+#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
+#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
+#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
+#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
+#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
+#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
+#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
+#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
+#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
+#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
+#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
+
+/*
+ * 2117A-CA PCI Address and Scatter-Gather Registers.
+ */
+#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
+
+#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
+#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
+#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
+
+#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
+#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
+#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
+
+#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
+#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
+#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
+
+#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
+#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
+#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
+
+#define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
+
+/*
+ * 2117A-CA Address Translation Registers.
+ */
+
+/* 8 tag registers, the first 4 of which are lockable. */
+#define CIA_IOC_TB_TAGn(n) \
+ (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
+
+/* 4 page registers per tag register. */
+#define CIA_IOC_TBn_PAGEm(n,m) \
+ (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
/*
* Memory spaces:
*/
-#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
-#define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
+#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
+#define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
#define CIA_IO (IDENT_ADDR + 0x8580000000UL)
#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
+#define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
+#define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
+#define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
+#define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
/*
* ALCOR's GRU ASIC registers
@@ -182,23 +249,19 @@
#define XLT_GRU_INT_REQ_BITS 0x80003fffUL
#define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
-
/*
- * Bit definitions for I/O Controller status register 0:
+ * PYXIS interrupt control registers
*/
-#define CIA_IOC_STAT0_CMD 0xf
-#define CIA_IOC_STAT0_ERR (1<<4)
-#define CIA_IOC_STAT0_LOST (1<<5)
-#define CIA_IOC_STAT0_THIT (1<<6)
-#define CIA_IOC_STAT0_TREF (1<<7)
-#define CIA_IOC_STAT0_CODE_SHIFT 8
-#define CIA_IOC_STAT0_CODE_MASK 0x7
-#define CIA_IOC_STAT0_P_NBR_SHIFT 13
-#define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff
-
-#if !CIA_ONE_HAE_WINDOW
-#define CIA_HAE_ADDRESS CIA_IOC_HAE_MEM
-#endif
+#define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
+#define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
+#define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
+#define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
+#define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
+#define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
+#define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
+#define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
+#define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
+#define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
/*
* Data structure for handling CIA machine checks.
@@ -206,52 +269,6 @@
/* System-specific info. */
struct el_CIA_sysdata_mcheck {
-#if 0
- /* ??? Where did this come from. It appears to bear no
- relation to the cia logout written in the milo sources.
- Who knows what happens in the srm console... */
- unsigned long coma_gcr;
- unsigned long coma_edsr;
- unsigned long coma_ter;
- unsigned long coma_elar;
- unsigned long coma_ehar;
- unsigned long coma_ldlr;
- unsigned long coma_ldhr;
- unsigned long coma_base0;
- unsigned long coma_base1;
- unsigned long coma_base2;
- unsigned long coma_cnfg0;
- unsigned long coma_cnfg1;
- unsigned long coma_cnfg2;
- unsigned long epic_dcsr;
- unsigned long epic_pear;
- unsigned long epic_sear;
- unsigned long epic_tbr1;
- unsigned long epic_tbr2;
- unsigned long epic_pbr1;
- unsigned long epic_pbr2;
- unsigned long epic_pmr1;
- unsigned long epic_pmr2;
- unsigned long epic_harx1;
- unsigned long epic_harx2;
- unsigned long epic_pmlt;
- unsigned long epic_tag0;
- unsigned long epic_tag1;
- unsigned long epic_tag2;
- unsigned long epic_tag3;
- unsigned long epic_tag4;
- unsigned long epic_tag5;
- unsigned long epic_tag6;
- unsigned long epic_tag7;
- unsigned long epic_data0;
- unsigned long epic_data1;
- unsigned long epic_data2;
- unsigned long epic_data3;
- unsigned long epic_data4;
- unsigned long epic_data5;
- unsigned long epic_data6;
- unsigned long epic_data7;
-#else
unsigned long cpu_err0;
unsigned long cpu_err1;
unsigned long cia_err;
@@ -263,7 +280,6 @@
unsigned long pci_err0;
unsigned long pci_err1;
unsigned long pci_err2;
-#endif
};
@@ -282,6 +298,8 @@
* get at PCI memory and I/O.
*/
+#define vucp volatile unsigned char *
+#define vusp volatile unsigned short *
#define vip volatile int *
#define vuip volatile unsigned int *
#define vulp volatile unsigned long *
@@ -325,6 +343,44 @@
mb();
}
+__EXTERN_INLINE unsigned int cia_bwx_inb(unsigned long addr)
+{
+ /* ??? I wish I could get rid of this. But there's no ioremap
+ equivalent for I/O space. PCI I/O can be forced into the
+ CIA BWX I/O region, but that doesn't take care of legacy
+ ISA crap. */
+
+ return __kernel_ldbu(*(vucp)(addr+CIA_BW_IO));
+}
+
+__EXTERN_INLINE void cia_bwx_outb(unsigned char b, unsigned long addr)
+{
+ __kernel_stb(b, *(vucp)(addr+CIA_BW_IO));
+ mb();
+}
+
+__EXTERN_INLINE unsigned int cia_bwx_inw(unsigned long addr)
+{
+ return __kernel_ldwu(*(vusp)(addr+CIA_BW_IO));
+}
+
+__EXTERN_INLINE void cia_bwx_outw(unsigned short b, unsigned long addr)
+{
+ __kernel_stw(b, *(vusp)(addr+CIA_BW_IO));
+ mb();
+}
+
+__EXTERN_INLINE unsigned int cia_bwx_inl(unsigned long addr)
+{
+ return *(vuip)(addr+CIA_BW_IO);
+}
+
+__EXTERN_INLINE void cia_bwx_outl(unsigned int b, unsigned long addr)
+{
+ *(vuip)(addr+CIA_BW_IO) = b;
+ mb();
+}
+
/*
* Memory functions. 64-bit and 32-bit accesses are done through
@@ -362,15 +418,7 @@
{
unsigned long result;
-#if !CIA_ONE_HAE_WINDOW
- unsigned long msb;
- /* Note that CIA_DENSE_MEM has no bits not masked in these
- operations, so we don't have to subtract it back out. */
- msb = addr & 0xE0000000;
- set_hae(msb);
-#endif
addr &= CIA_MEM_R1_MASK;
-
result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00);
return __kernel_extbl(result, addr & 3);
}
@@ -379,15 +427,7 @@
{
unsigned long result;
-#if !CIA_ONE_HAE_WINDOW
- unsigned long msb;
- /* Note that CIA_DENSE_MEM has no bits not masked in these
- operations, so we don't have to subtract it back out. */
- msb = addr & 0xE0000000;
- set_hae(msb);
-#endif
addr &= CIA_MEM_R1_MASK;
-
result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
return __kernel_extwl(result, addr & 3);
}
@@ -396,15 +436,7 @@
{
unsigned long w;
-#if !CIA_ONE_HAE_WINDOW
- unsigned long msb;
- /* Note that CIA_DENSE_MEM has no bits not masked in these
- operations, so we don't have to subtract it back out. */
- msb = addr & 0xE0000000;
- set_hae(msb);
-#endif
addr &= CIA_MEM_R1_MASK;
-
w = __kernel_insbl(b, addr & 3);
*(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w;
}
@@ -413,15 +445,7 @@
{
unsigned long w;
-#if !CIA_ONE_HAE_WINDOW
- unsigned long msb;
- /* Note that CIA_DENSE_MEM has no bits not masked in these
- operations, so we don't have to subtract it back out. */
- msb = addr & 0xE0000000;
- set_hae(msb);
-#endif
addr &= CIA_MEM_R1_MASK;
-
w = __kernel_inswl(b, addr & 3);
*(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w;
}
@@ -451,44 +475,117 @@
return addr + CIA_DENSE_MEM;
}
+__EXTERN_INLINE unsigned long cia_bwx_readb(unsigned long addr)
+{
+ return __kernel_ldbu(*(vucp)addr);
+}
+
+__EXTERN_INLINE unsigned long cia_bwx_readw(unsigned long addr)
+{
+ return __kernel_ldwu(*(vusp)addr);
+}
+
+__EXTERN_INLINE unsigned long cia_bwx_readl(unsigned long addr)
+{
+ return *(vuip)addr;
+}
+
+__EXTERN_INLINE unsigned long cia_bwx_readq(unsigned long addr)
+{
+ return *(vulp)addr;
+}
+
+__EXTERN_INLINE void cia_bwx_writeb(unsigned char b, unsigned long addr)
+{
+ __kernel_stb(b, *(vucp)addr);
+}
+
+__EXTERN_INLINE void cia_bwx_writew(unsigned short b, unsigned long addr)
+{
+ __kernel_stw(b, *(vusp)addr);
+}
+
+__EXTERN_INLINE void cia_bwx_writel(unsigned int b, unsigned long addr)
+{
+ *(vuip)addr = b;
+}
+
+__EXTERN_INLINE void cia_bwx_writeq(unsigned long b, unsigned long addr)
+{
+ *(vulp)addr = b;
+}
+
+__EXTERN_INLINE unsigned long cia_bwx_ioremap(unsigned long addr)
+{
+ return addr + CIA_BW_MEM;
+}
+
__EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
{
return addr >= IDENT_ADDR + 0x8000000000UL;
}
+#undef vucp
+#undef vusp
#undef vip
#undef vuip
#undef vulp
#ifdef __WANT_IO_DEF
-#define __inb cia_inb
-#define __inw cia_inw
-#define __inl cia_inl
-#define __outb cia_outb
-#define __outw cia_outw
-#define __outl cia_outl
-
-#define __readb cia_readb
-#define __readw cia_readw
-#define __writeb cia_writeb
-#define __writew cia_writew
-#define __readl cia_readl
-#define __readq cia_readq
-#define __writel cia_writel
-#define __writeq cia_writeq
-#define __ioremap cia_ioremap
-#define __is_ioaddr cia_is_ioaddr
-
-#define inb(port) \
- (__builtin_constant_p((port))?__inb(port):_inb(port))
-#define outb(x, port) \
- (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
-
-#define __raw_readl(a) __readl((unsigned long)(a))
-#define __raw_readq(a) __readq((unsigned long)(a))
-#define __raw_writel(v,a) __writel((v),(unsigned long)(a))
-#define __raw_writeq(v,a) __writeq((v),(unsigned long)(a))
+#ifdef CONFIG_ALPHA_PYXIS
+# define __inb(p) cia_bwx_inb((unsigned long)(p))
+# define __inw(p) cia_bwx_inw((unsigned long)(p))
+# define __inl(p) cia_bwx_inl((unsigned long)(p))
+# define __outb(x,p) cia_bwx_outb((x),(unsigned long)(p))
+# define __outw(x,p) cia_bwx_outw((x),(unsigned long)(p))
+# define __outl(x,p) cia_bwx_outl((x),(unsigned long)(p))
+# define __readb(a) cia_bwx_readb((unsigned long)(a))
+# define __readw(a) cia_bwx_readw((unsigned long)(a))
+# define __readl(a) cia_bwx_readl((unsigned long)(a))
+# define __readq(a) cia_bwx_readq((unsigned long)(a))
+# define __writeb(x,a) cia_bwx_writeb((x),(unsigned long)(a))
+# define __writew(x,a) cia_bwx_writew((x),(unsigned long)(a))
+# define __writel(x,a) cia_bwx_writel((x),(unsigned long)(a))
+# define __writeq(x,a) cia_bwx_writeq((x),(unsigned long)(a))
+# define __ioremap(a) cia_bwx_ioremap((unsigned long)(a))
+# define inb(p) __inb(p)
+# define inw(p) __inw(p)
+# define inl(p) __inl(p)
+# define outb(x,p) __outb((x),(p))
+# define outw(x,p) __outw((x),(p))
+# define outl(x,p) __outl((x),(p))
+# define __raw_readb(a) __readb(a)
+# define __raw_readw(a) __readw(a)
+# define __raw_readl(a) __readl(a)
+# define __raw_readq(a) __readq(a)
+# define __raw_writeb(x,a) __writeb((x),(a))
+# define __raw_writew(x,a) __writew((x),(a))
+# define __raw_writel(x,a) __writel((x),(a))
+# define __raw_writeq(x,a) __writeq((x),(a))
+#else
+# define __inb(p) cia_inb((unsigned long)(p))
+# define __inw(p) cia_inw((unsigned long)(p))
+# define __inl(p) cia_inl((unsigned long)(p))
+# define __outb(x,p) cia_outb((x),(unsigned long)(p))
+# define __outw(x,p) cia_outw((x),(unsigned long)(p))
+# define __outl(x,p) cia_outl((x),(unsigned long)(p))
+# define __readb(a) cia_readb((unsigned long)(a))
+# define __readw(a) cia_readw((unsigned long)(a))
+# define __readl(a) cia_readl((unsigned long)(a))
+# define __readq(a) cia_readq((unsigned long)(a))
+# define __writeb(x,a) cia_writeb((x),(unsigned long)(a))
+# define __writew(x,a) cia_writew((x),(unsigned long)(a))
+# define __writel(x,a) cia_writel((x),(unsigned long)(a))
+# define __writeq(x,a) cia_writeq((x),(unsigned long)(a))
+# define __ioremap(a) cia_ioremap((unsigned long)(a))
+# define __raw_readl(a) __readl(a)
+# define __raw_readq(a) __readq(a)
+# define __raw_writel(v,a) __writel((v),(a))
+# define __raw_writeq(v,a) __writeq((v),(a))
+#endif /* PYXIS */
+
+#define __is_ioaddr(a) cia_is_ioaddr((unsigned long)(a))
#endif /* __WANT_IO_DEF */
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)