patch-2.1.53 linux/arch/sparc64/kernel/rtrap.S

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Lines: 255
Date: Thu Sep 4 12:54:48 1997
Orig file: v2.1.52/linux/arch/sparc64/kernel/rtrap.S
Orig date: Mon Aug 18 18:19:45 1997

diff -u --recursive --new-file v2.1.52/linux/arch/sparc64/kernel/rtrap.S linux/arch/sparc64/kernel/rtrap.S
@@ -1,4 +1,4 @@
-/* $Id: rtrap.S,v 1.30 1997/08/10 04:49:33 davem Exp $
+/* $Id: rtrap.S,v 1.33 1997/08/21 09:13:22 davem Exp $
  * rtrap.S: Preparing for return from trap on Sparc V9.
  *
  * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
@@ -21,60 +21,76 @@
 		sethi			%hi(bh_mask), %l1
 		ldx			[%l2 + %lo(bh_active)], %l4
 		ldx			[%l1 + %lo(bh_mask)], %l7
+
 		andcc			%l4, %l7, %g0
 		be,pt			%xcc, 2f
-
 		 nop
 		call			do_bottom_half
 		 nop
 2:		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 		sethi			%hi(0xf << 20), %l4
 		andcc			%l1, TSTATE_PRIV, %l3
+
 		and			%l1, %l4, %l4
 		rdpr			%pstate, %l7
-
 		andn			%l1, %l4, %l1
 		be,pt			%icc, to_user
 		 andn			%l7, PSTATE_IE, %l7
-rt_continue:	ld			[%sp + PTREGS_OFF + PT_V9_FPRS], %l2
-		ld			[%g6 + AOFF_task_tss + AOFF_thread_ctx], %l0
-		ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
-		brnz,pn			%l2, rt_fpu_restore
-		 ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2
 
-rt_after_fpu:	ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
+		ld			[%sp + PTREGS_OFF + PT_V9_FPRS], %l2
+		andcc			%l2, FPRS_FEF, %g0
+		be,pt			%icc, rt_continue
+		 and			%l2, FPRS_DL, %l6
+		wr			%g0, FPRS_FEF, %fprs
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x108], %g5
+		membar			#StoreLoad | #LoadLoad
+		brz,pn			%l6, 1f
+		 wr			%g0, ASI_BLK_P, %asi
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x000] %asi, %f0
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x040] %asi, %f16
+1:		andcc			%l2, FPRS_DU, %g0
+		be,pn			%icc, 1f
+		 wr			%g5, 0, %gsr
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x080] %asi, %f32
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x0c0] %asi, %f48
+1:		membar			#Sync
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x100], %fsr
+rt_continue:	ld			[%g6 + AOFF_task_tss + AOFF_thread_ctx], %l0
+		ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
+		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2
+		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
 		mov			%g6, %l6
 		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
 		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
 		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
 		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7
+
 		wrpr			%l7, PSTATE_AG, %pstate
 		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
-
 		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1
 		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
 		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
 		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
 		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
 		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
+
 		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
 		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
-
 		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
 		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2
 		wr			%o3, %g0, %y
 		srl			%l4, 20, %l4
 		wrpr			%l4, 0x0, %pil
 		wrpr			%g0, 0x1, %tl
+
 		wrpr			%l1, %g0, %tstate
 		wrpr			%l2, %g0, %tpc
-
-		wr			%g0, ASI_DMMU, %asi
+		wrpr			%o2, %g0, %tnpc
+		mov			PRIMARY_CONTEXT, %l7
 		brnz,pn			%l3, kern_rtt
-		 wrpr			%o2, %g0, %tnpc
-		stxa			%l0, [%g0 + SECONDARY_CONTEXT] %asi
-		flush			%l6
-		stxa			%l0, [%g0 + PRIMARY_CONTEXT] %asi
+		 mov			SECONDARY_CONTEXT, %l5
+		stxa			%l0, [%l7] ASI_DMMU
+		stxa			%l0, [%l5] ASI_DMMU
 		flush			%l6
 		rdpr			%wstate, %l1
 
@@ -95,17 +111,17 @@
 		sethi			%hi(need_resched), %l0
 		ldx			[%l0 + %lo(need_resched)], %l0
 		sllx			%o1, %o0, %o1
-
 		wrpr			%l7, PSTATE_IE, %pstate
 		andcc			%o1, %l0, %g0
 		be,pt			%xcc, check_signal
 		 ldx			[%g6 + AOFF_task_signal], %l0
+
 		call			schedule
 		 nop
 		ldx			[%g6 + AOFF_task_signal], %l0
 		nop
-
 check_signal:	ldx			[%g6 + AOFF_task_blocked], %o0
+		ld			[%sp + PTREGS_OFF + PT_V9_FPRS], %l2
 		andncc			%l0, %o0, %g0
 		be,pt			%xcc, check_user_wins
 		 ldx			[%g6 + AOFF_task_tss + AOFF_thread_w_saved], %o2
@@ -113,31 +129,115 @@
 		mov			%l6, %o3
 		call			do_signal
 		 add			%sp, STACK_BIAS + REGWIN_SZ, %o1
-
 		ldx			[%g6 + AOFF_task_tss + AOFF_thread_w_saved], %o2
 		clr			%l6
-check_user_wins:brz,pt			%o2, rt_continue
-		 nop
+check_user_wins:brz,pt			%o2, 1f
+		 sethi			%hi(TSTATE_PEF), %o3
+
 		call			fault_in_user_windows
 		 add			%sp, STACK_BIAS + REGWIN_SZ, %o0
-		ba,a,pt			%xcc, rt_continue
-rt_fpu_restore:	wr			%g0, FPRS_FEF, %fprs
 
-		add			%sp, PTREGS_OFF + TRACEREG_SZ, %g4
-		wr			%g0, ASI_BLK_P, %asi
+		sethi			%hi(TSTATE_PEF), %o3
+1:		andcc			%l2, FPRS_FEF, %g0
+		be,a,pt			%icc, rt_continue
+		 andn			%l1, %o3, %l1		! If fprs.FEF is not set, disable tstate.PEF
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x108], %o3
+		ld			[%g6 + AOFF_task_tss + AOFF_thread_flags], %l2
+		wr			%g0, FPRS_FEF, %fprs
+		wr			%o3, 0, %gsr
+		andcc			%l2, SPARC_FLAG_USEDFPUL, %g0
+		bne,pn			%icc, 2f
+		 andcc			%l2, SPARC_FLAG_USEDFPUU, %g0
+		fzero			%f0
+		bne,pn			%icc, 1f
+		 fzero			%f2
+		faddd			%f0, %f2, %f4
+		fmuld			%f0, %f2, %f6
+		faddd			%f0, %f2, %f8
+		fmuld			%f0, %f2, %f10
+		faddd			%f0, %f2, %f12
+		fmuld			%f0, %f2, %f14
+		faddd			%f0, %f2, %f16
+		fmuld			%f0, %f2, %f18
+		faddd			%f0, %f2, %f20
+		fmuld			%f0, %f2, %f22
+		faddd			%f0, %f2, %f24
+		fmuld			%f0, %f2, %f26
+		faddd			%f0, %f2, %f28
+		fmuld			%f0, %f2, %f30
+		faddd			%f0, %f2, %f32
+		fmuld			%f0, %f2, %f34
+		faddd			%f0, %f2, %f36
+		fmuld			%f0, %f2, %f38
+		faddd			%f0, %f2, %f40
+		fmuld			%f0, %f2, %f42
+		faddd			%f0, %f2, %f44
+		fmuld			%f0, %f2, %f46
+		faddd			%f0, %f2, %f48
+		fmuld			%f0, %f2, %f50
+		faddd			%f0, %f2, %f52
+		fmuld			%f0, %f2, %f54
+		faddd			%f0, %f2, %f56
+		fmuld			%f0, %f2, %f58
+		faddd			%f0, %f2, %f60
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x100], %fsr
+		ba,pt			%xcc, rt_continue
+		 wr			%g0, FPRS_FEF, %fprs
+1:		wr			%g0, ASI_BLK_P, %asi
 		membar			#StoreLoad | #LoadLoad
-		ldda			[%g4 + 0x000] %asi, %f0
-		ldda			[%g4 + 0x040] %asi, %f16
-		ldda			[%g4 + 0x080] %asi, %f32
-		ldda			[%g4 + 0x0c0] %asi, %f48
-		ldx			[%g4 + 0x100], %fsr
-
-		ldx			[%g4 + 0x108], %g3
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x080] %asi, %f32
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x0c0] %asi, %f48
+		faddd			%f0, %f2, %f4
+		fmuld			%f0, %f2, %f6
+		faddd			%f0, %f2, %f8
+		fmuld			%f0, %f2, %f10
+		faddd			%f0, %f2, %f12
+		fmuld			%f0, %f2, %f14
+		faddd			%f0, %f2, %f16
+		fmuld			%f0, %f2, %f18
+		faddd			%f0, %f2, %f20
+		fmuld			%f0, %f2, %f22
+		faddd			%f0, %f2, %f24
+		fmuld			%f0, %f2, %f26
+		faddd			%f0, %f2, %f28
+		fmuld			%f0, %f2, %f30
 		membar			#Sync
-		b,pt			%xcc, rt_after_fpu
-		 wr			%g3, 0, %gsr
-		nop
-		nop
-		nop
-		nop
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x100], %fsr
+		ba,pt			%xcc, rt_continue
+		 wr			%g0, FPRS_FEF, %fprs
+2:		membar			#StoreLoad | #LoadLoad
+		andcc			%l2, SPARC_FLAG_USEDFPUU, %g0
+		bne,pt			%icc, 3f
+		 wr			%g0, ASI_BLK_P, %asi
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x000] %asi, %f0
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x040] %asi, %f16
+		fzero			%f32
+		fzero			%f34
+		faddd			%f32, %f34, %f36
+		fmuld			%f32, %f34, %f38
+		faddd			%f32, %f34, %f40
+		fmuld			%f32, %f34, %f42
+		faddd			%f32, %f34, %f44
+		fmuld			%f32, %f34, %f46
+		faddd			%f32, %f34, %f48
+		fmuld			%f32, %f34, %f50
+		faddd			%f32, %f34, %f52
+		fmuld			%f32, %f34, %f54
+		faddd			%f32, %f34, %f56
+		fmuld			%f32, %f34, %f58
+		faddd			%f32, %f34, %f60
+		fmuld			%f32, %f34, %f62
+		membar			#Sync
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x100], %fsr
+		ba,pt			%xcc, rt_continue
+		 wr			%g0, FPRS_FEF, %fprs
+3:		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x000] %asi, %f0
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x040] %asi, %f16
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x080] %asi, %f32
+		ldda			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x0c0] %asi, %f48
+		membar			#Sync
+		ldx			[%sp + PTREGS_OFF + TRACEREG_SZ + 0x100], %fsr
+		ba,pt			%xcc, rt_continue
+		 wr			%g0, FPRS_FEF, %fprs
+
 #undef PTREGS_OFF
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