patch-2.1.37 linux/drivers/net/de4x5.h

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diff -u --recursive --new-file v2.1.36/linux/drivers/net/de4x5.h linux/drivers/net/de4x5.h
@@ -139,7 +139,7 @@
 #define CFCS_DST    0x06000000       /* DEVSEL Timing         (S) */
 #define CFCS_DPR    0x01000000       /* Data Parity Report    (S) */
 #define CFCS_FBB    0x00800000       /* Fast Back-To-Back     (S) */
-#define CFCS_SLE    0x00000100       /* System Error Enable   (C) */
+#define CFCS_SEE    0x00000100       /* System Error Enable   (C) */
 #define CFCS_PER    0x00000040       /* Parity Error Response (C) */
 #define CFCS_MO     0x00000004       /* Master Operation      (C) */
 #define CFCS_MSA    0x00000002       /* Memory Space Access   (C) */
@@ -150,8 +150,8 @@
 */
 #define CFRV_BC     0xff000000       /* Base Class */
 #define CFRV_SC     0x00ff0000       /* Subclass */
-#define CFRV_SN     0x000000f0       /* Step Number */
-#define CFRV_RN     0x0000000f       /* Revision Number */
+#define CFRV_RN     0x000000f0       /* Revision Number */
+#define CFRV_SN     0x0000000f       /* Step Number */
 #define BASE_CLASS  0x02000000       /* Indicates Network Controller */
 #define SUB_CLASS   0x00000000       /* Indicates Ethernet Controller */
 #define STEP_NUMBER 0x00000020       /* Increments for future chips */
@@ -170,12 +170,33 @@
 #define CBIO_IOSI   0x00000001       /* I/O Space Indicator (RO, value is 1) */
 
 /*
+** PCI Configuration Card Information Structure Register (PCI_CCIS)
+*/
+#define CCIS_ROMI   0xf0000000       /* ROM Image */
+#define CCIS_ASO    0x0ffffff8       /* Address Space Offset */
+#define CCIS_ASI    0x00000007       /* Address Space Indicator */
+
+/*
+** PCI Configuration Subsystem ID Register (PCI_SSID)
+*/
+#define SSID_SSID   0xffff0000       /* Subsystem ID */
+#define SSID_SVID   0x0000ffff       /* Subsystem Vendor ID */
+
+/*
 ** PCI Configuration Expansion ROM Base Address Register (PCI_CBER)
 */
 #define CBER_MASK   0xfffffc00       /* Expansion ROM Base Address Mask */
 #define CBER_ROME   0x00000001       /* ROM Enable */
 
 /*
+** PCI Configuration Interrupt Register (PCI_CFIT)
+*/
+#define CFIT_MXLT   0xff000000       /* MAX_LAT Value (0.25us periods) */
+#define CFIT_MNGT   0x00ff0000       /* MIN_GNT Value (0.25us periods) */
+#define CFIT_IRQP   0x0000ff00       /* Interrupt Pin */
+#define CFIT_IRQL   0x000000ff       /* Interrupt Line */
+
+/*
 ** PCI Configuration Power Management Area Register (PCI_CFPM)
 */
 #define SLEEP       0x80             /* Power Saving Sleep Mode */
@@ -188,6 +209,7 @@
 /*
 ** DC21040 Bus Mode Register (DE4X5_BMR)
 */
+#define BMR_RML    0x00200000       /* [Memory] Read Multiple */
 #define BMR_DBO    0x00100000       /* Descriptor Byte Ordering (Endian) */
 #define BMR_TAP    0x000e0000       /* Transmit Automatic Polling */
 #define BMR_DAS    0x00010000       /* Diagnostic Address Space */
@@ -198,6 +220,7 @@
 #define BMR_BAR    0x00000002       /* Bus ARbitration */
 #define BMR_SWR    0x00000001       /* Software Reset */
 
+                                    /* Timings here are for 10BASE-T/AUI only*/
 #define TAP_NOPOLL 0x00000000       /* No automatic polling */
 #define TAP_200US  0x00020000       /* TX automatic polling every 200us */
 #define TAP_800US  0x00040000       /* TX automatic polling every 800us */
@@ -249,18 +272,21 @@
 #define TRBA       0xfffffffc       /* TX Descriptor List Start Address */
 
 /*
-** DC21040 Status Register (DE4X5_STS)
+** Status Register (DE4X5_STS)
 */
+#define STS_GPI    0x04000000       /* General Purpose Port Interrupt */
 #define STS_BE     0x03800000       /* Bus Error Bits */
 #define STS_TS     0x00700000       /* Transmit Process State */
 #define STS_RS     0x000e0000       /* Receive Process State */
 #define STS_NIS    0x00010000       /* Normal Interrupt Summary */
 #define STS_AIS    0x00008000       /* Abnormal Interrupt Summary */
 #define STS_ER     0x00004000       /* Early Receive */
+#define STS_FBE    0x00002000       /* Fatal Bus Error */
 #define STS_SE     0x00002000       /* System Error */
 #define STS_LNF    0x00001000       /* Link Fail */
 #define STS_FD     0x00000800       /* Full-Duplex Short Frame Received */
 #define STS_TM     0x00000800       /* Timer Expired (DC21041) */
+#define STS_ETI    0x00000400       /* Early Transmit Interupt */
 #define STS_AT     0x00000400       /* AUI/TP Pin */
 #define STS_RWT    0x00000200       /* Receive Watchdog Time-Out */
 #define STS_RPS    0x00000100       /* Receive Process Stopped */
@@ -268,6 +294,7 @@
 #define STS_RI     0x00000040       /* Receive Interrupt */
 #define STS_UNF    0x00000020       /* Transmit Underflow */
 #define STS_LNP    0x00000010       /* Link Pass */
+#define STS_ANC    0x00000010       /* Autonegotiation Complete */
 #define STS_TJT    0x00000008       /* Transmit Jabber Time-Out */
 #define STS_TU     0x00000004       /* Transmit Buffer Unavailable */
 #define STS_TPS    0x00000002       /* Transmit Process Stopped */
@@ -300,8 +327,10 @@
 #define INT_CANCEL 0x0001ffff       /* For zeroing all interrupt sources */
 
 /*
-** DC21040 Operation Mode Register (DE4X5_OMR)
+** Operation Mode Register (DE4X5_OMR)
 */
+#define OMR_SC     0x80000000       /* Special Capture Effect Enable */
+#define OMR_RA     0x40000000       /* Receive All */
 #define OMR_SDP    0x02000000       /* SD Polarity - MUST BE ASSERTED */
 #define OMR_SCR    0x01000000       /* Scrambler Mode */
 #define OMR_PCS    0x00800000       /* PCS Function */
@@ -326,27 +355,31 @@
 #define OMR_SR     0x00000002       /* Start/Stop Receive */
 #define OMR_HP     0x00000001       /* Hash/Perfect Receive Filtering Mode */
 
-#define TR_72      0x00000000       /* Threshold set to 72 bytes */
-#define TR_96      0x00004000       /* Threshold set to 96 bytes */
-#define TR_128     0x00008000       /* Threshold set to 128 bytes */
-#define TR_160     0x0000c000       /* Threshold set to 160 bytes */
+#define TR_72      0x00000000       /* Threshold set to 72 (128) bytes */
+#define TR_96      0x00004000       /* Threshold set to 96 (256) bytes */
+#define TR_128     0x00008000       /* Threshold set to 128 (512) bytes */
+#define TR_160     0x0000c000       /* Threshold set to 160 (1024) bytes */
 
 /*
 ** DC21040 Interrupt Mask Register (DE4X5_IMR)
 */
+#define IMR_GPM    0x04000000       /* General Purpose Port Mask */
 #define IMR_NIM    0x00010000       /* Normal Interrupt Summary Mask */
 #define IMR_AIM    0x00008000       /* Abnormal Interrupt Summary Mask */
 #define IMR_ERM    0x00004000       /* Early Receive Mask */
+#define IMR_FBM    0x00002000       /* Fatal Bus Error Mask */
 #define IMR_SEM    0x00002000       /* System Error Mask */
 #define IMR_LFM    0x00001000       /* Link Fail Mask */
 #define IMR_FDM    0x00000800       /* Full-Duplex (Short Frame) Mask */
 #define IMR_TMM    0x00000800       /* Timer Expired Mask (DC21041) */
+#define IMR_ETM    0x00000400       /* Early Transmit Interrupt Mask */
 #define IMR_ATM    0x00000400       /* AUI/TP Switch Mask */
 #define IMR_RWM    0x00000200       /* Receive Watchdog Time-Out Mask */
 #define IMR_RSM    0x00000100       /* Receive Stopped Mask */
 #define IMR_RUM    0x00000080       /* Receive Buffer Unavailable Mask */
 #define IMR_RIM    0x00000040       /* Receive Interrupt Mask */
 #define IMR_UNM    0x00000020       /* Underflow Interrupt Mask */
+#define IMR_ANM    0x00000010       /* Autonegotiation Complete Mask */
 #define IMR_LPM    0x00000010       /* Link Pass */
 #define IMR_TJM    0x00000008       /* Transmit Time-Out Jabber Mask */
 #define IMR_TUM    0x00000004       /* Transmit Buffer Unavailable Mask */
@@ -354,13 +387,7 @@
 #define IMR_TIM    0x00000001       /* Transmit Interrupt Mask */
 
 /*
-** DC21040 Missed Frames Counter (DE4X5_MFC)
-*/
-#define MFC_OVFL   0x00010000       /* Missed Frames Counter Overflow Bit */
-#define MFC_CNTR   0x0000ffff       /* Missed Frames Counter Bits */
-
-/*
-** DC21140 Missed Frames and FIFO Overflow Counters (DE4X5_MFC)
+** Missed Frames and FIFO Overflow Counters (DE4X5_MFC)
 */
 #define MFC_FOCO   0x10000000       /* FIFO Overflow Counter Overflow Bit */
 #define MFC_FOC    0x0ffe0000       /* FIFO Overflow Counter Bits */
@@ -461,7 +488,7 @@
 ** MII Management Auto Negotiation Advertisement Register
 */
 #define MII_ANA_TAF  0x03e0        /* Technology Ability Field */
-#define MII_ANA_T4AM 0x0400        /* T4 Technology Ability Mask */
+#define MII_ANA_T4AM 0x0200        /* T4 Technology Ability Mask */
 #define MII_ANA_TXAM 0x0180        /* TX Technology Ability Mask */
 #define MII_ANA_FDAM 0x0140        /* Full Duplex Technology Ability Mask */
 #define MII_ANA_HDAM 0x02a0        /* Half Duplex Technology Ability Mask */
@@ -476,7 +503,7 @@
 #define MII_ANLPA_ACK  0x4000      /* Remote Acknowledge */
 #define MII_ANLPA_RF   0x2000      /* Remote Fault */
 #define MII_ANLPA_TAF  0x03e0      /* Technology Ability Field */
-#define MII_ANLPA_T4AM 0x0400      /* T4 Technology Ability Mask */
+#define MII_ANLPA_T4AM 0x0200      /* T4 Technology Ability Mask */
 #define MII_ANLPA_TXAM 0x0180      /* TX Technology Ability Mask */
 #define MII_ANLPA_FDAM 0x0140      /* Full Duplex Technology Ability Mask */
 #define MII_ANLPA_HDAM 0x02a0      /* Half Duplex Technology Ability Mask */
@@ -547,6 +574,8 @@
 #define SROM_100BASEFF 0x0008      /*  100BASE-FX full duplex */
 
 #define BLOCK_LEN      0x7f        /* Extended blocks length mask */
+#define EXT_FIELD      0x40        /* Extended blocks extension field bit */
+#define MEDIA_CODE     0x3f        /* Extended blocks media code mask */
 
 /*
 ** SROM Compact Format Block Masks
@@ -589,14 +618,18 @@
 #define GEP_CTRL 0x00000100        /* GEP control bit                  */
 
 /*
-** DC21040 SIA Status Register (DE4X5_SISR)
+** SIA Status Register (DE4X5_SISR)
 */
 #define SISR_LPC   0xffff0000      /* Link Partner's Code Word */
 #define SISR_LPN   0x00008000      /* Link Partner Negotiable */
 #define SISR_ANS   0x00007000      /* Auto Negotiation Arbitration State */
-#define SISR_NSN   0x00000800      /* Non Stable NLPs Detected */
+#define SISR_NSN   0x00000800      /* Non Stable NLPs Detected (DC21041) */
+#define SISR_TRF   0x00000800      /* Transmit Remote Fault */
+#define SISR_NSND  0x00000400      /* Non Stable NLPs Detected (DC21142) */
 #define SISR_ANR_FDS 0x00000400    /* Auto Negotiate Restart/Full Duplex Sel.*/
+#define SISR_TRA   0x00000200      /* 10BASE-T Receive Port Activity */
 #define SISR_NRA   0x00000200      /* Non Selected Port Receive Activity */
+#define SISR_ARA   0x00000100      /* AUI Receive Port Activity */
 #define SISR_SRA   0x00000100      /* Selected Port Receive Activity */
 #define SISR_DAO   0x00000080      /* PLL All One */
 #define SISR_DAZ   0x00000040      /* PLL All Zero */
@@ -606,7 +639,7 @@
 #define SISR_LKF   0x00000004      /* Link Fail Status */
 #define SISR_NCR   0x00000002      /* Network Connection Error */
 #define SISR_PAUI  0x00000001      /* AUI_TP Indication */
-#define SIA_RESET  0x00000000      /* SIA Reset */
+#define SISR_MRA   0x00000001      /* MII Receive Port Activity */
 
 #define ANS_NDIS   0x00000000      /* Nway disable */
 #define ANS_TDIS   0x00001000      /* Transmit Disable */
@@ -617,7 +650,7 @@
 #define ANS_LCHK   0x00006000      /* Link Check */
 
 /*
-** DC21040 SIA Connectivity Register (DE4X5_SICR)
+** SIA Connectivity Register (DE4X5_SICR)
 */
 #define SICR_SDM   0xffff0000       /* SIA Diagnostics Mode */
 #define SICR_OE57  0x00008000       /* Output Enable 5 6 7 */
@@ -636,14 +669,14 @@
 #define SICR_SIM   0x00000040       /* Serial Interface Input Multiplexer */
 #define SICR_ENI   0x00000020       /* Encoder Input Multiplexer */
 #define SICR_EDP   0x00000010       /* SIA PLL External Input Enable */
-#define SICR_AUI   0x00000008       /* 10Base-T or AUI */
+#define SICR_AUI   0x00000008       /* 10Base-T (0) or AUI (1) */
 #define SICR_CAC   0x00000004       /* CSR Auto Configuration */
 #define SICR_PS    0x00000002       /* Pin AUI/TP Selection */
 #define SICR_SRL   0x00000001       /* SIA Reset */
-#define SICR_RESET 0xffff0000       /* Reset value for SICR */
+#define SIA_RESET  0x00000000       /* SIA Reset Value */
 
 /*
-** DC21040 SIA Transmit and Receive Register (DE4X5_STRR)
+** SIA Transmit and Receive Register (DE4X5_STRR)
 */
 #define STRR_TAS   0x00008000       /* 10Base-T/AUI Autosensing Enable */
 #define STRR_SPP   0x00004000       /* Set Polarity Plus */
@@ -663,8 +696,20 @@
 #define STRR_RESET 0xffffffff       /* Reset value for STRR */
 
 /*
-** DC21040 SIA General Register (DE4X5_SIGR)
+** SIA General Register (DE4X5_SIGR)
 */
+#define SIGR_RMI   0x40000000       /* Receive Match Interrupt */
+#define SIGR_GI1   0x20000000       /* General Port Interrupt 1 */
+#define SIGR_GI0   0x10000000       /* General Port Interrupt 0 */
+#define SIGR_CWE   0x08000000       /* Control Write Enable */
+#define SIGR_RME   0x04000000       /* Receive Match Enable */
+#define SIGR_GEI1  0x02000000       /* GEP Interrupt Enable on Port 1 */
+#define SIGR_GEI0  0x01000000       /* GEP Interrupt Enable on Port 0 */
+#define SIGR_LGS3  0x00800000       /* LED/GEP3 Select */
+#define SIGR_LGS2  0x00400000       /* LED/GEP2 Select */
+#define SIGR_LGS1  0x00200000       /* LED/GEP1 Select */
+#define SIGR_LGS0  0x00100000       /* LED/GEP0 Select */
+#define SIGR_MD    0x000f0000       /* General Purpose Mode and Data */
 #define SIGR_LV2   0x00008000       /* General Purpose LED2 value */
 #define SIGR_LE2   0x00004000       /* General Purpose LED2 enable */
 #define SIGR_FRL   0x00002000       /* Force Receiver Low */
@@ -687,7 +732,8 @@
 ** Receive Descriptor Bit Summary
 */
 #define R_OWN      0x80000000       /* Own Bit */
-#define RD_FL      0x7fff0000       /* Frame Length */
+#define RD_FF      0x40000000       /* Filtering Fail */
+#define RD_FL      0x3fff0000       /* Frame Length */
 #define RD_ES      0x00008000       /* Error Summary */
 #define RD_LE      0x00004000       /* Length Error */
 #define RD_DT      0x00003000       /* Data Type */
@@ -699,6 +745,7 @@
 #define RD_CS      0x00000040       /* Collision Seen */
 #define RD_FT      0x00000020       /* Frame Type */
 #define RD_RJ      0x00000010       /* Receive Watchdog */
+#define RD_RE      0x00000008       /* Report on MII Error */
 #define RD_DB      0x00000004       /* Dribbling Bit */
 #define RD_CE      0x00000002       /* CRC Error */
 #define RD_OF      0x00000001       /* Overflow */
@@ -734,40 +781,39 @@
 #define TD_TCH     0x01000000       /* Second Address Chained */
 #define TD_DPD     0x00800000       /* Disabled Padding */
 #define TD_FT0     0x00400000       /* Filtering Type */
-#define TD_RBS2    0x003ff800       /* Buffer 2 Size */
-#define TD_RBS1    0x000007ff       /* Buffer 1 Size */
+#define TD_TBS2    0x003ff800       /* Buffer 2 Size */
+#define TD_TBS1    0x000007ff       /* Buffer 1 Size */
 
 #define PERFECT_F  0x00000000
 #define HASH_F     TD_FT0
 #define INVERSE_F  TD_FT1
-#define HASH_O_F   TD_FT1| TD_F0
+#define HASH_O_F   (TD_FT1 | TD_F0)
 
 /*
 ** Media / mode state machine definitions
 */
-#define NC              0x0000     /* No Connection */
-#define TP              0x0001     /* 10Base-T */
-#define TP_NW           0x0002     /* 10Base-T with Nway */
-#define BNC             0x0004     /* Thinwire */
-#define AUI             0x0008     /* Thickwire */
+#define NC              0x0000     /* No Connection                        */
+#define TP              0x0001     /* 10Base-T                             */
+#define TP_NW           0x0002     /* 10Base-T with Nway                   */
+#define BNC             0x0004     /* Thinwire                             */
+#define AUI             0x0008     /* Thickwire                            */
 #define BNC_AUI         0x0010     /* BNC/AUI on DC21040 indistinguishable */
-#define ANS             0x0020     /* Intermediate AutoNegotiation State */
-#define ANS_1           0x0021     /* Intermediate AutoNegotiation State */
-
-#define _10Mb           0x0040     /* 10Mb/s Ethernet */
-#define _100Mb          0x0080     /* 100Mb/s Ethernet */
-#define SPD_DET         0x0100     /* Parallel speed detection */
-#define INIT            0x0200     /* Initial state */
-#define EXT_SIA         0x0400     /* External SIA for motherboard chip */
-#define ANS_SUSPECT     0x0802     /* Suspect the ANS (TP) port is down */
-#define TP_SUSPECT      0x0803     /* Suspect the TP port is down */
-#define BNC_AUI_SUSPECT 0x0804     /* Suspect the BNC or AUI port is down */
-#define EXT_SIA_SUSPECT 0x0805     /* Suspect the EXT SIA port is down */
-#define BNC_SUSPECT     0x0806     /* Suspect the BNC port is down */
-#define AUI_SUSPECT     0x0807     /* Suspect the AUI port is down */
+#define ANS             0x0020     /* Intermediate AutoNegotiation State   */
+#define _10Mb           0x0040     /* 10Mb/s Ethernet                      */
+#define _100Mb          0x0080     /* 100Mb/s Ethernet                     */
+#define SPD_DET         0x0100     /* Parallel speed detection             */
+#define INIT            0x0200     /* Initial state                        */
+#define EXT_SIA         0x0400     /* External SIA for motherboard chip    */
+#define ANS_SUSPECT     0x0802     /* Suspect the ANS (TP) port is down    */
+#define TP_SUSPECT      0x0803     /* Suspect the TP port is down          */
+#define BNC_AUI_SUSPECT 0x0804     /* Suspect the BNC or AUI port is down  */
+#define EXT_SIA_SUSPECT 0x0805     /* Suspect the EXT SIA port is down     */
+#define BNC_SUSPECT     0x0806     /* Suspect the BNC port is down         */
+#define AUI_SUSPECT     0x0807     /* Suspect the AUI port is down         */
+#define MII             0x1000     /* MII on the 21143                     */
 
-#define AUTO            0x4000     /* Auto sense the media or speed */
-#define TIMER_CB        0x80000000 /* Timer callback detection */
+#define AUTO            0x4000     /* Auto sense the media or speed        */
+#define TIMER_CB        0x80000000 /* Timer callback detection             */
 
 /*
 ** DE4X5 DEBUG Options
@@ -798,7 +844,6 @@
 #define POLL_DEMAND          1
 
 #define LOST_MEDIA_THRESHOLD 3
-#define LOST_MEDIA           (lp->lostMedia > LOST_MEDIA_THRESHOLD)
 
 #define MASK_INTERRUPTS      1
 #define UNMASK_INTERRUPTS    0
@@ -859,7 +904,7 @@
     }\
     omr |= ((lp->fdx ? OMR_FDX : 0) | OMR_TTM);\
     outl(omr, DE4X5_OMR);\
-    lp->cache.gep = 0;\
+    if (!lp->useSROM) lp->cache.gep = 0;\
   } else if (lp->useSROM && !lp->useMII) {\
     omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
     omr |= (lp->fdx ? OMR_FDX : 0);\
@@ -887,7 +932,7 @@
     }\
     if (fdx) omr |= OMR_FDX;\
     outl(omr, DE4X5_OMR);\
-    lp->cache.gep = 0;\
+    if (!lp->useSROM) lp->cache.gep = 0;\
   } else if (lp->useSROM && !lp->useMII) {\
     omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
     omr |= (lp->fdx ? OMR_FDX : 0);\
@@ -906,7 +951,6 @@
     mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
     omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
     outl(omr, DE4X5_OMR);\
-    lp->cache.gep = 0;\
   } else if (lp->useSROM && !lp->useMII) {\
     omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
     outl(omr, DE4X5_OMR);\
@@ -934,7 +978,7 @@
 ** Recognised commands for the driver 
 */
 #define DE4X5_GET_HWADDR	0x01 /* Get the hardware address */
-#define DE4X5_SET_HWADDR	0x02 /* Get the hardware address */
+#define DE4X5_SET_HWADDR	0x02 /* Set the hardware address */
 #define DE4X5_SET_PROM  	0x03 /* Set Promiscuous Mode */
 #define DE4X5_CLR_PROM  	0x04 /* Clear Promiscuous Mode */
 #define DE4X5_SAY_BOO	        0x05 /* Say "Boo!" to the kernel log file */

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