patch-2.1.121 linux/include/asm-alpha/core_tsunami.h

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diff -u --recursive --new-file v2.1.120/linux/include/asm-alpha/core_tsunami.h linux/include/asm-alpha/core_tsunami.h
@@ -35,91 +35,77 @@
 #endif
 
 /*
- * CChip and DChip registers
+ * CChip, DChip, and PChip registers
  */
-#define	TSUNAMI_CSR_CSC		(IDENT_ADDR + TS_BIAS + 0x1A0000000UL)
-#define	TSUNAMI_CSR_MTR		(IDENT_ADDR + TS_BIAS + 0x1A0000040UL)
-#define	TSUNAMI_CSR_MISC	(IDENT_ADDR + TS_BIAS + 0x1A0000080UL)
-#define	TSUNAMI_CSR_MPD		(IDENT_ADDR + TS_BIAS + 0x1A00000C0UL)
-#define	TSUNAMI_CSR_AAR0	(IDENT_ADDR + TS_BIAS + 0x1A0000100UL)
-#define	TSUNAMI_CSR_AAR1	(IDENT_ADDR + TS_BIAS + 0x1A0000140UL)
-#define	TSUNAMI_CSR_AAR2	(IDENT_ADDR + TS_BIAS + 0x1A0000180UL)
-#define	TSUNAMI_CSR_AAR3	(IDENT_ADDR + TS_BIAS + 0x1A00001C0UL)
-#define	TSUNAMI_CSR_DIM0	(IDENT_ADDR + TS_BIAS + 0x1A0000200UL)
-#define	TSUNAMI_CSR_DIM1	(IDENT_ADDR + TS_BIAS + 0x1A0000240UL)
-#define	TSUNAMI_CSR_DIR0	(IDENT_ADDR + TS_BIAS + 0x1A0000280UL)
-#define	TSUNAMI_CSR_DIR1	(IDENT_ADDR + TS_BIAS + 0x1A00002C0UL)
-
-#define	TSUNAMI_CSR_DRIR	(IDENT_ADDR + TS_BIAS + 0x1A0000300UL)
-#define	TSUNAMI_CSR_PRBEN	(IDENT_ADDR + TS_BIAS + 0x1A0000340UL)
-#define	TSUNAMI_CSR_IIC	       	(IDENT_ADDR + TS_BIAS + 0x1A0000380UL)
-#define	TSUNAMI_CSR_WDR	       	(IDENT_ADDR + TS_BIAS + 0x1A00003C0UL)
-#define	TSUNAMI_CSR_MPR0	(IDENT_ADDR + TS_BIAS + 0x1A0000400UL)
-#define	TSUNAMI_CSR_MPR1	(IDENT_ADDR + TS_BIAS + 0x1A0000440UL)
-#define	TSUNAMI_CSR_MPR2	(IDENT_ADDR + TS_BIAS + 0x1A0000480UL)
-#define	TSUNAMI_CSR_MPR3	(IDENT_ADDR + TS_BIAS + 0x1A00004C0UL)
-#define	TSUNAMI_CSR_TTR		(IDENT_ADDR + TS_BIAS + 0x1A0000580UL)
-#define	TSUNAMI_CSR_TDR		(IDENT_ADDR + TS_BIAS + 0x1A00005C0UL)
-#define	TSUNAMI_CSR_DSC	       	(IDENT_ADDR + TS_BIAS + 0x1B0000800UL)
-#define	TSUNAMI_CSR_STR		(IDENT_ADDR + TS_BIAS + 0x1B0000840UL)
-#define	TSUNAMI_CSR_DREV	(IDENT_ADDR + TS_BIAS + 0x1B0000880UL)
+
+typedef struct {
+	volatile unsigned long csr __attribute__((aligned(64)));
+} tsunami_64;
+
+typedef struct {
+	tsunami_64	csc;
+	tsunami_64	mtr;
+	tsunami_64	misc;
+	tsunami_64	mpd;
+	tsunami_64	aar0;
+	tsunami_64	aar1;
+	tsunami_64	aar2;
+	tsunami_64	aar3;
+	tsunami_64	dim0;
+	tsunami_64	dim1;
+	tsunami_64	dir0;
+	tsunami_64	dir1;
+	tsunami_64	drir;
+	tsunami_64	prben;
+	tsunami_64	iic;	/* a.k.a. iic0 */
+	tsunami_64	wdr;	/* a.k.a. iic1 */
+	tsunami_64	mpr0;
+	tsunami_64	mpr1;
+	tsunami_64	mpr2;
+	tsunami_64	mpr3;
+	tsunami_64	mctl;
+	tsunami_64	ttr;
+	tsunami_64	tdr;
+	tsunami_64	dim2;
+	tsunami_64	dim3;
+	tsunami_64	dir2;
+	tsunami_64	dir3;
+	tsunami_64	iic2;
+	tsunami_64	iic3;
+} tsunami_cchip;
+
+typedef struct {
+	tsunami_64	dsc;
+	tsunami_64	str;
+	tsunami_64	drev;
+} tsunami_dchip;
+
+typedef struct {
+	tsunami_64	wsba[4];
+	tsunami_64	wsm[4];
+	tsunami_64	tba[4];
+	tsunami_64	pctl;
+	tsunami_64	plat;
+	tsunami_64	reserved;
+	tsunami_64	perror;
+	tsunami_64	perrmask;
+	tsunami_64	perrset;
+	tsunami_64	tlbiv;
+	tsunami_64	tlbia;
+	tsunami_64	pmonctl;
+	tsunami_64	pmoncnt;
+} tsunami_pchip;
+
+#define TSUNAMI_cchip  ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
+#define TSUNAMI_dchip  ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
+#define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
+#define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
+extern int TSUNAMI_bootcpu;
 
 /*
- * PChip registers
+ * TSUNAMI Pchip Error register.
  */
-#define	TSUNAMI_PCHIP0_WSBA0  	(IDENT_ADDR + TS_BIAS + 0x180000000UL)
-#define	TSUNAMI_PCHIP0_WSBA1  	(IDENT_ADDR + TS_BIAS + 0x180000040UL)
-#define	TSUNAMI_PCHIP0_WSBA2  	(IDENT_ADDR + TS_BIAS + 0x180000080UL)
-#define	TSUNAMI_PCHIP0_WSBA3  	(IDENT_ADDR + TS_BIAS + 0x1800000C0UL)
-
-#define	TSUNAMI_PCHIP0_WSM0  	(IDENT_ADDR + TS_BIAS + 0x180000100UL)
-#define	TSUNAMI_PCHIP0_WSM1  	(IDENT_ADDR + TS_BIAS + 0x180000140UL)
-#define	TSUNAMI_PCHIP0_WSM2  	(IDENT_ADDR + TS_BIAS + 0x180000180UL)
-#define	TSUNAMI_PCHIP0_WSM3  	(IDENT_ADDR + TS_BIAS + 0x1800001C0UL)
-#define	TSUNAMI_PCHIP0_TBA0  	(IDENT_ADDR + TS_BIAS + 0x180000200UL)
-#define	TSUNAMI_PCHIP0_TBA1  	(IDENT_ADDR + TS_BIAS + 0x180000240UL)
-#define	TSUNAMI_PCHIP0_TBA2  	(IDENT_ADDR + TS_BIAS + 0x180000280UL)
-#define	TSUNAMI_PCHIP0_TBA3  	(IDENT_ADDR + TS_BIAS + 0x1800002C0UL)
-
-#define	TSUNAMI_PCHIP0_PCTL  	(IDENT_ADDR + TS_BIAS + 0x180000300UL)
-#define	TSUNAMI_PCHIP0_PLAT  	(IDENT_ADDR + TS_BIAS + 0x180000340UL)
-#define	TSUNAMI_PCHIP0_RESERVED	(IDENT_ADDR + TS_BIAS + 0x180000380UL)
-#define	TSUNAMI_PCHIP0_PERROR	(IDENT_ADDR + TS_BIAS + 0x1800003c0UL)
-#define	TSUNAMI_PCHIP0_PERRMASK	(IDENT_ADDR + TS_BIAS + 0x180000400UL)
-#define	TSUNAMI_PCHIP0_PERRSET 	(IDENT_ADDR + TS_BIAS + 0x180000440UL)
-#define	TSUNAMI_PCHIP0_TLBIV  	(IDENT_ADDR + TS_BIAS + 0x180000480UL)
-#define	TSUNAMI_PCHIP0_TLBIA 	(IDENT_ADDR + TS_BIAS + 0x1800004C0UL)
-#define	TSUNAMI_PCHIP0_PMONCTL	(IDENT_ADDR + TS_BIAS + 0x180000500UL)
-#define	TSUNAMI_PCHIP0_PMONCNT	(IDENT_ADDR + TS_BIAS + 0x180000540UL)
-
-#define	TSUNAMI_PCHIP1_WSBA0  	(IDENT_ADDR + TS_BIAS + 0x380000000UL)
-#define	TSUNAMI_PCHIP1_WSBA1  	(IDENT_ADDR + TS_BIAS + 0x380000040UL)
-#define	TSUNAMI_PCHIP1_WSBA2  	(IDENT_ADDR + TS_BIAS + 0x380000080UL)
-#define	TSUNAMI_PCHIP1_WSBA3  	(IDENT_ADDR + TS_BIAS + 0x3800000C0UL)
-#define	TSUNAMI_PCHIP1_WSM0  	(IDENT_ADDR + TS_BIAS + 0x380000100UL)
-#define	TSUNAMI_PCHIP1_WSM1  	(IDENT_ADDR + TS_BIAS + 0x380000140UL)
-#define	TSUNAMI_PCHIP1_WSM2  	(IDENT_ADDR + TS_BIAS + 0x380000180UL)
-#define	TSUNAMI_PCHIP1_WSM3  	(IDENT_ADDR + TS_BIAS + 0x3800001C0UL)
-
-#define	TSUNAMI_PCHIP1_TBA0  	(IDENT_ADDR + TS_BIAS + 0x380000200UL)
-#define	TSUNAMI_PCHIP1_TBA1  	(IDENT_ADDR + TS_BIAS + 0x380000240UL)
-#define	TSUNAMI_PCHIP1_TBA2  	(IDENT_ADDR + TS_BIAS + 0x380000280UL)
-#define	TSUNAMI_PCHIP1_TBA3  	(IDENT_ADDR + TS_BIAS + 0x3800002C0UL)
-
-#define	TSUNAMI_PCHIP1_PCTL  	(IDENT_ADDR + TS_BIAS + 0x380000300UL)
-#define	TSUNAMI_PCHIP1_PLAT  	(IDENT_ADDR + TS_BIAS + 0x380000340UL)
-#define	TSUNAMI_PCHIP1_RESERVED	(IDENT_ADDR + TS_BIAS + 0x380000380UL)
-#define	TSUNAMI_PCHIP1_PERROR	(IDENT_ADDR + TS_BIAS + 0x3800003c0UL)
-#define	TSUNAMI_PCHIP1_PERRMASK	(IDENT_ADDR + TS_BIAS + 0x380000400UL)
-#define	TSUNAMI_PCHIP1_PERRSET	(IDENT_ADDR + TS_BIAS + 0x380000440UL)
-#define	TSUNAMI_PCHIP1_TLBIV  	(IDENT_ADDR + TS_BIAS + 0x380000480UL)
-#define	TSUNAMI_PCHIP1_TLBIA	(IDENT_ADDR + TS_BIAS + 0x3800004C0UL)
-#define	TSUNAMI_PCHIP1_PMONCTL	(IDENT_ADDR + TS_BIAS + 0x380000500UL)
-#define	TSUNAMI_PCHIP1_PMONCNT	(IDENT_ADDR + TS_BIAS + 0x380000540UL)
-
-/*                                                                          */
-/* TSUNAMI Pchip Error register.                                            */
-/*                                                                          */
+
 #define perror_m_lost 0x1
 #define perror_m_serr 0x2
 #define perror_m_perr 0x4
@@ -137,50 +123,52 @@
 #define perror_m_cmd 0xF0000000000000UL
 #define perror_m_syn 0xFF00000000000000UL
 union TPchipPERROR {   
-    struct  {
-        unsigned int perror_v_lost : 1;
-        unsigned perror_v_serr : 1;
-        unsigned perror_v_perr : 1;
-        unsigned perror_v_dcrto : 1;
-        unsigned perror_v_sge : 1;
-        unsigned perror_v_ape : 1;
-        unsigned perror_v_ta : 1;
-        unsigned perror_v_rdpe : 1;
-        unsigned perror_v_nds : 1;
-        unsigned perror_v_rto : 1;
-        unsigned perror_v_uecc : 1;
-        unsigned perror_v_cre : 1;                 
-        unsigned perror_v_rsvd1 : 4;
-        unsigned perror_v_addrl : 32;
-        unsigned perror_v_addrh : 3;
-        unsigned perror_v_rsvd2 : 1;
-        unsigned perror_v_cmd : 4;
-        unsigned perror_v_syn : 8;
+	struct  {
+		unsigned int perror_v_lost : 1;
+		unsigned perror_v_serr : 1;
+		unsigned perror_v_perr : 1;
+		unsigned perror_v_dcrto : 1;
+		unsigned perror_v_sge : 1;
+		unsigned perror_v_ape : 1;
+		unsigned perror_v_ta : 1;
+		unsigned perror_v_rdpe : 1;
+		unsigned perror_v_nds : 1;
+		unsigned perror_v_rto : 1;
+		unsigned perror_v_uecc : 1;
+		unsigned perror_v_cre : 1;                 
+		unsigned perror_v_rsvd1 : 4;
+		unsigned perror_v_addrl : 32;
+		unsigned perror_v_addrh : 3;
+		unsigned perror_v_rsvd2 : 1;
+		unsigned perror_v_cmd : 4;
+		unsigned perror_v_syn : 8;
         } perror_r_bits;
-    int perror_q_whole [2];
-    } ;                       
-/*                                                                          */
-/* TSUNAMI Pchip Window Space Base Address register.                        */
-/*                                                                          */
+	int perror_q_whole [2];
+};                       
+
+/*
+ * TSUNAMI Pchip Window Space Base Address register.
+ */
 #define wsba_m_ena 0x1                
 #define wsba_m_sg 0x2
 #define wsba_m_ptp 0x4
 #define wsba_m_addr 0xFFF00000  
 #define wmask_k_sz1gb 0x3FF00000                   
 union TPchipWSBA {
-    struct  {
-        unsigned wsba_v_ena : 1;
-        unsigned wsba_v_sg : 1;
-        unsigned wsba_v_ptp : 1;
-        unsigned wsba_v_rsvd1 : 17;
-        unsigned wsba_v_addr : 12;
-        unsigned wsba_v_rsvd2 : 32;
+	struct  {
+		unsigned wsba_v_ena : 1;
+		unsigned wsba_v_sg : 1;
+		unsigned wsba_v_ptp : 1;
+		unsigned wsba_v_rsvd1 : 17;
+		unsigned wsba_v_addr : 12;
+		unsigned wsba_v_rsvd2 : 32;
         } wsba_r_bits;
-    int wsba_q_whole [2];
-    } ;
-/*									    */
-/* TSUNAMI Pchip Control Register					    */
-/*									    */
+	int wsba_q_whole [2];
+};
+
+/*
+ * TSUNAMI Pchip Control Register
+ */
 #define pctl_m_fdsc 0x1
 #define pctl_m_fbtb 0x2
 #define pctl_m_thdis 0x4
@@ -207,37 +195,38 @@
 #define pctl_m_rsvd2 0xFFFF000000000000UL
 
 union TPchipPCTL {
-    struct {
-	unsigned pctl_v_fdsc : 1;
-	unsigned pctl_v_fbtb : 1;
-	unsigned pctl_v_thdis : 1;
-	unsigned pctl_v_chaindis : 1;
-	unsigned pctl_v_tgtlat : 1;
-	unsigned pctl_v_hole : 1;
-	unsigned pctl_v_mwin : 1;
-	unsigned pctl_v_arbena : 1;
-	unsigned pctl_v_prigrp : 7;
-	unsigned pctl_v_ppri : 1;
-	unsigned pctl_v_rsvd1 : 2;
-	unsigned pctl_v_eccen : 1;
-	unsigned pctl_v_padm : 1;
-	unsigned pctl_v_cdqmax : 4;
-	unsigned pctl_v_rev : 8;
-	unsigned pctl_v_crqmax : 4;
-	unsigned pctl_v_ptpmax : 4;
-	unsigned pctl_v_pclkx : 2;
-	unsigned pctl_v_fdsdis : 1;
-	unsigned pctl_v_fdwdis : 1;
-	unsigned pctl_v_ptevrfy : 1;
-	unsigned pctl_v_rpp : 1;
-	unsigned pctl_v_pid : 2;
-	unsigned pctl_v_rsvd2 : 16;
+	struct {
+		unsigned pctl_v_fdsc : 1;
+		unsigned pctl_v_fbtb : 1;
+		unsigned pctl_v_thdis : 1;
+		unsigned pctl_v_chaindis : 1;
+		unsigned pctl_v_tgtlat : 1;
+		unsigned pctl_v_hole : 1;
+		unsigned pctl_v_mwin : 1;
+		unsigned pctl_v_arbena : 1;
+		unsigned pctl_v_prigrp : 7;
+		unsigned pctl_v_ppri : 1;
+		unsigned pctl_v_rsvd1 : 2;
+		unsigned pctl_v_eccen : 1;
+		unsigned pctl_v_padm : 1;
+		unsigned pctl_v_cdqmax : 4;
+		unsigned pctl_v_rev : 8;
+		unsigned pctl_v_crqmax : 4;
+		unsigned pctl_v_ptpmax : 4;
+		unsigned pctl_v_pclkx : 2;
+		unsigned pctl_v_fdsdis : 1;
+		unsigned pctl_v_fdwdis : 1;
+		unsigned pctl_v_ptevrfy : 1;
+		unsigned pctl_v_rpp : 1;
+		unsigned pctl_v_pid : 2;
+		unsigned pctl_v_rsvd2 : 16;
 	} pctl_r_bits;
-    int pctl_q_whole [2];
-} ;
-/*                                                                          */
-/* TSUNAMI Pchip Error Mask Register.                                       */
-/*                                                                          */
+	int pctl_q_whole [2];
+};
+
+/*
+ * TSUNAMI Pchip Error Mask Register.
+ */
 #define perrmask_m_lost 0x1
 #define perrmask_m_serr 0x2
 #define perrmask_m_perr 0x4
@@ -252,37 +241,37 @@
 #define perrmask_m_cre 0x800
 #define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL
 union TPchipPERRMASK {   
-    struct  {
-        unsigned int perrmask_v_lost : 1;
-        unsigned perrmask_v_serr : 1;
-        unsigned perrmask_v_perr : 1;
-        unsigned perrmask_v_dcrto : 1;
-        unsigned perrmask_v_sge : 1;
-        unsigned perrmask_v_ape : 1;
-        unsigned perrmask_v_ta : 1;
-        unsigned perrmask_v_rdpe : 1;
-        unsigned perrmask_v_nds : 1;
-        unsigned perrmask_v_rto : 1;
-        unsigned perrmask_v_uecc : 1;
-        unsigned perrmask_v_cre : 1;                 
-        unsigned perrmask_v_rsvd1 : 20;
-	unsigned perrmask_v_rsvd2 : 32;
+	struct  {
+		unsigned int perrmask_v_lost : 1;
+		unsigned perrmask_v_serr : 1;
+		unsigned perrmask_v_perr : 1;
+		unsigned perrmask_v_dcrto : 1;
+		unsigned perrmask_v_sge : 1;
+		unsigned perrmask_v_ape : 1;
+		unsigned perrmask_v_ta : 1;
+		unsigned perrmask_v_rdpe : 1;
+		unsigned perrmask_v_nds : 1;
+		unsigned perrmask_v_rto : 1;
+		unsigned perrmask_v_uecc : 1;
+		unsigned perrmask_v_cre : 1;                 
+		unsigned perrmask_v_rsvd1 : 20;
+		unsigned perrmask_v_rsvd2 : 32;
         } perrmask_r_bits;
-    int perrmask_q_whole [2];
-    } ;                       
+	int perrmask_q_whole [2];
+};                       
 
 /*
  * Memory spaces:
  */
-#define TSUNAMI_PCI0_MEM		(IDENT_ADDR + TS_BIAS + 0x000000000UL)
-#define TSUNAMI_PCI0_IACK_SC		(IDENT_ADDR + TS_BIAS + 0x1F8000000UL)
-#define TSUNAMI_PCI0_IO			(IDENT_ADDR + TS_BIAS + 0x1FC000000UL)
-#define TSUNAMI_PCI0_CONF		(IDENT_ADDR + TS_BIAS + 0x1FE000000UL)
-
-#define TSUNAMI_PCI1_MEM		(IDENT_ADDR + TS_BIAS + 0x200000000UL)
-#define TSUNAMI_PCI1_IACK_SC		(IDENT_ADDR + TS_BIAS + 0x3F8000000UL)
-#define TSUNAMI_PCI1_IO			(IDENT_ADDR + TS_BIAS + 0x3FC000000UL)
-#define TSUNAMI_PCI1_CONF		(IDENT_ADDR + TS_BIAS + 0x3FE000000UL)
+#define HOSE(h) (((unsigned long)(h)) << 33)
+
+#define TSUNAMI_MEM(h)	     (IDENT_ADDR + TS_BIAS + 0x000000000UL + HOSE(h))
+#define _TSUNAMI_IACK_SC(h)  (IDENT_ADDR + TS_BIAS + 0x1F8000000UL + HOSE(h))
+#define TSUNAMI_IO(h)	     (IDENT_ADDR + TS_BIAS + 0x1FC000000UL + HOSE(h))
+#define TSUNAMI_CONF(h)	     (IDENT_ADDR + TS_BIAS + 0x1FE000000UL + HOSE(h))
+
+#define TSUNAMI_IACK_SC	     _TSUNAMI_IACK_SC(0) /* hack! */
+
 
 /*
  * Data structure for handling TSUNAMI machine checks:
@@ -319,51 +308,44 @@
  * can only use linear accesses to get at PCI memory and I/O spaces.
  */
 
-/* HACK ALERT! HACK ALERT! */
-/* HACK ALERT! HACK ALERT! */
-
-/* Only using PCI bus 0 for now in all routines.  */
-
-#define TSUNAMI_IACK_SC  TSUNAMI_PCI0_IACK_SC
-
-/* HACK ALERT! HACK ALERT! */
-/* HACK ALERT! HACK ALERT! */
-
 #define vucp	volatile unsigned char *
 #define vusp	volatile unsigned short *
 #define vuip	volatile unsigned int *
 #define vulp	volatile unsigned long *
 
+#define XADDR	((addr) & 0xffffffffUL)
+#define XHOSE	(((addr) >> 32) & 3UL)
+
 __EXTERN_INLINE unsigned int tsunami_inb(unsigned long addr)
 {
-	return __kernel_ldbu(*(vucp)(addr + TSUNAMI_PCI0_IO));
+	return __kernel_ldbu(*(vucp)(XADDR + TSUNAMI_IO(XHOSE)));
 }
 
 __EXTERN_INLINE void tsunami_outb(unsigned char b, unsigned long addr)
 {
-	__kernel_stb(b, *(vucp)(addr + TSUNAMI_PCI0_IO));
+	__kernel_stb(b, *(vucp)(XADDR + TSUNAMI_IO(XHOSE)));
 	mb();
 }
 
 __EXTERN_INLINE unsigned int tsunami_inw(unsigned long addr)
 {
-	return __kernel_ldwu(*(vusp)(addr+TSUNAMI_PCI0_IO));
+	return __kernel_ldwu(*(vusp)(XADDR + TSUNAMI_IO(XHOSE)));
 }
 
 __EXTERN_INLINE void tsunami_outw(unsigned short b, unsigned long addr)
 {
-	__kernel_stw(b, *(vusp)(addr+TSUNAMI_PCI0_IO));
+	__kernel_stw(b, *(vusp)(XADDR + TSUNAMI_IO(XHOSE)));
 	mb();
 }
 
 __EXTERN_INLINE unsigned int tsunami_inl(unsigned long addr)
 {
-	return *(vuip)(addr+TSUNAMI_PCI0_IO);
+	return *(vuip)(XADDR + TSUNAMI_IO(XHOSE));
 }
 
 __EXTERN_INLINE void tsunami_outl(unsigned int b, unsigned long addr)
 {
-	*(vuip)(addr+TSUNAMI_PCI0_IO) = b;
+	*(vuip)(XADDR + TSUNAMI_IO(XHOSE)) = b;
 	mb();
 }
 
@@ -373,45 +355,45 @@
 
 __EXTERN_INLINE unsigned long tsunami_readb(unsigned long addr)
 {
-	return __kernel_ldbu(*(vucp)(addr+TSUNAMI_PCI0_MEM));
+	return __kernel_ldbu(*(vucp)(XADDR + TSUNAMI_MEM(XHOSE)));
 }
 
 __EXTERN_INLINE unsigned long tsunami_readw(unsigned long addr)
 {
-	return __kernel_ldwu(*(vusp)(addr+TSUNAMI_PCI0_MEM));
+	return __kernel_ldwu(*(vusp)(XADDR + TSUNAMI_MEM(XHOSE)));
 }
 
 __EXTERN_INLINE unsigned long tsunami_readl(unsigned long addr)
 {
-	return *(vuip)(addr+TSUNAMI_PCI0_MEM);
+	return *(vuip)(XADDR + TSUNAMI_MEM(XHOSE));
 }
 
 __EXTERN_INLINE unsigned long tsunami_readq(unsigned long addr)
 {
-	return *(vulp)(addr+TSUNAMI_PCI0_MEM);
+	return *(vulp)(XADDR + TSUNAMI_MEM(XHOSE));
 }
 
 __EXTERN_INLINE void tsunami_writeb(unsigned char b, unsigned long addr)
 {
-	__kernel_stb(b, *(vucp)(addr+TSUNAMI_PCI0_MEM));
+	__kernel_stb(b, *(vucp)(XADDR + TSUNAMI_MEM(XHOSE)));
 	mb();
 }
 
 __EXTERN_INLINE void tsunami_writew(unsigned short b, unsigned long addr)
 {
-	__kernel_stw(b, *(vusp)(addr+TSUNAMI_PCI0_MEM));
+	__kernel_stw(b, *(vusp)(XADDR + TSUNAMI_MEM(XHOSE)));
 	mb();
 }
 
 __EXTERN_INLINE void tsunami_writel(unsigned int b, unsigned long addr)
 {
-	*(vuip)(addr+TSUNAMI_PCI0_MEM) = b;
+	*(vuip)(XADDR + TSUNAMI_MEM(XHOSE)) = b;
 	mb();
 }
 
 __EXTERN_INLINE void tsunami_writeq(unsigned long b, unsigned long addr)
 {
-	*(vulp)(addr+TSUNAMI_PCI0_MEM) = b;
+	*(vulp)(XADDR + TSUNAMI_MEM(XHOSE)) = b;
 	mb();
 }
 
@@ -419,13 +401,16 @@
 
 __EXTERN_INLINE unsigned long tsunami_dense_mem(unsigned long addr)
 {
-	return TSUNAMI_PCI0_MEM;
+	return TSUNAMI_MEM(XHOSE);
 }
 
 #undef vucp
 #undef vusp
 #undef vuip
 #undef vulp
+
+#undef XADDR
+#undef XHOSE
 
 #ifdef __WANT_IO_DEF
 

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