patch-1.3.71 linux/include/asm-sparc/psr.h

• Lines: 157
• Date: Mon Mar 4 08:50:03 1996
• Orig file: v1.3.70/linux/include/asm-sparc/psr.h
• Orig date: Sat Nov 25 19:04:51 1995

diff -u --recursive --new-file v1.3.70/linux/include/asm-sparc/psr.h linux/include/asm-sparc/psr.h
@@ -1,4 +1,4 @@
-/* $Id: psr.h,v 1.5 1995/11/25 02:32:31 davem Exp $
+/* $Id: psr.h,v 1.10 1996/03/01 07:20:57 davem Exp $
  * psr.h: This file holds the macros for masking off various parts of
  *        the processor status register on the Sparc. This is valid
  *        for Version 8. On the V9 this is renamed to the PSTATE
@@ -11,10 +11,6 @@
 #ifndef __LINUX_SPARC_PSR_H
 #define __LINUX_SPARC_PSR_H
 
-#define __LINUX_SPARC_V8  /* duh */
-
-#ifdef __LINUX_SPARC_V8
-
 /* The Sparc PSR fields are laid out as the following:
  *
  *  ------------------------------------------------------------------------
@@ -22,7 +18,6 @@
  *  | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
  *  ------------------------------------------------------------------------
  */
-
 #define PSR_CWP     0x0000001f         /* current window pointer     */
 #define PSR_ET      0x00000020         /* enable traps field         */
 #define PSR_PS      0x00000040         /* previous privilege level   */
@@ -30,6 +25,7 @@
 #define PSR_PIL     0x00000f00         /* processor interrupt level  */
 #define PSR_EF      0x00001000         /* enable floating point      */
 #define PSR_EC      0x00002000         /* enable co-processor        */
+#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
 #define PSR_ICC     0x00f00000         /* integer condition codes    */
 #define PSR_C       0x00100000         /* carry bit                  */
 #define PSR_V       0x00200000         /* overflow bit               */
@@ -38,6 +34,8 @@
 #define PSR_VERS    0x0f000000         /* cpu-version field          */
 #define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
 
+#ifdef __KERNEL__
+
 #ifndef __ASSEMBLY__
 /* Get the %psr register. */
 extern inline unsigned int get_psr(void)
@@ -50,8 +48,9 @@
 
 extern inline void put_psr(unsigned int new_psr)
 {
-  __asm__("wr %0, 0x0, %%psr\n\t" : :
-	  "r" (new_psr));
+	__asm__ __volatile__("wr %0, 0x0, %%psr\n\t"
+			     "nop; nop; nop;\n\t" : :
+			     "r" (new_psr));
 }
 
 /* Get the %fsr register.  Be careful, make sure the floating point
@@ -74,101 +73,6 @@
 
 #endif /* !(__ASSEMBLY__) */
 
-#endif /* !(__LINUX_SPARC_V8) */
-
-#ifdef __LINUX_SPARC_V9
-
-/* The information available in the %psr on the V8 is spread amongst
- * a whole bunch of registers on the V9. The main one being PSTATE.
- *
- *   --------------------------------------------------------
- *   |  CLE  | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
- *   |   9   |  8  |  7-6 |  5  |  4  |  3 |   2  |  1 |  0 |
- *   --------------------------------------------------------
- *
- * Writes and reads to PSTATE are done via 'wrpr' and 'rdpr' instructions.
- *
- * For example:  wrpr %o2, or'd_bit_pattern, %pstate
- *               rdpr %pstate, %o3
- */
-
-#define PSTATE_AG    0x001   /* Alternate Globals             */
-#define PSTATE_IE    0x002   /* Interrupt Enable              */
-#define PSTATE_PRIV  0x004   /* Current privilege level       */
-#define PSTATE_AM    0x008   /* Address mask (data reads can  */
-			     /* be chosen to be either big or */
-			     /* little endian on V9).         */
-#define PSTATE_PEF   0x010   /* enable floating point         */
-#define PSTATE_RED   0x020   /* RED trap state (set if trap   */
-                             /* trap_level == max_tl).        */
-#define PSTATE_MM    0x0c0   /* Memory model (Total Store     */
-                             /* Order=0, Partial Store Order  */
-                             /* =1 or Relaxed Memory Order=2) */
-#define PSTATE_TLE   0x100   /* Trap Little Endian            */
-#define PSTATE_CLE   0x200   /* Current Little Endian         */
-
-
-extern inline unsigned int get_v9_pstate(void)
-{
-	unsigned int pstate;
-	__asm__ __volatile__("rdpr %pstate, %0\n\t" :
-			     "=r" (pstate));
-	return pstate;
-}
-
-extern inline void put_v9_pstate(unsigned int pstate)
-{
-	__asm__ __volatile__("wrpr %0, 0x0, %pstate\n\t" : :
-			     "r" (pstate));
-	return;
-}
-
-/* The Version Register holds vendor information for the chip:
- *
- *  ---------------------------------------------------------------------------
- *  | manufacturer | implementation | mask | reserved | maxtl | resv | maxwin |
- *  |  63-48       |   47-32        | 31-24|   23-16  | 15-8  | 7-5  |  4-0   |
- *  ---------------------------------------------------------------------------
- *
- */
-
-#define VERS_MAXWIN  0x000000000000001f     /* 'nwindows' on this chip       */
-#define VERS_MAXTL   0x00000000000ff000     /* Maximum Trap-level supported  */
-#define VERS_MASK    0x0000000ff0000000     /* impl. dep. chip mask revision */
-#define VERS_MANUF   0xffff000000000000     /* Manufacturer ID code          */
-
-extern inline unsigned int get_v9_version(void)
-{
-	unsigned int vers;
-	__asm__ __volatile__("rdpr %ver, %0\n\t" :
-			     "=r" (vers));
-	return vers;
-}
-
-extern inline unsigned int get_v9_tstate(void)
-{
-	unsigned int tstate;
-	__asm__ __volatile__("rdpr %tstate, %0\n\t" :
-			     "=r" (pstate));
-	return tstate;
-}
-
-extern inline unsigned int get_v9_pil(void)
-{
-	unsigned int pil;
-	__asm__ __volatile__("rdpr %pil, %0\n\t" :
-			     "=r" (pstate));
-	return pil;
-}
-
-extern inline void put_v9_pil(unsigned int pil)
-{
-	__asm__ __volatile__("wrpr %0, 0x0, %pil\n\t" : :
-			     "r" (pil));
-	return;
-}
-
-
-#endif /* !(__LINUX_SPARC_V9) */
+#endif /* (__KERNEL__) */
 
 #endif /* !(__LINUX_SPARC_PSR_H) */