patch-1.3.4 linux/include/asm-sparc/system.h

• Lines: 153
• Date: Sat Jun 17 09:34:09 1995
• Orig file: v1.3.3/linux/include/asm-sparc/system.h
• Orig date: Sun Feb 26 20:46:20 1995

diff -u --recursive --new-file v1.3.3/linux/include/asm-sparc/system.h linux/include/asm-sparc/system.h
@@ -4,50 +4,84 @@
 #include <asm/segment.h>
 
 /*
- * System defines.. Note that this is included both from .c and .S
- * files, so it does only defines, not any C code.
- */
-
-/*
  * I wish the boot time image was as beautiful as the Alpha's
  * but no such luck. The icky PROM loads us at 0x0, and jumps
- * to magic address 0x4000 to start thing going. This means that
- * I can stick the pcb and user/kernel stacks in the area from
- * 0x0-0x4000 and be reasonably sure that this is sane.
+ * to magic address 0x4000 to start things going.
  *
  * Sorry, I can't impress people with cool looking 64-bit values
- * yet. ;-)
+ * yet. Wait till V9 ;-)
  */
 
+#include <asm/page.h>
 #include <asm/openprom.h>
 #include <asm/psr.h>
 
-#define INIT_PCB	0x00011fe0
-#define INIT_STACK	0x00013fe0
-#define START_ADDR	0x00004000
-#define START_SIZE	(32*1024)
-#define EMPTY_PGT	0x00001000
-#define EMPTY_PGE	0x00001000
-#define ZERO_PGE	0x00001000
-
-#define IRQ_ENA_ADR     0x2000        /* This is a bitmap of all activated IRQ's
-				       * which is mapped in head.S during boot.
-				       */
+#define START_ADDR	(0x00004000)
+#define EMPTY_PGT       (&empty_bad_page)
+#define EMPTY_PGE	(&empty_bad_page_table)
+#define ZERO_PGE	(&empty_zero_page)
 
 #ifndef __ASSEMBLY__
 
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+  sun4        = 0x00,
+  sun4c       = 0x01,
+  sun4m       = 0x02,
+  sun4d       = 0x03,
+  sun4e       = 0x04,
+  sun4u       = 0x05,
+  sun_unknown = 0x06,
+};
+
+extern enum sparc_cpu sparc_cpu_model;
+
+extern unsigned long empty_bad_page;
+extern unsigned long empty_bad_page_table;
+extern unsigned long empty_zero_page;
+
 extern void wrent(void *, unsigned long);
 extern void wrkgp(unsigned long);
 extern struct linux_romvec *romvec;
 
-#define halt() { romvec->pv_halt(); }
+#define halt() do { \
+			 printk("Entering monitor in file %s at line %d\n", __FILE__, __LINE__); \
+romvec->pv_halt(); } while(0)
+
 #define move_to_user_mode() halt()
-#define switch_to(x) halt()
 
 #ifndef stbar  /* store barrier Sparc insn to synchronize stores in PSO */
 #define stbar() __asm__ __volatile__("stbar": : :"memory")
 #endif
 
+/* When a context switch happens we must flush all user windows so that
+ * the windows of the current process are flushed onto it's stack. This
+ * way the windows are all clean for the next process.
+ */
+
+#define flush_user_windows() \
+do { __asm__ __volatile__( \
+			  "save %sp, -64, %sp\n\t" \
+			  "save %sp, -64, %sp\n\t" \
+			  "save %sp, -64, %sp\n\t" \
+			  "save %sp, -64, %sp\n\t" \
+			  "save %sp, -64, %sp\n\t" \
+			  "save %sp, -64, %sp\n\t" \
+			  "save %sp, -64, %sp\n\t" \
+			  "restore\n\t" \
+			  "restore\n\t" \
+			  "restore\n\t" \
+			  "restore\n\t" \
+			  "restore\n\t" \
+			  "restore\n\t" \
+			  "restore\n\t"); } while(0)
+
+extern void sparc_switch_to(void *new_task);
+
+#define switch_to(p) sparc_switch_to(p)
+
 /* Changing the PIL on the sparc is a bit hairy. I'll figure out some
  * more optimized way of doing this soon. This is bletcherous code.
  */
@@ -73,36 +107,6 @@
 #define iret() __asm__ __volatile__ ("jmp %%l1\n\t" \
 				     "rett %%l2\n\t": : :"memory")
 
-#define _set_gate(gate_addr,type,dpl,addr) \
-__asm__ __volatile__ ("nop\n\t")
-
-#define set_intr_gate(n,addr) \
-	_set_gate(&idt[n],14,0,addr)
-
-#define set_trap_gate(n,addr) \
-	_set_gate(&idt[n],15,0,addr)
-
-#define set_system_gate(n,addr) \
-	_set_gate(&idt[n],15,3,addr)
-
-#define set_call_gate(a,addr) \
-	_set_gate(a,12,3,addr)
-
-
-extern inline unsigned int get_psr(void)
-{
-  unsigned int ret_val;
-  __asm__("rd %%psr, %0\n\t" :
-	  "=r" (ret_val));
-  return ret_val;
-}
-
-extern inline void put_psr(unsigned int new_psr)
-{
-  __asm__("wr %0, 0x0, %%psr\n\t" : :
-	  "r" (new_psr));
-}
-
 /* Must this be atomic? */
 
 extern inline void *xchg_u32(int * m, unsigned long val)
@@ -110,7 +114,7 @@
 	unsigned long dummy;
 
 	__asm__ __volatile__(
-		"ld %1,%2   ! xchg_u32() is here\n\t"
+		"ld %1,%2\n\t"
 		"st %0, %1\n\t"
 		"or %%g0, %2, %0"
 		: "=r" (val), "=m" (*m), "=r" (dummy)