bk://bk.arm.linux.org.uk/linux-2.6-rmk
rmk@flint.arm.linux.org.uk|ChangeSet|20040408214903|46447 rmk

# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
#   2004/04/08 14:53:48-07:00 akpm@bix.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into bix.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/04/08 14:53:46-07:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/04/08 22:49:03+01:00 rmk@flint.arm.linux.org.uk 
#   [ARM] Move definition of the kernel module space to asm-arm
#   
#   Since all machine classes define module space the same way, we
#   move this into the common ARM code.
# 
# include/asm-arm/memory.h
#   2004/04/08 22:47:03+01:00 rmk@flint.arm.linux.org.uk +11 -0
#   Add MODULE_START and MODULE_END.
#   Add check to ensure that user space doesn't overlap module space.
# 
# include/asm-arm/arch-tbox/vmalloc.h
#   2004/04/08 22:47:03+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-shark/vmalloc.h
#   2004/04/08 22:47:03+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-sa1100/vmalloc.h
#   2004/04/08 22:47:03+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-s3c2410/vmalloc.h
#   2004/04/08 22:47:03+01:00 rmk@flint.arm.linux.org.uk +0 -4
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-rpc/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-pxa/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-omap/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-nexuspci/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-l7200/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-iop3xx/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-integrator/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-epxa10db/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-ebsa285/vmalloc.h
#   2004/04/08 22:47:02+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-ebsa110/vmalloc.h
#   2004/04/08 22:47:01+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-clps711x/vmalloc.h
#   2004/04/08 22:47:01+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-cl7500/vmalloc.h
#   2004/04/08 22:47:01+01:00 rmk@flint.arm.linux.org.uk +0 -4
#   Remove MODULE_START and MODULE_END
# 
# include/asm-arm/arch-adifcc/vmalloc.h
#   2004/04/08 22:47:01+01:00 rmk@flint.arm.linux.org.uk +0 -3
#   Remove MODULE_START and MODULE_END
# 
# ChangeSet
#   2004/04/08 20:42:54+01:00 rmk@flint.arm.linux.org.uk 
#   [ARM] Fix ordering of machine class selection.
#   
#   The machine class should be in alphabetical order.  Swap ordering
#   of the recently added TI and S3C2410 entries to return it to this
#   ordering.
# 
# arch/arm/Kconfig
#   2004/04/08 20:41:09+01:00 rmk@flint.arm.linux.org.uk +3 -3
#   Fix ordering of machine class selection - return it to alphabetical
#   order.
# 
# ChangeSet
#   2004/04/08 20:32:47+01:00 elf@com.rmk.(none) 
#   [ARM PATCH] 1806/1: Adding barrier() to show_stack () for proper backtracing
#   
#   Patch from Marc Singer
#   
#   As suggested by Russell, we add a barrier() before returning from
#   stack_trace().  This was helpful when diagnosing a problem with a
#   kernel transition to user-space where the problem was a lack of
#   floating point support in the kernel.  Without this change, the
#   backtrace reported an error.
#   
#   It is possible that this change has already been made.  I don't see it
#   in any of the applied patches that I can read.
#   
# 
# arch/arm/kernel/traps.c
#   2004/04/08 01:00:00+01:00 elf@com.rmk.(none) +1 -0
#   [PATCH] 1806/1: Adding barrier() to show_stack () for proper backtracing
# 
# ChangeSet
#   2004/04/05 15:36:29-07:00 akpm@bix.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into bix.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/04/05 15:36:26-07:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/04/05 22:31:45+01:00 hugh@com.rmk.(none) 
#   [PATCH] make_coherent pgoff
#   
#   Patch from Hugh Dickins
#   
#   In wandering through the Linus 2.6 tree preparing for changeover of
#   i_mmap and i_mmap_shared to Rajesh's prio tree for object-based rmap...
#   I noticed that pgoff in make_coherent doesn't add up (plus, I think
#   we need to mask out the word "don't" in the comment further down).
#   2.4.25 looks equally wrong.
# 
# arch/arm/mm/fault-armv.c
#   2004/04/05 22:29:10+01:00 hugh@com.rmk.(none) +4 -2
#   [PATCH] make_coherent pgoff
# 
# ChangeSet
#   2004/04/05 22:22:34+01:00 petri.koistinen@fi.rmk.(none) 
#   [PATCH] update Compaq Personal Server URL
#   
#   Patch from Petri T. Koistinen
#   
#   Update of Compaq Personal Server URL.
# 
# arch/arm/mach-footbridge/Kconfig
#   2004/04/05 22:20:43+01:00 petri.koistinen@fi.rmk.(none) +1 -1
#   [PATCH] update Compaq Personal Server URL
# 
# ChangeSet
#   2004/04/05 22:17:46+01:00 rmk@flint.arm.linux.org.uk 
#   [ARM] Add ecard_(request|release)_resources().
# 
# include/asm-arm/ecard.h
#   2004/04/05 22:15:54+01:00 rmk@flint.arm.linux.org.uk +7 -1
#   Add ecard_(request|release)_resources().
# 
# arch/arm/kernel/ecard.c
#   2004/04/05 22:15:54+01:00 rmk@flint.arm.linux.org.uk +36 -0
#   Add ecard_(request|release)_resources()
# 
# ChangeSet
#   2004/04/05 19:53:19+01:00 rmk@flint.arm.linux.org.uk 
#   [ARM] Fix silent build error caused by undefined symbol.
#   
#   Current binutils silently ignores certain undefined symbols; this
#   cset fixes one such instance.
# 
# include/asm-arm/thread_info.h
#   2004/04/05 19:51:16+01:00 rmk@flint.arm.linux.org.uk +2 -2
#   TI_USED_MATH is no longer used; it should be TI_USED_CP.
# 
# ChangeSet
#   2004/04/05 16:05:54+01:00 rmk@flint.arm.linux.org.uk 
#   [ARM] Clean up formatting of s3c2410 help texts.
# 
# arch/arm/mach-s3c2410/Kconfig
#   2004/04/05 16:03:50+01:00 rmk@flint.arm.linux.org.uk +5 -5
#   Clean up formatting of help texts.
# 
# ChangeSet
#   2004/04/05 16:01:52+01:00 ben-linux@org.rmk.(none) 
#   [ARM PATCH] 1794/1: S3C2410 - arch/arm/kernel patches [ repost 1791/1 ]
#   
#   Patch from Ben Dooks
#   
#   arch/arm/kernel patch for S3C2410 support
#   
#    - default configurations for S3C2410
#    - build changes for S3C2410
#    - IRQ support for kernel entry
#    - debug serial support
# 
# arch/arm/configs/s3c2410_defconfig
#   2004/04/05 15:59:35+01:00 ben-linux@org.rmk.(none) +799 -0
# 
# arch/arm/configs/s3c2410_defconfig
#   2004/04/05 15:59:35+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/configs/s3c2410_defconfig
# 
# arch/arm/configs/bast_defconfig
#   2004/04/05 15:59:29+01:00 ben-linux@org.rmk.(none) +802 -0
# 
# arch/arm/mm/Kconfig
#   2004/04/05 15:59:29+01:00 ben-linux@org.rmk.(none) +6 -3
#   [PATCH] 1794/1: S3C2410 - arch/arm/kernel patches [ repost 1791/1 ]
# 
# arch/arm/kernel/entry-armv.S
#   2004/04/05 15:59:29+01:00 ben-linux@org.rmk.(none) +123 -0
#   [PATCH] 1794/1: S3C2410 - arch/arm/kernel patches [ repost 1791/1 ]
# 
# arch/arm/configs/bast_defconfig
#   2004/04/05 15:59:29+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/configs/bast_defconfig
# 
# arch/arm/kernel/debug.S
#   2004/04/05 15:59:28+01:00 ben-linux@org.rmk.(none) +88 -0
#   [PATCH] 1794/1: S3C2410 - arch/arm/kernel patches [ repost 1791/1 ]
# 
# arch/arm/Makefile
#   2004/04/05 15:59:28+01:00 ben-linux@org.rmk.(none) +1 -0
#   [PATCH] 1794/1: S3C2410 - arch/arm/kernel patches [ repost 1791/1 ]
# 
# arch/arm/Kconfig
#   2004/04/05 15:59:28+01:00 ben-linux@org.rmk.(none) +38 -0
#   [PATCH] 1794/1: S3C2410 - arch/arm/kernel patches [ repost 1791/1 ]
# 
# ChangeSet
#   2004/04/05 15:37:18+01:00 ben-linux@org.rmk.(none) 
#   [ARM PATCH] 1792/1: S3C2410 - arch/arm/boot [ fix for 1789/1 ]
#   
#   Patch from Ben Dooks
#   
#   arch/arm/boot support for S3C2410
#   
#   support for boot (and debug) messages via EmbeddedICE (CP14)
#   comms registers.
#   
#   fixed typos from 1789/1
# 
# arch/arm/boot/compressed/ice-dcc.S
#   2004/04/05 15:35:15+01:00 ben-linux@org.rmk.(none) +17 -0
# 
# arch/arm/boot/compressed/misc.c
#   2004/04/05 15:35:15+01:00 ben-linux@org.rmk.(none) +16 -0
#   [PATCH] 1792/1: S3C2410 - arch/arm/boot [ fix for 1789/1 ]
# 
# arch/arm/boot/compressed/ice-dcc.S
#   2004/04/05 15:35:15+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/boot/compressed/ice-dcc.S
# 
# arch/arm/boot/compressed/head.S
#   2004/04/05 15:35:14+01:00 ben-linux@org.rmk.(none) +6 -0
#   [PATCH] 1792/1: S3C2410 - arch/arm/boot [ fix for 1789/1 ]
# 
# arch/arm/boot/compressed/Makefile
#   2004/04/05 15:35:14+01:00 ben-linux@org.rmk.(none) +4 -0
#   [PATCH] 1792/1: S3C2410 - arch/arm/boot [ fix for 1789/1 ]
# 
# arch/arm/boot/Makefile
#   2004/04/05 15:35:14+01:00 ben-linux@org.rmk.(none) +4 -0
#   [PATCH] 1792/1: S3C2410 - arch/arm/boot [ fix for 1789/1 ]
# 
# ChangeSet
#   2004/04/05 14:59:51+01:00 ben-linux@org.rmk.(none) 
#   [ARM PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
#   
#   Patch from Ben Dooks
#   
#   Core support for S3C2410 based machines
#   
#   machine support for Simtec BAST, VR1000 and
#   IPAQ H1940
#   
#   repost of 1790/1 with configuration definition fixed
# 
# arch/arm/mach-s3c2410/s3c2410.h
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +6 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/s3c2410.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +191 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/mach-vr1000.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +164 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/mach-h1940.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +100 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/mach-bast.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +194 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/irq.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +598 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/s3c2410.h
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/s3c2410.h
# 
# arch/arm/mach-s3c2410/s3c2410.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/s3c2410.c
# 
# arch/arm/mach-s3c2410/mach-vr1000.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/mach-vr1000.c
# 
# arch/arm/mach-s3c2410/mach-h1940.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/mach-h1940.c
# 
# arch/arm/mach-s3c2410/mach-bast.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/mach-bast.c
# 
# arch/arm/mach-s3c2410/irq.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/irq.c
# 
# arch/arm/mach-s3c2410/bast.h
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +2 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/bast-irq.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +132 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/Makefile
#   2004/04/05 14:37:21+01:00 ben-linux@org.rmk.(none) +18 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/bast.h
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/bast.h
# 
# arch/arm/mach-s3c2410/bast-irq.c
#   2004/04/05 14:36:14+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/bast-irq.c
# 
# arch/arm/mach-s3c2410/Makefile
#   2004/04/05 14:37:21+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/Makefile
# 
# arch/arm/mach-s3c2410/Kconfig
#   2004/04/05 14:36:58+01:00 ben-linux@org.rmk.(none) +25 -0
#   [PATCH] 1793/1: S3C2410 - arch/arm/mach-s3c2410 [ repost of 1790/1 ]
# 
# arch/arm/mach-s3c2410/Kconfig
#   2004/04/05 14:36:58+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-s3c2410/Kconfig
# 
# ChangeSet
#   2004/04/05 14:54:49+01:00 ben-linux@org.rmk.(none) 
#   [ARM PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
#   
#   Patch from Ben Dooks
#   
#   This patch is a repost of 1778/1 with the memory.h file fixed.
#   
#   
#   
#   This patch contains all the necessary include files for include/asm-arm/arch-s3c2410 for Samsing S3C2410 SoC CPU support. 
#   
#   
#   
#   The patch also includes the support headers for IPAQ H1940, Simtec BAST and VR1000 board support.
# 
# include/asm-arm/arch-s3c2410/vr1000-map.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +112 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/vr1000-irq.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +30 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/vr1000-cpld.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +22 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/vmalloc.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +40 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/uncompress.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +110 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/timex.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +33 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/time.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +173 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/system.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +84 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/serial.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +28 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-watchdog.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +44 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-timer.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +108 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-serial.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +140 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-rtc.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +63 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-lcd.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +107 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/vr1000-map.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/vr1000-map.h
# 
# include/asm-arm/arch-s3c2410/vr1000-irq.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/vr1000-irq.h
# 
# include/asm-arm/arch-s3c2410/vr1000-cpld.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/vr1000-cpld.h
# 
# include/asm-arm/arch-s3c2410/vmalloc.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/vmalloc.h
# 
# include/asm-arm/arch-s3c2410/uncompress.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/uncompress.h
# 
# include/asm-arm/arch-s3c2410/timex.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/timex.h
# 
# include/asm-arm/arch-s3c2410/time.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/time.h
# 
# include/asm-arm/arch-s3c2410/system.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/system.h
# 
# include/asm-arm/arch-s3c2410/serial.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/serial.h
# 
# include/asm-arm/arch-s3c2410/regs-watchdog.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-watchdog.h
# 
# include/asm-arm/arch-s3c2410/regs-timer.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-timer.h
# 
# include/asm-arm/arch-s3c2410/regs-serial.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-serial.h
# 
# include/asm-arm/arch-s3c2410/regs-rtc.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-rtc.h
# 
# include/asm-arm/arch-s3c2410/regs-lcd.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-lcd.h
# 
# include/asm-arm/arch-s3c2410/regs-irq.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +38 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-iis.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +63 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-gpio.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +604 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-clock.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +72 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/param.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +27 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/memory.h
#   2004/04/05 11:15:15+01:00 ben-linux@org.rmk.(none) +61 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/map.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +148 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/irqs.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +115 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/io.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +198 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/ide.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +49 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/hardware.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +43 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/dma.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +169 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/bast-map.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +150 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/bast-irq.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +32 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/regs-irq.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-irq.h
# 
# include/asm-arm/arch-s3c2410/regs-iis.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-iis.h
# 
# include/asm-arm/arch-s3c2410/regs-gpio.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-gpio.h
# 
# include/asm-arm/arch-s3c2410/regs-clock.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/regs-clock.h
# 
# include/asm-arm/arch-s3c2410/param.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/param.h
# 
# include/asm-arm/arch-s3c2410/memory.h
#   2004/04/05 11:15:15+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/memory.h
# 
# include/asm-arm/arch-s3c2410/map.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/map.h
# 
# include/asm-arm/arch-s3c2410/irqs.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/irqs.h
# 
# include/asm-arm/arch-s3c2410/io.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/io.h
# 
# include/asm-arm/arch-s3c2410/ide.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/ide.h
# 
# include/asm-arm/arch-s3c2410/hardware.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/hardware.h
# 
# include/asm-arm/arch-s3c2410/dma.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/dma.h
# 
# include/asm-arm/arch-s3c2410/bast-map.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/bast-map.h
# 
# include/asm-arm/arch-s3c2410/bast-irq.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/bast-irq.h
# 
# include/asm-arm/arch-s3c2410/bast-cpld.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +25 -0
#   [PATCH] 1788/1: SC2410 include/asm-arm/arch-s3c2410 [repost of 1778/1]
# 
# include/asm-arm/arch-s3c2410/bast-cpld.h
#   2004/04/02 16:45:47+01:00 ben-linux@org.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-s3c2410/bast-cpld.h
# 
# ChangeSet
#   2004/04/04 16:01:39-07:00 akpm@bix.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into bix.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/04/04 16:01:36-07:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/04/04 22:34:25+01:00 nico@org.rmk.(none) 
#   [ARM PATCH] 1783/1: more PXA reg definitions
#   
#   Patch from Nicolas Pitre
#   
# 
# include/asm-arm/arch-pxa/pxa-regs.h
#   2003/12/15 01:07:42+00:00 nico@org.rmk.(none) +29 -0
#   [PATCH] 1783/1: more PXA reg definitions
# 
# ChangeSet
#   2004/04/04 22:08:18+01:00 nico@org.rmk.(none) 
#   [ARM PATCH] 1782/1: discontigmem support for PXA chips
#   
#   Patch from Nicolas Pitre
#   
# 
# include/asm-arm/arch-pxa/memory.h
#   2004/03/26 16:57:59+00:00 nico@org.rmk.(none) +48 -0
#   [PATCH] 1782/1: discontigmem support for PXA chips
# 
# ChangeSet
#   2004/04/04 13:40:31+01:00 tony@com.rmk.(none) 
#   [ARM PATCH] 1781/1: Add TI OMAP support, arch files
#   
#   Patch from Tony Lindgren
#   
#   This patch adds the arch files for Texas Instruments OMAP-1510 and 
#   1610 processors. 
#   
#   OMAP is an embedded ARM processor with integrated DSP.
#   
#   OMAP-1610 has hardware support for USB OTG, which might be of interest
#   to Linux developers. OMAP-1610 could be easily be used as development 
#   platform to add USB OTG support to Linux.
#   
#   This patch is an updated version of patch 1769/1 with Russell King's
#   comments fixed. This patch requires patch 1777/1 applied.
#   
#   This patch is brought to you by various linux-omap developers.
# 
# arch/arm/mach-omap/omap-perseus2.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +116 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/ocpi.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +116 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/mux.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +124 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/leds.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +2 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/leds.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +23 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/leds-perseus2.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +103 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/leds-innovator.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +103 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/irq.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +224 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/innovator1610.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +91 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/gpio.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +755 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/fpga.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +209 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/dma.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +560 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/clocks.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +676 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/bus.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +280 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/Kconfig
#   2004/03/24 19:22:11+00:00 tony@com.rmk.(none) +113 -3
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/omap-perseus2.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/omap-perseus2.c
# 
# arch/arm/mach-omap/omap-generic.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +77 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/ocpi.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/ocpi.c
# 
# arch/arm/mach-omap/mux.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/mux.c
# 
# arch/arm/mach-omap/leds.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds.h
# 
# arch/arm/mach-omap/leds.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds.c
# 
# arch/arm/mach-omap/leds-perseus2.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds-perseus2.c
# 
# arch/arm/mach-omap/leds-innovator.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/leds-innovator.c
# 
# arch/arm/mach-omap/irq.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/irq.c
# 
# arch/arm/mach-omap/innovator1610.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/innovator1610.c
# 
# arch/arm/mach-omap/innovator1510.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +99 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/gpio.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/gpio.c
# 
# arch/arm/mach-omap/fpga.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/fpga.c
# 
# arch/arm/mach-omap/dma.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/dma.c
# 
# arch/arm/mach-omap/common.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +6 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/common.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +69 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/clocks.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/clocks.c
# 
# arch/arm/mach-omap/bus.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/bus.c
# 
# arch/arm/mach-omap/omap-generic.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/omap-generic.c
# 
# arch/arm/mach-omap/innovator1510.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/innovator1510.c
# 
# arch/arm/mach-omap/common.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/common.h
# 
# arch/arm/mach-omap/common.c
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/common.c
# 
# arch/arm/mach-omap/Makefile
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +36 -0
#   [PATCH] 1781/1: Add TI OMAP support, arch files
# 
# arch/arm/mach-omap/Makefile
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/Makefile
# 
# ChangeSet
#   2004/04/04 13:36:50+01:00 tony@com.rmk.(none) 
#   [ARM PATCH] 1780/1: Add TI OMAP support, include files
#   
#   Patch from Tony Lindgren
#   
#   This patch adds the include files for Texas Instruments OMAP-1510 and 
#   1610 processors. 
#   
#   OMAP is an embedded ARM processor with integrated DSP.
#   
#   OMAP-1610 has hardware support for USB OTG, which might be of interest
#   to Linux developers. OMAP-1610 could be easily be used as development 
#   platform to add USB OTG support to Linux.
#   
#   This patch is an updated version of patch 1768/1 with Russell King's
#   comments fixed. This patch requires patch 1777/1 applied.
#   
#   This patch is brought to you by various linux-omap developers.
# 
# include/asm-arm/arch-omap/serial.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +167 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/pm.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +150 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/mux.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +462 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/fpga.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +26 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/vmalloc.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +35 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/uncompress.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +76 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/timex.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +35 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/time.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +212 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/system.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +20 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/serial.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/serial.h
# 
# include/asm-arm/arch-omap/pm.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/pm.h
# 
# include/asm-arm/arch-omap/param.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +24 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/omap-perseus2.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +152 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/omap-h2.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +35 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/mux.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/mux.h
# 
# include/asm-arm/arch-omap/memory.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +92 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/irqs.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +262 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/io.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +24 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/hardware.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +327 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/gpio.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +68 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/fpga.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/fpga.h
# 
# include/asm-arm/arch-omap/dma.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +224 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/clocks.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +216 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/bus.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +97 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/vmalloc.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/vmalloc.h
# 
# include/asm-arm/arch-omap/uncompress.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/uncompress.h
# 
# include/asm-arm/arch-omap/timex.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/timex.h
# 
# include/asm-arm/arch-omap/time.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/time.h
# 
# include/asm-arm/arch-omap/system.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/system.h
# 
# include/asm-arm/arch-omap/param.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/param.h
# 
# include/asm-arm/arch-omap/omap1610.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +73 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/omap1510.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +54 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/omap-perseus2.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap-perseus2.h
# 
# include/asm-arm/arch-omap/omap-innovator.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +214 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/omap-h2.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap-h2.h
# 
# include/asm-arm/arch-omap/memory.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/memory.h
# 
# include/asm-arm/arch-omap/irqs.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/irqs.h
# 
# include/asm-arm/arch-omap/io.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/io.h
# 
# include/asm-arm/arch-omap/hardware.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/hardware.h
# 
# include/asm-arm/arch-omap/gpio.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/gpio.h
# 
# include/asm-arm/arch-omap/dma.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/dma.h
# 
# include/asm-arm/arch-omap/clocks.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/clocks.h
# 
# include/asm-arm/arch-omap/bus.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/bus.h
# 
# include/asm-arm/arch-omap/omap1610.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap1610.h
# 
# include/asm-arm/arch-omap/omap1510.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap1510.h
# 
# include/asm-arm/arch-omap/omap-innovator.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap-innovator.h
# 
# include/asm-arm/arch-omap/omap730.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +50 -0
#   [PATCH] 1780/1: Add TI OMAP support, include files
# 
# include/asm-arm/arch-omap/omap730.h
#   2004/03/25 17:34:51+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/include/asm-arm/arch-omap/omap730.h
# 
# ChangeSet
#   2004/04/04 13:32:38+01:00 tony@com.rmk.(none) 
#   [ARM PATCH] 1777/1: Add TI OMAP support to ARM core files
#   
#   Patch from Tony Lindgren
#   
#   This patch updates the ARM Linux core files to add support for 
#   Texas Instruments OMAP-1510, 1610, and 730 processors. 
#   
#   OMAP is an embedded ARM processor with integrated DSP.
#   
#   OMAP-1610 has hardware support for USB OTG, which might be of interest
#   to Linux developers. OMAP-1610 could be easily be used as development 
#   platform to add USB OTG support to Linux.
#   
#   This patch is an updated version of an earlier patch 1767/1 
#   with the dummy Kconfig added for OMAP as suggested by Russell King
#   here:
#   
#   http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=1767/1
#   
#   This patch is brought to you by various linux-omap developers.
# 
# include/asm-arm/proc-fns.h
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +8 -0
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# include/asm-arm/cacheflush.h
#   2004/03/15 17:01:34+00:00 tony@com.rmk.(none) +1 -1
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/mm/tlb-v4wbi.S
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +1 -1
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/kernel/entry-armv.S
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +27 -0
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/kernel/debug.S
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +26 -0
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/boot/Makefile
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +3 -0
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/Makefile
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +2 -0
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/Kconfig
#   2004/03/15 17:01:33+00:00 tony@com.rmk.(none) +7 -2
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/mach-omap/Kconfig
#   2004/03/16 01:08:17+00:00 tony@com.rmk.(none) +3 -0
#   [PATCH] 1777/1: Add TI OMAP support to ARM core files
# 
# arch/arm/mach-omap/Kconfig
#   2004/03/16 01:08:17+00:00 tony@com.rmk.(none) +0 -0
#   BitKeeper file /usr/src/bk/linux-2.6-rmk/arch/arm/mach-omap/Kconfig
# 
# ChangeSet
#   2004/03/27 02:24:52-08:00 akpm@bix.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into bix.(none):/usr/src/dead-bk-arm
# 
# arch/arm/Kconfig
#   2004/03/27 02:24:49-08:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/03/25 10:54:20-08:00 akpm@bix.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into bix.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/03/25 10:54:18-08:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/03/19 10:00:02-08:00 akpm@bix.(none) 
#   Merge bix.(none):/usr/src/bk25 into bix.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/03/19 09:59:59-08:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/03/15 22:29:04-08:00 akpm@bix.(none) 
#   Merge bix.(none):/usr/src/bk25 into bix.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/03/15 22:28:51-08:00 akpm@bix.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/26 11:28:15-08:00 akpm@mnm.(none) 
#   Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/02/26 11:28:09-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/23 20:16:50-08:00 akpm@mnm.(none) 
#   Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/02/23 20:16:44-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/20 18:41:24-08:00 akpm@mnm.(none) 
#   Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/02/20 18:41:17-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/20 13:48:13-08:00 akpm@mnm.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into mnm.(none):/usr/src/bk-arm
# 
# include/asm-arm/pci.h
#   2004/02/20 13:48:07-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/20 13:45:54-08:00 akpm@mnm.(none) 
#   Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm
# 
# arch/arm/Kconfig
#   2004/02/20 13:45:48-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/10 12:08:32-08:00 akpm@mnm.(none) 
#   Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm
# 
# include/asm-arm/pci.h
#   2004/02/10 12:08:26-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/06 13:18:37-08:00 akpm@mnm.(none) 
#   Merge mnm.(none):/usr/src/bk25 into mnm.(none):/usr/src/bk-arm
# 
# include/asm-arm/pci.h
#   2004/02/06 13:18:30-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
# ChangeSet
#   2004/02/06 10:43:46-08:00 akpm@mnm.(none) 
#   Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
#   into mnm.(none):/usr/src/bk-arm
# 
# include/asm-arm/pci.h
#   2004/02/06 10:43:40-08:00 akpm@mnm.(none) +0 -0
#   Auto merged
# 
diff -Nru a/arch/arm/Kconfig b/arch/arm/Kconfig
--- a/arch/arm/Kconfig	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/Kconfig	Thu Apr  8 14:54:32 2004
@@ -135,6 +135,16 @@
 config ARCH_SHARK
 	bool "Shark"
 
+config ARCH_S3C2410
+	bool "Samsung S3C2410"
+	help
+	  Samsung S3C2410X CPU based systems, such as the Simtec Electronics
+	  BAST (http://www.simtec.co.uk/products/EB110ITX/), the IPAQ 1940 or
+	  the Samsung SMDK2410 development board (and derviatives).
+
+config ARCH_OMAP
+	bool "TI OMAP"
+
 endchoice
 
 source "arch/arm/mach-clps711x/Kconfig"
@@ -151,6 +161,10 @@
 
 source "arch/arm/mach-sa1100/Kconfig"
 
+source "arch/arm/mach-omap/Kconfig"
+
+source "arch/arm/mach-s3c2410/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool
@@ -500,7 +514,7 @@
 
 config LEDS
 	bool "Timer and CPU usage LEDs"
-	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T
+	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP
 	help
 	  If you say Y here, the LEDs on your machine will be used
 	  to provide useful information about your current system status.
@@ -514,7 +528,7 @@
 
 config LEDS_TIMER
 	bool "Timer LED" if LEDS && (ARCH_NETWINDER || ARCH_EBSA285 || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_P720T)
-	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T
+	depends on ARCH_NETWINDER || ARCH_EBSA110 || ARCH_EBSA285 || ARCH_FTVPCI || ARCH_SHARK || ARCH_CO285 || ARCH_SA1100 || ARCH_LUBBOCK || ARCH_PXA_IDP || ARCH_INTEGRATOR || ARCH_CDB89712 || ARCH_P720T || ARCH_OMAP
 	default y if ARCH_EBSA110
 	help
 	  If you say Y here, one of the system LEDs (the green one on the
@@ -719,6 +733,18 @@
 	  in the kernel.  This is helpful if you are debugging code that
 	  executes before the console is initialized.
 
+config DEBUG_ICEDCC
+	bool "Kernel low-level debugging via EmbeddedICE DCC channel"
+	depends on DEBUG_LL
+	help
+	  Say Y here if you want the debug print routines to direct their
+	  output to the EmbeddedICE macrocell's DCC channel using
+	  co-processor 14. This is known to work on the ARM9 style ICE
+	  channel.
+
+	  It does include a timeout to ensure that the system does not
+	  totally freeze when there is nothing connected to read.
+
 config DEBUG_DC21285_PORT
 	bool "Kernel low-level debugging messages via footbridge serial port"
 	depends on DEBUG_LL && FOOTBRIDGE
@@ -735,6 +761,23 @@
 	  Say Y here if you want the debug print routines to direct their
 	  output to the second serial port on these devices.  Saying N will
 	  cause the debug messages to appear on the first serial port.
+
+config DEBUG_S3C2410_PORT
+	depends on DEBUG_LL && ARCH_S3C2410
+	bool "Kernel low-level debugging messages via S3C2410 UART"
+	help
+	  Say Y here if you want debug print routines to go to one of the
+	  S3C2410 internal UARTs. The chosen UART must have been configured
+	  before it is used.
+
+config DEBUG_S3C2410_UART
+	int
+	depends on DEBUG_LL && ARCH_S3C2410
+	default "0"
+	help
+	  Choice for UART for kernel low-level using S3C2410 UARTS,
+	  should be between zero and two. The port must have been
+	  initalised by the boot-loader before use.
 
 endmenu
 
diff -Nru a/arch/arm/Makefile b/arch/arm/Makefile
--- a/arch/arm/Makefile	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/Makefile	Thu Apr  8 14:54:32 2004
@@ -47,6 +47,7 @@
 tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM922T)	:=-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM925T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_ARM926T)	:=-mtune=arm9tdmi
 tune-$(CONFIG_CPU_SA110)	:=-mtune=strongarm110
 tune-$(CONFIG_CPU_SA1100)	:=-mtune=strongarm1100
@@ -91,6 +92,8 @@
 textaddr-$(CONFIG_ARCH_FORTUNET)   := 0xc0008000
  machine-$(CONFIG_ARCH_IOP3XX)	   := iop3xx
  machine-$(CONFIG_ARCH_ADIFCC)	   := adifcc
+ machine-$(CONFIG_ARCH_OMAP)	   := omap
+ machine-$(CONFIG_ARCH_S3C2410)	   := s3c2410
 
 TEXTADDR := $(textaddr-y)
 ifeq ($(incdir-y),)
diff -Nru a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
--- a/arch/arm/boot/Makefile	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/boot/Makefile	Thu Apr  8 14:54:32 2004
@@ -51,6 +51,13 @@
 params_phys-$(CONFIG_ARCH_IOP3XX)	:= 0xa0000100
    zreladdr-$(CONFIG_ARCH_ADIFCC)	:= 0xc0008000
 params_phys-$(CONFIG_ARCH_ADIFCC)	:= 0xc0000100
+   zreladdr-$(CONFIG_ARCH_OMAP)		:= 0x10008000
+params_phys-$(CONFIG_ARCH_OMAP)		:= 0x10000100
+initrd_phys-$(CONFIG_ARCH_OMAP)		:= 0x10800000
+
+   zreladdr-$(CONFIG_ARCH_S3C2410)      := 0x30008000
+params_phys-$(CONFIG_ARCH_S3C2410)      := 0x30000100
+
 
 ZRELADDR    := $(zreladdr-y)
 ZTEXTADDR   := $(ztextaddr-y)
diff -Nru a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
--- a/arch/arm/boot/compressed/Makefile	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/boot/compressed/Makefile	Thu Apr  8 14:54:32 2004
@@ -55,6 +55,10 @@
 OBJS		+= head-xscale.o
 endif
 
+ifeq ($(CONFIG_DEBUG_ICEDCC),y)
+OBJS            += ice-dcc.o
+endif
+
 SEDFLAGS	= s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/;s/BSS_START/$(ZBSSADDR)/
 
 targets       := vmlinux vmlinux.lds piggy piggy.gz piggy.o \
diff -Nru a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
--- a/arch/arm/boot/compressed/head.S	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/boot/compressed/head.S	Thu Apr  8 14:54:32 2004
@@ -25,6 +25,12 @@
 		.macro	writeb, rb
 		str	\rb, [r3, #0x160]
 		.endm
+#elif defined(CONFIG_DEBUG_ICEDCC)
+		.macro	loadsp, rb
+		.endm
+		.macro writeb, rb
+		mcr	p14, 0, \rb, c0, c1, 0
+		.endm
 #elif defined(CONFIG_FOOTBRIDGE)
 		.macro	loadsp,	rb
 		mov	\rb, #0x7c000000
diff -Nru a/arch/arm/boot/compressed/ice-dcc.S b/arch/arm/boot/compressed/ice-dcc.S
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/boot/compressed/ice-dcc.S	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,17 @@
+
+
+	.text
+
+	.global	icedcc_putc
+
+icedcc_putc:
+	mov	r2, #0x4000000
+1:
+	subs	r2, r2, #1
+	movlt	pc, r14
+	mrc	p14, 0, r1, c0, c0, 0
+	tst	r1, #2
+	bne	1b
+
+	mcr	p14, 0, r0, c1, c0, 0
+	mov	pc, r14
diff -Nru a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
--- a/arch/arm/boot/compressed/misc.c	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/boot/compressed/misc.c	Thu Apr  8 14:54:32 2004
@@ -27,6 +27,22 @@
 #define puts printf
 #endif
 
+#ifdef CONFIG_DEBUG_ICEDCC
+#define puts icedcc_puts
+#define putc icedcc_putc
+
+extern void idedcc_putc(int ch);
+
+static void
+icedcc_puts(const char *ptr)
+{
+	for (; *ptr != '\0'; ptr++) {
+		icedcc_putc(*ptr);
+	}
+}
+
+#endif
+
 #define __ptr_t void *
 
 /*
diff -Nru a/arch/arm/configs/bast_defconfig b/arch/arm/configs/bast_defconfig
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/configs/bast_defconfig	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,802 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_CLEAN_COMPILE is not set
+CONFIG_STANDALONE=y
+CONFIG_BROKEN=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_ADIFCC is not set
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SHARK is not set
+CONFIG_ARCH_S3C2410=y
+
+#
+# CLPS711X/EP721X Implementations
+#
+
+#
+# Epxa10db
+#
+
+#
+# Footbridge Implementations
+#
+
+#
+# IOP3xx Implementation Options
+#
+# CONFIG_ARCH_IOP310 is not set
+# CONFIG_ARCH_IOP321 is not set
+
+#
+# IOP3xx Chipset Features
+#
+
+#
+# Intel PXA250/210 Implementations
+#
+
+#
+# SA11x0 Implementations
+#
+
+#
+# S3C2410 Implementations
+#
+CONFIG_ARCH_BAST=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# General setup
+#
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+# CONFIG_HOTPLUG is not set
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+CONFIG_PARPORT_PC_CML1=y
+# CONFIG_PARPORT_SERIAL is not set
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC_SUPERIO=y
+# CONFIG_PARPORT_ARC is not set
+CONFIG_PARPORT_OTHER=y
+CONFIG_PARPORT_1284=y
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_PARTITIONS is not set
+# CONFIG_MTD_CONCAT is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_PARIDE is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+CONFIG_IPV6_SCTP__=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_SMC91X is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BT is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDETAPE=m
+CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_BLK_DEV_IDE_BAST=y
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN_BOOL is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_TSLIBDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PARKBD is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2410_CONSOLE=y
+# CONFIG_SERIAL_DZ is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_TIPAR is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_PHILIPSPAR is not set
+# CONFIG_SCx200_ACB is not set
+
+#
+# I2C Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=m
+# CONFIG_SENSORS_ADM1021 is not set
+CONFIG_SENSORS_EEPROM=m
+# CONFIG_SENSORS_IT87 is not set
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM85=m
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_GSS is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ACORN_PARTITION=y
+CONFIG_ACORN_PARTITION_CUMANA=y
+CONFIG_ACORN_PARTITION_EESOX=y
+CONFIG_ACORN_PARTITION_ICS=y
+CONFIG_ACORN_PARTITION_ADFS=y
+CONFIG_ACORN_PARTITION_POWERTEC=y
+CONFIG_ACORN_PARTITION_RISCIX=y
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_SOLARIS_X86_PARTITION=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_NEC98_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Graphics support
+#
+CONFIG_FB=y
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+
+#
+# Logo configuration
+#
+# CONFIG_LOGO is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+
+#
+# Console Switches
+#
+# CONFIG_SWITCHES is not set
+
+#
+# USB support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_PRINTK=y
+CONFIG_DEBUG_S3C2410_PORT=y
+CONFIG_DEBUG_S3C2410_UART=0
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_CRC32=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
diff -Nru a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/configs/s3c2410_defconfig	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,799 @@
+#
+# Automatically generated make config: don't edit
+#
+CONFIG_ARM=y
+CONFIG_MMU=y
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_CLEAN_COMPILE is not set
+CONFIG_STANDALONE=y
+CONFIG_BROKEN=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_IKCONFIG is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_ADIFCC is not set
+# CONFIG_ARCH_ANAKIN is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_CAMELOT is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP3XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SHARK is not set
+CONFIG_ARCH_S3C2410=y
+
+#
+# CLPS711X/EP721X Implementations
+#
+
+#
+# Epxa10db
+#
+
+#
+# Footbridge Implementations
+#
+
+#
+# IOP3xx Implementation Options
+#
+# CONFIG_ARCH_IOP310 is not set
+# CONFIG_ARCH_IOP321 is not set
+
+#
+# IOP3xx Chipset Features
+#
+
+#
+# Intel PXA250/210 Implementations
+#
+
+#
+# SA11x0 Implementations
+#
+
+#
+# S3C2410 Implementations
+#
+CONFIG_ARCH_BAST=y
+CONFIG_ARCH_H1940=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# General setup
+#
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+# CONFIG_HOTPLUG is not set
+
+#
+# At least one math emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_ARTHUR is not set
+CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Parallel port support
+#
+CONFIG_PARPORT=y
+CONFIG_PARPORT_PC=y
+CONFIG_PARPORT_PC_CML1=y
+# CONFIG_PARPORT_SERIAL is not set
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC_SUPERIO=y
+# CONFIG_PARPORT_ARC is not set
+CONFIG_PARPORT_OTHER=y
+CONFIG_PARPORT_1284=y
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_PARTITIONS is not set
+# CONFIG_MTD_CONCAT is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_EDB7312 is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_PARIDE is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+CONFIG_IPV6_SCTP__=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_SMC91X is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BT is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDETAPE=m
+CONFIG_BLK_DEV_IDEFLOPPY=m
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDE_TASKFILE_IO is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_BLK_DEV_IDE_BAST=y
+# CONFIG_BLK_DEV_IDEDMA is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# I2O device support
+#
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN_BOOL is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_TSLIBDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PARKBD is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_COMPUTONE is not set
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_DIGIEPCA is not set
+# CONFIG_DIGI is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2410_CONSOLE=y
+CONFIG_SERIAL_BAST_SIO=y
+# CONFIG_SERIAL_DZ is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+CONFIG_PRINTER=y
+# CONFIG_LP_CONSOLE is not set
+CONFIG_PPDEV=y
+# CONFIG_TIPAR is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_ALGOPCF is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_PHILIPSPAR is not set
+# CONFIG_SCx200_ACB is not set
+
+#
+# I2C Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=m
+# CONFIG_SENSORS_ADM1021 is not set
+CONFIG_SENSORS_EEPROM=m
+# CONFIG_SENSORS_IT87 is not set
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM85=m
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+
+#
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS_FS=y
+CONFIG_JFFS_FS_VERBOSE=0
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_GSS is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_SOLARIS_X86_PARTITION=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_NEC98_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Graphics support
+#
+CONFIG_FB=y
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+
+#
+# Logo configuration
+#
+# CONFIG_LOGO is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+
+#
+# Console Switches
+#
+# CONFIG_SWITCHES is not set
+
+#
+# USB support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_PRINTK=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_S3C2410_PORT=y
+CONFIG_DEBUG_S3C2410_UART=0
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_CRC32=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
diff -Nru a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
--- a/arch/arm/kernel/debug.S	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/kernel/debug.S	Thu Apr  8 14:54:32 2004
@@ -44,6 +44,34 @@
 		beq	1001b
 		.endm
 
+#elif defined(CONFIG_DEBUG_ICEDCC)
+		@@ debug using ARM EmbeddedICE DCC channel
+		.macro	addruart, rx
+		.endm
+
+		.macro	senduart, rd, rx
+		mcr	p14, 0, \rd, c1, c0, 0
+		.endm
+
+		.macro	busyuart, rd, rx
+1001:
+		mrc	p14, 0, \rx, c0, c0, 0
+		tst	\rx, #2
+		beq	1001b
+
+		.endm
+
+		.macro	waituart, rd, rx
+		mov	\rd, #0x2000000
+1001:
+		subs	\rd, \rd, #1
+		bmi	1002f
+		mrc	p14, 0, \rx, c0, c0, 0
+		tst	\rx, #2
+		bne	1001b
+1002:
+		.endm
+
 #elif defined(CONFIG_ARCH_EBSA110)
 		.macro	addruart,rx
 		mov	\rx, #0xf0000000
@@ -436,6 +464,92 @@
 		tst	\rd, #0x10
 		beq	1001b
 		.endm
+
+#elif defined(CONFIG_ARCH_OMAP)
+
+#include <asm/arch/serial.h>
+
+		.macro	addruart,rx
+		mov	\rx, #0xff000000
+		orr	\rx, \rx, #0x00fb0000
+		.endm
+
+		.macro	senduart,rd,rx
+		strb	\rd, [\rx]
+		.endm
+
+		.macro	busyuart,rd,rx
+1002:		ldrb	\rd, [\rx, #(0x5 << OMAP_SERIAL_REG_SHIFT)]
+		and	\rd, \rd, #0x60
+		teq	\rd, #0x60
+		bne	1002b
+		.endm
+
+		.macro	waituart,rd,rx
+1001:		ldrb	\rd, [\rx, #(0x6 << OMAP_SERIAL_REG_SHIFT)]
+		tst	\rd, #0x10
+		beq	1001b
+		.endm
+
+#elif defined(CONFIG_ARCH_S3C2410)
+#include <asm/arch/map.h>
+#include <asm/arch/regs-serial.h>
+
+		.macro addruart, rx
+		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1
+		ldreq	\rx, = S3C2410_PA_UART
+		ldrne	\rx, = S3C2410_VA_UART
+#if CONFIG_DEBUG_S3C2410_UART != 0
+		add	\rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
+#endif
+		.endm
+
+		.macro	senduart,rd,rx
+		str	\rd, [\rx, # S3C2410_UTXH ]
+		.endm
+
+		.macro	busyuart, rd, rx
+		ldr	\rd, [ \rx, # S3C2410_UFCON ]
+		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
+		beq	1001f				@
+		@ FIFO enabled...
+1003:
+		ldr	\rd, [ \rx, # S3C2410_UFSTAT ]
+		tst	\rd, #S3C2410_UFSTAT_TXFULL
+		bne	1003b
+		b	1002f
+
+1001:
+		@ busy waiting for non fifo
+		ldr	\rd, [ \rx, # S3C2410_UTRSTAT ]
+		tst	\rd, #S3C2410_UTRSTAT_TXFE
+		beq	1001b
+
+1002:		@ exit busyuart
+		.endm
+
+		.macro	waituart,rd,rx
+
+		ldr	\rd, [ \rx, # S3C2410_UFCON ]
+		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
+		beq	1001f				@
+		@ FIFO enabled...
+1003:
+		ldr	\rd, [ \rx, # S3C2410_UFSTAT ]
+		ands	\rd, \rd, #15<<S3C2410_UFSTAT_TXSHIFT
+		bne	1003b
+		b	1002f
+
+1001:
+		@ idle waiting for non fifo
+		ldr	\rd, [ \rx, # S3C2410_UTRSTAT ]
+		tst	\rd, #S3C2410_UTRSTAT_TXFE
+		beq	1001b
+
+1002:		@ exit busyuart
+		.endm
+
 #else
 #error Unknown architecture
 #endif
diff -Nru a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
--- a/arch/arm/kernel/ecard.c	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/kernel/ecard.c	Thu Apr  8 14:54:32 2004
@@ -908,6 +908,42 @@
 
 static DEVICE_ATTR(device, S_IRUGO, ecard_show_device, NULL);
 
+
+int ecard_request_resources(struct expansion_card *ec)
+{
+	int i, err = 0;
+
+	for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
+		if (ecard_resource_end(ec, i) &&
+		    !request_mem_region(ecard_resource_start(ec, i),
+					ecard_resource_len(ec, i),
+					ec->dev.driver->name)) {
+			err = -EBUSY;
+			break;
+		}
+	}
+
+	if (err) {
+		while (i--)
+			if (ecard_resource_end(ec, i))
+				release_mem_region(ecard_resource_start(ec, i),
+						   ecard_resource_len(ec, i));
+	}
+	return err;
+}
+EXPORT_SYMBOL(ecard_request_resources);
+
+void ecard_release_resources(struct expansion_card *ec)
+{
+	int i;
+
+	for (i = 0; i < ECARD_NUM_RESOURCES; i++)
+		if (ecard_resource_end(ec, i))
+			release_mem_region(ecard_resource_start(ec, i),
+					   ecard_resource_len(ec, i));
+}
+EXPORT_SYMBOL(ecard_release_resources);
+
 /*
  * Probe for an expansion card.
  *
diff -Nru a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
--- a/arch/arm/kernel/entry-armv.S	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/kernel/entry-armv.S	Thu Apr  8 14:54:32 2004
@@ -608,6 +608,156 @@
 		.macro	irq_prio_table
 		.endm
 
+#elif defined(CONFIG_ARCH_OMAP)
+
+		.macro	disable_fiq
+		.endm
+
+		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+		ldr	\base, =IO_ADDRESS(OMAP_IH1_BASE)
+		ldr	\irqnr, [\base, #IRQ_ITR]
+		ldr	\tmp, [\base, #IRQ_MIR]
+		mov	\irqstat, #0xffffffff
+		bic	\tmp, \irqstat, \tmp
+		tst	\irqnr, \tmp
+		beq	1510f
+
+		ldr	\irqnr, [\base, #IRQ_SIR_FIQ]
+		cmp	\irqnr, #0
+		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ]
+		cmpeq	\irqnr, #INT_IH2_IRQ
+		ldreq	\base, =IO_ADDRESS(OMAP_IH2_BASE)
+		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ]
+		addeqs	\irqnr, \irqnr, #32
+1510:
+		.endm
+
+		.macro	irq_prio_table
+		.endm
+
+#elif defined(CONFIG_ARCH_S3C2410)
+		/* S3C2410X IRQ Handler, <ben@simtec.co.uk> */
+
+		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+30000:
+		mov	\tmp, #S3C2410_VA_IRQ
+		ldr	\irqnr, [ \tmp, #0x14 ]		@ get irq no
+		teq	\irqnr, #4
+		teqne	\irqnr, #5
+		beq	1002f				@ external irq reg
+		teq	\irqnr, #16
+		beq	1003f				@ lcd controller
+
+		@ debug check to see if interrupt reported is the same
+		@ as the offset....
+
+		teq	\irqnr, #0
+		beq	20002f
+		ldr	\irqstat, [ \tmp, #0x10 ]	@ INTPND
+		mov	\irqstat, \irqstat, lsr \irqnr
+		tst	\irqstat, #1
+		bne	20002f
+
+#if 1
+		stmfd	r13!, { r0 - r4 , r14 }
+		ldr	r1,	[ \tmp, #0x14 ]		@ intoffset
+		ldr	r2,	[ \tmp, #0x10 ]		@ INTPND
+		ldr	r3,	[ \tmp, #0x00 ]		@ SRCPND
+		adr	r0, 20003f
+		bl	printk
+		b	20004f
+#endif
+20003:
+		.ascii	"<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
+		.byte	0
+		.align	4
+20004:
+		mov	r1, #1
+		mov	\tmp, #S3C2410_VA_IRQ
+		ldmfd	r13!, { r0 - r4 , r14 }
+
+		@ try working out interript number for ourselves
+		mov	\irqnr, #0
+		ldr	\irqstat, [ \tmp, #0x10 ]	@ INTPND
+10021:
+		movs	\irqstat, \irqstat, lsr#1
+		bcs	30000b		@ try and re-start the proccess
+		add	\irqnr, \irqnr, #1
+		cmp	\irqnr, #32
+		ble	10021b
+
+		@ found no interrupt, set Z flag and leave
+		movs	\irqnr, #0
+		b	1001f
+
+20005:
+20002:		@ exit
+		@ we base the s3c2410x interrupts at 16 and above to allow
+		@ isa peripherals to have their standard interrupts, also
+		@ ensure that Z flag is un-set on exit
+
+		@ note, we cannot be sure if we get IRQ_EINT0 (0) that
+		@ there is simply no interrupt pending, so in all other
+		@ cases we jump to say we have found something, otherwise
+		@ we check to see if the interrupt really is assrted
+		adds	\irqnr, \irqnr, #IRQ_EINT0
+		teq	\irqnr, #IRQ_EINT0
+		bne	1001f				@ exit
+		ldr	\irqstat, [ \tmp, #0x10 ]	@ INTPND
+		teq	\irqstat, #0
+		moveq	\irqnr, #0
+		b	1001f
+
+		@ we get here from no main or external interrupts pending
+1002:
+		add	\tmp, \tmp, #S3C2410_VA_GPIO - S3C2410_VA_IRQ
+		ldr	\irqstat, [ \tmp, # 0xa8 ]	@ EXTINTPEND
+		ldr	\irqnr, [ \tmp, # 0xa4 ]	@ EXTINTMASK
+
+		bic	\irqstat, \irqstat, \irqnr	@ clear masked irqs
+
+		mov	\irqnr, #IRQ_EINT4		@ start extint nos
+		mov	\irqstat, \irqstat, lsr#4	@ ignore bottom 4 bits
+10021:
+		movs	\irqstat, \irqstat, lsr#1
+		bcs	1004f
+		add	\irqnr, \irqnr, #1
+		cmp	\irqnr, #IRQ_EINT23
+		ble	10021b
+
+		@ found no interrupt, set Z flag and leave
+		movs	\irqnr, #0
+		b	1001f
+
+1003:
+		@ lcd interrupt has been asserted...
+		add	\tmp, \tmp, #S3C2410_VA_LCD - S3C2410_VA_IRQ
+		ldr	\irqstat, [ \tmp, # 0x54 ]	@ lcd int pending
+
+		tst	\irqstat, #2
+		movne	\irqnr, #IRQ_LCD_FRAME
+		tst	\irqstat, #1
+		movne	\irqnr, #IRQ_LCD_FIFO
+
+		@ fall through to exit with flags updated
+
+1004:		@ ensure Z flag clear in case our MOVS shifted out the last bit
+		teq	\irqnr, #0
+1001:
+		@ exit irq routine
+		.endm
+
+
+		/* currently don't need an disable_fiq macro */
+
+		.macro	disable_fiq
+		.endm
+
+		/* we don't have an irq priority table */
+		.macro irq_prio_table
+		.endm
+
 #else
 #error Unknown architecture
 #endif
diff -Nru a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
--- a/arch/arm/kernel/traps.c	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/kernel/traps.c	Thu Apr  8 14:54:32 2004
@@ -204,6 +204,7 @@
 		asm("mov%? %0, fp" : "=r" (fp));
 
 	c_backtrace(fp, 0x10);
+	barrier();
 }
 
 spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
diff -Nru a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
--- a/arch/arm/mach-footbridge/Kconfig	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/mach-footbridge/Kconfig	Thu Apr  8 14:54:32 2004
@@ -22,7 +22,7 @@
 	  There are no product plans beyond the current research
 	  prototypes at this time.  Information is available at:
 
-	  <http://crl.research.compaq.com/projects/personalserver/>
+	  <http://www.crl.hpl.hp.com/projects/personalserver/>
 
 	  If you have any questions or comments about the  Compaq Personal
 	  Server, send e-mail to skiff@crl.dec.com.
diff -Nru a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/Kconfig	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,113 @@
+
+menu "TI OMAP Implementations"
+
+choice
+	prompt "OMAP Core Type"
+	depends on ARCH_OMAP
+	default ARCH_OMAP1510
+
+config ARCH_OMAP1510
+	bool "OMAP-1510 Based System"
+	select CPU_ARM925T
+	select CPU_DCACHE_WRITETHROUGH
+
+config ARCH_OMAP1610
+	bool "OMAP-1610 Based System"
+	select CPU_ARM926T
+
+endchoice
+
+choice
+	prompt "OMAP Board Type"
+	depends on ARCH_OMAP
+	default MACH_OMAP_INNOVATOR
+
+config MACH_OMAP_INNOVATOR
+	bool "TI Innovator"
+	depends on ARCH_OMAP1510 || ARCH_OMAP1610
+	help
+          TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
+          have such a board.
+
+config MACH_OMAP_GENERIC
+	bool "Generic OMAP board"
+	depends on ARCH_OMAP1510 || ARCH_OMAP1610
+	help
+          Support for generic OMAP-1510 or 1610 board with no
+          FPGA. Can be used as template for porting Linux to
+          custom OMAP boards. Say Y here if you have a custom
+          board.
+
+endchoice
+
+comment "OMAP Feature Selections"
+
+config MACH_OMAP_H2
+	bool "TI H2 Support"
+	depends on ARCH_OMAP1610 && MACH_OMAP_INNOVATOR
+    	help
+	  TI OMAP 1610 H2 board support. Say Y here if you have such
+	  a board.
+
+config OMAP_MUX
+	bool "OMAP multiplexing support"
+        depends on ARCH_OMAP
+	default y
+        help
+          Pin multiplexing support for OMAP boards. If your bootloader
+          sets the multiplexing correctly, say N. Otherwise, or if unsure,
+          say Y.
+
+config OMAP_MUX_DEBUG
+	bool "Multiplexing debug output"
+        depends on OMAP_MUX
+        default n
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
+
+config OMAP_ARM_195MHZ
+	bool "OMAP ARM 195 MHz CPU"
+	depends on ARCH_OMAP730
+	help
+          Enable 195MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_192MHZ
+	bool "OMAP ARM 192 MHz CPU"
+	depends on ARCH_OMAP1610
+	help
+          Enable 192MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_182MHZ
+	bool "OMAP ARM 182 MHz CPU"
+	depends on ARCH_OMAP730
+	help
+          Enable 182MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_168MHZ
+	bool "OMAP ARM 168 MHz CPU"
+	depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730
+	help
+          Enable 168MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_120MHZ
+	bool "OMAP ARM 120 MHz CPU"
+	depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730
+	help
+          Enable 120MHz clock for OMAP CPU. If unsure, say N.
+
+config OMAP_ARM_60MHZ
+	bool "OMAP ARM 60 MHz CPU"
+	depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730
+        default y
+	help
+          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
+
+config OMAP_ARM_30MHZ
+	bool "OMAP ARM 30 MHz CPU"
+	depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730
+	help
+          Enable 30MHz clock for OMAP CPU. If unsure, say N.
+
+endmenu
diff -Nru a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/Makefile	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,36 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := common.o irq.o dma.o clocks.o mux.o bus.o gpio.o
+obj-m :=
+obj-n :=
+obj-  :=
+led-y := leds.o
+
+# OCPI interconnect support for 1610
+ifeq ($(CONFIG_ARCH_OMAP1610),y)
+obj-y += ocpi.o
+ifeq ($(CONFIG_OMAP_INNOVATOR),y)
+obj-y += innovator1610.o
+endif
+endif
+
+ifeq ($(CONFIG_ARCH_OMAP1510),y)
+ifeq ($(CONFIG_OMAP_INNOVATOR),y)
+obj-y += innovator1510.o fpga.o
+endif
+endif
+
+# Specific board support
+obj-$(CONFIG_MACH_OMAP_GENERIC) += omap-generic.o
+obj-$(CONFIG_MACH_OMAP_PERSEUS2) += omap-perseus2.o
+
+# LEDs support
+led-$(CONFIG_OMAP_INNOVATOR) += leds-innovator.o
+led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-perseus2.o
+obj-$(CONFIG_LEDS) += $(led-y)
+
+# kgdb support
+obj-$(CONFIG_KGDB_SERIAL)	+= kgdb-serial.o
diff -Nru a/arch/arm/mach-omap/bus.c b/arch/arm/mach-omap/bus.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/bus.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,280 @@
+/*
+ * linux/arch/arm/mach-omap/bus.c
+ *
+ * Virtual bus for OMAP. Allows better power management, such as managing
+ * shared clocks, and mapping of bus addresses to Local Bus addresses.
+ *
+ * See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for
+ * examples on how to register drivers to this bus.
+ *
+ * Copyright (C) 2003 - 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ * Portions of code based on sa1111.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/bus.h>
+
+static int omap_bus_match(struct device *_dev, struct device_driver *_drv);
+static int omap_bus_suspend(struct device *dev, u32 state);
+static int omap_bus_resume(struct device *dev);
+
+/*
+ * OMAP bus definitions
+ *
+ * NOTE: Most devices should use TIPB. LBUS does automatic address mapping
+ *	 to Local Bus addresses, and should only be used for Local Bus devices.
+ *	 We may add new buses later on for power management reasons. Basically
+ *	 we want to be able to turn off any bus if it's not used by device
+ *	 drivers.
+ */
+static struct device omap_bus_devices[OMAP_NR_BUSES] = {
+	{
+		.bus_id		= OMAP_BUS_NAME_TIPB
+	}, {
+		.bus_id		= OMAP_BUS_NAME_LBUS
+	},
+};
+
+static struct bus_type omap_bus_types[OMAP_NR_BUSES] = {
+	{
+		.name		= OMAP_BUS_NAME_TIPB,
+		.match		= omap_bus_match,
+		.suspend	= omap_bus_suspend,
+		.resume		= omap_bus_resume,
+	}, {
+		.name		= OMAP_BUS_NAME_LBUS,	/* Local bus on 1510 */
+		.match		= omap_bus_match,
+		.suspend	= omap_bus_suspend,
+		.resume		= omap_bus_resume,
+	},
+};
+
+#ifdef CONFIG_ARCH_OMAP1510
+/*
+ * NOTE: This code _should_ go somewhere else. But let's wait for the
+ *	 dma-mapping code to settle down first.
+ */
+
+/*
+ * Test for Local Bus device in order to do address translation between
+ * dma_handle and Local Bus address.
+ */
+inline int dmadev_uses_omap_lbus(struct device * dev)
+{
+	return dev->bus == &omap_bus_types[OMAP_BUS_LBUS] ? 1 : 0;
+}
+
+/*
+ * Translate bus address to Local Bus address for dma-mapping
+ */
+inline int dmadev_to_lbus(dma_addr_t addr)
+{
+	return bus_to_lbus(addr);
+}
+
+/*
+ * Translate Local Bus address to bus address for dma-mapping
+ */
+inline int lbus_to_dmadev(dma_addr_t addr)
+{
+	return lbus_to_bus(addr);
+}
+#endif
+
+static int omap_bus_match(struct device *dev, struct device_driver *drv)
+{
+	struct omap_dev *omapdev = OMAP_DEV(dev);
+	struct omap_driver *omapdrv = OMAP_DRV(drv);
+
+	return omapdev->devid == omapdrv->devid;
+}
+
+static int omap_bus_suspend(struct device *dev, u32 state)
+{
+	struct omap_dev *omapdev = OMAP_DEV(dev);
+	struct omap_driver *omapdrv = OMAP_DRV(dev->driver);
+	int ret = 0;
+
+	if (omapdrv && omapdrv->suspend)
+		ret = omapdrv->suspend(omapdev, state);
+	return ret;
+}
+
+static int omap_bus_resume(struct device *dev)
+{
+	struct omap_dev *omapdev = OMAP_DEV(dev);
+	struct omap_driver *omapdrv = OMAP_DRV(dev->driver);
+	int ret = 0;
+
+	if (omapdrv && omapdrv->resume)
+		ret = omapdrv->resume(omapdev);
+	return ret;
+}
+
+static int omap_device_probe(struct device *dev)
+{
+	struct omap_dev *omapdev = OMAP_DEV(dev);
+	struct omap_driver *omapdrv = OMAP_DRV(dev->driver);
+	int ret = -ENODEV;
+
+	if (omapdrv && omapdrv->probe)
+		ret = omapdrv->probe(omapdev);
+
+	return ret;
+}
+
+static int omap_device_remove(struct device *dev)
+{
+	struct omap_dev *omapdev = OMAP_DEV(dev);
+	struct omap_driver *omapdrv = OMAP_DRV(dev->driver);
+	int ret = 0;
+
+	if (omapdrv && omapdrv->remove)
+		ret = omapdrv->remove(omapdev);
+	return ret;
+}
+
+int omap_device_register(struct omap_dev *odev)
+{
+	if (!odev)
+		return -EINVAL;
+
+	if (odev->busid < 0 || odev->busid >= OMAP_NR_BUSES) {
+		printk(KERN_ERR "%s: busid invalid: %s: bus: %i\n",
+		       __FUNCTION__, odev->name, odev->busid);
+		return -EINVAL;
+	}
+
+	odev->dev.parent = &omap_bus_devices[odev->busid];
+	odev->dev.bus = &omap_bus_types[odev->busid];
+
+	/* This is needed for USB OHCI to work */
+	if (odev->dma_mask)
+		odev->dev.dma_mask = odev->dma_mask;
+
+	snprintf(odev->dev.bus_id, BUS_ID_SIZE, "%s%u",
+		 odev->name, odev->devid);
+
+	printk("Registering OMAP device '%s'. Parent at %s\n",
+		 odev->dev.bus_id, odev->dev.parent->bus_id);
+
+	return device_register(&odev->dev);
+}
+
+void omap_device_unregister(struct omap_dev *odev)
+{
+	if (odev)
+		device_unregister(&odev->dev);
+}
+
+int omap_driver_register(struct omap_driver *driver)
+{
+	int ret;
+
+	if (driver->busid < 0 || driver->busid >= OMAP_NR_BUSES) {
+		printk(KERN_ERR "%s: busid invalid: bus: %i device: %i\n",
+		       __FUNCTION__, driver->busid, driver->devid);
+		return -EINVAL;
+	}
+
+	driver->drv.probe = omap_device_probe;
+	driver->drv.remove = omap_device_remove;
+	driver->drv.bus = &omap_bus_types[driver->busid];
+
+	/*
+	 * driver_register calls bus_add_driver
+	 */
+	ret = driver_register(&driver->drv);
+
+	return ret;
+}
+
+void omap_driver_unregister(struct omap_driver *driver)
+{
+	driver_unregister(&driver->drv);
+}
+
+static int __init omap_bus_init(void)
+{
+	int i, ret;
+
+	/* Initialize all OMAP virtual buses */
+	for (i = 0; i < OMAP_NR_BUSES; i++) {
+		ret = device_register(&omap_bus_devices[i]);
+		if (ret != 0) {
+			printk(KERN_ERR "Unable to register bus device %s\n",
+			       omap_bus_devices[i].bus_id);
+			continue;
+		}
+		ret = bus_register(&omap_bus_types[i]);
+		if (ret != 0) {
+			printk(KERN_ERR "Unable to register bus %s\n",
+			       omap_bus_types[i].name);
+			device_unregister(&omap_bus_devices[i]);
+		}
+	}
+	printk("OMAP virtual buses initialized\n");
+
+	return ret;
+}
+
+static void __exit omap_bus_exit(void)
+{
+	int i;
+
+	/* Unregister all OMAP virtual buses */
+	for (i = 0; i < OMAP_NR_BUSES; i++) {
+		bus_unregister(&omap_bus_types[i]);
+		device_unregister(&omap_bus_devices[i]);
+	}
+}
+
+module_init(omap_bus_init);
+module_exit(omap_bus_exit);
+
+MODULE_DESCRIPTION("Virtual bus for OMAP");
+MODULE_LICENSE("GPL");
+
+EXPORT_SYMBOL(omap_bus_types);
+EXPORT_SYMBOL(omap_driver_register);
+EXPORT_SYMBOL(omap_driver_unregister);
+EXPORT_SYMBOL(omap_device_register);
+EXPORT_SYMBOL(omap_device_unregister);
+
+#ifdef CONFIG_ARCH_OMAP1510
+EXPORT_SYMBOL(dmadev_uses_omap_lbus);
+EXPORT_SYMBOL(dmadev_to_lbus);
+EXPORT_SYMBOL(lbus_to_dmadev);
+#endif
diff -Nru a/arch/arm/mach-omap/clocks.c b/arch/arm/mach-omap/clocks.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/clocks.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,676 @@
+/*
+ * Clock interface for OMAP
+ *
+ * Copyright (C) 2001 RidgeRun, Inc
+ * Written by Gordon McNutt <gmcnutt@ridgerun.com>
+ * Updated 2004 for Linux 2.6 by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clocks.h>
+
+/* Input clock in MHz */
+static unsigned int source_clock = 12;
+
+/*
+ * We use one spinlock for all clock registers for now. We may want to
+ * change this to be clock register specific later on. Before we can do
+ * that, we need to map out the shared clock registers.
+ */
+static spinlock_t clock_lock = SPIN_LOCK_UNLOCKED;
+
+typedef struct {
+	char		*name;
+	__u8		flags;
+	ck_t		parent;
+	volatile __u16	*rate_reg;	/* Clock rate register */
+	volatile __u16	*enbl_reg;	/* Enable register */
+	volatile __u16	*idle_reg;	/* Idle register */
+	volatile __u16	*slct_reg;	/* Select register */
+	__s8		rate_shift;	/* Clock rate bit shift */
+	__s8		enbl_shift;	/* Clock enable bit shift */
+	__s8		idle_shift;	/* Clock idle bit shift */
+	__s8		slct_shift;	/* Clock select bit shift */
+} ck_info_t;
+
+#define CK_NAME(ck)		ck_info_table[ck].name
+#define CK_FLAGS(ck)		ck_info_table[ck].flags
+#define CK_PARENT(ck)		ck_info_table[ck].parent
+#define CK_RATE_REG(ck)		ck_info_table[ck].rate_reg
+#define CK_ENABLE_REG(ck)	ck_info_table[ck].enbl_reg
+#define CK_IDLE_REG(ck)		ck_info_table[ck].idle_reg
+#define CK_SELECT_REG(ck)	ck_info_table[ck].slct_reg
+#define CK_RATE_SHIFT(ck)	ck_info_table[ck].rate_shift
+#define CK_ENABLE_SHIFT(ck)	ck_info_table[ck].enbl_shift
+#define CK_IDLE_SHIFT(ck)	ck_info_table[ck].idle_shift
+#define CK_SELECT_SHIFT(ck)	ck_info_table[ck].slct_shift
+#define CK_CAN_CHANGE_RATE(cl)	(CK_FLAGS(ck) & CK_RATEF)
+#define CK_CAN_DISABLE(cl)	(CK_FLAGS(ck) & CK_ENABLEF)
+#define CK_CAN_IDLE(cl)		(CK_FLAGS(ck) & CK_IDLEF)
+#define CK_CAN_SWITCH(cl)	(CK_FLAGS(ck) & CK_SELECTF)
+
+static ck_info_t ck_info_table[] = {
+	{
+		.name		= "clkin",
+		.flags		= 0,
+		.parent		= OMAP_CLKIN,
+	}, {
+		.name		= "ck_gen1",
+		.flags		= CK_RATEF | CK_IDLEF,
+		.rate_reg	= CK_DPLL1,
+		.idle_reg	= ARM_IDLECT1,
+		.idle_shift	= IDLDPLL_ARM,
+		.parent		= OMAP_CLKIN,
+	}, {
+		.name		= "ck_gen2",
+		.flags		= 0,
+		.parent		= OMAP_CK_GEN1,
+	}, {
+		.name		= "ck_gen3",
+		.flags		= 0,
+		.parent		= OMAP_CK_GEN1,
+	}, {
+		.name		= "tc_ck",
+		.flags		= CK_RATEF | CK_IDLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[TCDIV(9:8)] */
+		.idle_reg	= ARM_IDLECT1,
+		.rate_shift	= TCDIV,
+		.idle_shift	= IDLIF_ARM
+	}, {
+		.name		= "arm_ck",
+		.flags		= CK_IDLEF | CK_RATEF,
+		.parent		= OMAP_CK_GEN1,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[ARMDIV(5:4)] */
+		.idle_reg	= ARM_IDLECT1,
+		.rate_shift	= ARMDIV,
+		.idle_shift	= SETARM_IDLE,
+	}, {
+		.name		= "mpuper_ck",
+		.flags		= CK_RATEF | CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN1,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[PERDIV(1:0)] */
+		.enbl_reg	= ARM_IDLECT2,
+		.idle_reg	= ARM_IDLECT1,
+		.rate_shift	= PERDIV,
+		.enbl_shift	= EN_PERCK,
+		.idle_shift	= IDLPER_ARM
+	}, {
+		.name		= "arm_gpio_ck",
+		.flags		= CK_ENABLEF,
+		.parent		= OMAP_CK_GEN1,
+		.enbl_reg	= ARM_IDLECT2,
+		.enbl_shift	= EN_GPIOCK
+	}, {
+		.name		= "mpuxor_ck",
+		.flags		= CK_ENABLEF | CK_IDLEF,
+		.parent		= OMAP_CLKIN,
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.idle_shift	= IDLXORP_ARM,
+		.enbl_shift	= EN_XORPCK
+	}, {
+		.name		= "mputim_ck",
+		.flags		= CK_IDLEF | CK_ENABLEF | CK_SELECTF,
+		.parent		= OMAP_CLKIN,
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.slct_reg	= ARM_CKCTL,
+		.idle_shift	= IDLTIM_ARM,
+		.enbl_shift	= EN_TIMCK,
+		.slct_shift	= ARM_TIMXO
+	}, {
+		.name		= "mpuwd_ck",
+		.flags		= CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CLKIN,
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.idle_shift	= IDLWDT_ARM,
+		.enbl_shift	= EN_WDTCK,
+	}, {
+		.name		= "dsp_ck",
+		.flags		= CK_RATEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN2,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[DSPDIV(7:6)] */
+		.enbl_reg	= ARM_CKCTL,
+		.rate_shift	= DSPDIV,
+		.enbl_shift	= EN_DSPCK,
+	}, {
+		.name		= "dspmmu_ck",
+		.flags		= CK_RATEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN2,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[DSPMMUDIV(11:10)] */
+		.enbl_reg	= ARM_CKCTL,
+		.rate_shift	= DSPMMUDIV,
+		.enbl_shift	= EN_DSPCK,
+	}, {
+		.name		= "dma_ck",
+		.flags		= CK_RATEF | CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[TCDIV(9:8)] */
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.rate_shift	= TCDIV,
+		.idle_shift	= IDLIF_ARM,
+		.enbl_shift	= DMACK_REQ
+	}, {
+		.name		= "api_ck",
+		.flags		= CK_RATEF | CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[TCDIV(9:8)] */
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.rate_shift	= TCDIV,
+		.idle_shift	= IDLAPI_ARM,
+		.enbl_shift	= EN_APICK,
+	}, {
+		.name		= "hsab_ck",
+		.flags		= CK_RATEF | CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[TCDIV(9:8)] */
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.rate_shift	= TCDIV,
+		.idle_shift	= IDLHSAB_ARM,
+		.enbl_shift	= EN_HSABCK,
+	}, {
+		.name		= "lbfree_ck",
+		.flags		= CK_RATEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[TCDIV(9:8)] */
+		.enbl_reg	= ARM_IDLECT2,
+		.rate_shift	= TCDIV,
+		.enbl_shift	= EN_LBFREECK,
+	}, {
+		.name		= "lb_ck",
+		.flags		= CK_RATEF | CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[TCDIV(9:8)] */
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.rate_shift	= TCDIV,
+		.idle_shift	= IDLLB_ARM,
+		.enbl_shift	= EN_LBCK,
+	}, {
+		.name		= "lcd_ck",
+		.flags		= CK_RATEF | CK_IDLEF | CK_ENABLEF,
+		.parent		= OMAP_CK_GEN3,
+		.rate_reg	= ARM_CKCTL,	/* ARM_CKCTL[LCDDIV(3:2)] */
+		.idle_reg	= ARM_IDLECT1,
+		.enbl_reg	= ARM_IDLECT2,
+		.rate_shift	= LCDDIV,
+		.idle_shift	= IDLLCD_ARM,
+		.enbl_shift	= EN_LCDCK,
+	},
+};
+
+/*****************************************************************************/
+
+#define CK_IN_RANGE(ck)		(!((ck < OMAP_CK_MIN) || (ck > OMAP_CK_MAX)))
+
+int ck_auto_unclock = 1;
+int ck_debug = 0;
+
+#define CK_MAX_PLL_FREQ		OMAP_CK_MAX_RATE
+static __u8 ck_valid_table[CK_MAX_PLL_FREQ / 8 + 1];
+static __u8 ck_lookup_table[CK_MAX_PLL_FREQ];
+
+int
+ck_set_input(ck_t ck, ck_t input)
+{
+	int ret = 0, shift;
+	volatile __u16 *reg;
+	unsigned long flags;
+
+	if (!CK_IN_RANGE(ck) || !CK_CAN_SWITCH(ck)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	reg = CK_SELECT_REG(ck);
+	shift = CK_SELECT_SHIFT(ck);
+
+	spin_lock_irqsave(&clock_lock, flags);
+	if (input == OMAP_CLKIN) {
+		*((volatile __u16 *) reg) &= ~(1 << shift);
+		goto exit;
+	} else if (input == CK_PARENT(ck)) {
+		*((volatile __u16 *) reg) |= (1 << shift);
+		goto exit;
+	}
+
+	ret = -EINVAL;
+ exit:
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+
+int
+ck_get_input(ck_t ck, ck_t * input)
+{
+	int ret = -EINVAL;
+	unsigned long flags;
+
+	if (!CK_IN_RANGE(ck))
+		goto exit;
+
+	ret = 0;
+
+	spin_lock_irqsave(&clock_lock, flags);
+	if (CK_CAN_SWITCH(ck)) {
+		int shift;
+		volatile __u16 *reg;
+
+		reg = CK_SELECT_REG(ck);
+		shift = CK_SELECT_SHIFT(ck);
+		if (*reg & (1 << shift)) {
+			*input = CK_PARENT(ck);
+			goto exit;
+		}
+	}
+
+	*input = OMAP_CLKIN;
+
+ exit:
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+
+static int
+__ck_set_pll_rate(ck_t ck, int rate)
+{
+	volatile __u16 *pll;
+	unsigned long flags;
+
+	if ((rate < 0) || (rate > CK_MAX_PLL_FREQ))
+		return -EINVAL;
+
+	/* Scan downward for the closest matching frequency */
+	while (rate && !test_bit(rate, (unsigned long *)&ck_valid_table))
+		rate--;
+
+	if (!rate) {
+		printk(KERN_ERR "%s: couldn't find a matching rate\n",
+			__FUNCTION__);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&clock_lock, flags);
+	pll = (volatile __u16 *) CK_RATE_REG(ck);
+
+	/* Clear the rate bits */
+	*pll &= ~(0x1f << 5);
+
+	/* Set the rate bits */
+	*pll |= (ck_lookup_table[rate - 1] << 5);
+	spin_unlock_irqrestore(&clock_lock, flags);
+
+	return 0;
+}
+
+static int
+__ck_set_clkm_rate(ck_t ck, int rate)
+{
+	int shift, prate, div, ret;
+	volatile __u16 *reg;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	/*
+	 * We can only set this clock's value to a fraction of its
+	 * parent's value. The interface says I'll round down when necessary.
+	 * So first let's get the parent's current rate.
+	 */
+	prate = ck_get_rate(CK_PARENT(ck));
+
+	/*
+	 * Let's just start with the highest fraction and keep searching
+	 * down through available rates until we find one less than or equal
+	 * to the desired rate.
+	 */
+	for (div = 0; div < 4; div++) {
+		if (prate <= rate)
+			break;
+		prate = prate / 2;
+	}
+
+	/*
+	 * Oops. Looks like the caller wants a rate lower than we can support.
+	 */
+	if (div == 5) {
+		printk(KERN_ERR "%s: %d is too low\n",
+			__FUNCTION__, rate);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	/*
+	 * One more detail: if this clock supports more than one parent, then
+	 * we're going to automatically switch over to the parent which runs
+	 * through the divisor. For omap this is not ambiguous because for all
+	 * such clocks one choice is always OMAP_CLKIN (which doesn't run
+	 * through the divisor) and the other is whatever I encoded as
+	 * CK_PARENT. Note that I wait until we get this far because I don't
+	 * want to switch the input until we're sure this is going to work.
+	 */
+	if (CK_CAN_SWITCH(ck))
+		if ((ret = ck_set_input(ck, CK_PARENT(ck))) < 0) {
+			BUG();
+			goto exit;
+		}
+
+	/*
+	 * At last, we can set the divisor. Clear the old rate bits and
+	 * set the new ones.
+	 */
+	reg = (volatile __u16 *) CK_RATE_REG(ck);
+	shift = CK_RATE_SHIFT(ck);
+	*reg &= ~(3 << shift);
+	*reg |= (div << shift);
+
+	/* And return the new (actual, after rounding down) rate. */
+	ret = prate;
+
+ exit:
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+
+int
+ck_set_rate(ck_t ck, int rate)
+{
+	int ret = -EINVAL;
+
+	if (!CK_IN_RANGE(ck) || !CK_CAN_CHANGE_RATE(ck))
+		goto exit;
+
+	switch (ck) {
+
+	default:
+		ret = __ck_set_clkm_rate(ck, rate);
+		break;
+
+	case OMAP_CK_GEN1:
+		ret = __ck_set_pll_rate(ck, rate);
+		break;
+
+	};
+
+ exit:
+	return ret;
+}
+
+static int
+__ck_get_pll_rate(ck_t ck)
+{
+	int m, d;
+
+	__u16 pll = *((volatile __u16 *) CK_RATE_REG(ck));
+
+	m = (pll & (0x1f << 7)) >> 7;
+	m = m ? m : 1;
+	d = (pll & (3 << 5)) >> 5;
+	d++;
+
+	return ((source_clock * m) / d);
+}
+
+static int
+__ck_get_clkm_rate(ck_t ck)
+{
+	static int bits2div[] = { 1, 2, 4, 8 };
+	int in, bits, reg, shift;
+
+	reg = *(CK_RATE_REG(ck));
+	shift = CK_RATE_SHIFT(ck);
+
+	in = ck_get_rate(CK_PARENT(ck));
+	bits = (reg & (3 << shift)) >> shift;
+
+	return (in / bits2div[bits]);
+}
+
+int
+ck_get_rate(ck_t ck)
+{
+	int ret = 0;
+	ck_t parent;
+
+	if (!CK_IN_RANGE(ck)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	switch (ck) {
+
+	case OMAP_CK_GEN1:
+		ret = __ck_get_pll_rate(ck);
+		break;
+
+	case OMAP_CLKIN:
+		ret = source_clock;
+		break;
+
+	case OMAP_MPUXOR_CK:
+	case OMAP_CK_GEN2:
+	case OMAP_CK_GEN3:
+	case OMAP_ARM_GPIO_CK:
+		ret = ck_get_rate(CK_PARENT(ck));
+		break;
+
+	case OMAP_ARM_CK:
+	case OMAP_MPUPER_CK:
+	case OMAP_DSP_CK:
+	case OMAP_DSPMMU_CK:
+	case OMAP_LCD_CK:
+	case OMAP_TC_CK:
+	case OMAP_DMA_CK:
+	case OMAP_API_CK:
+	case OMAP_HSAB_CK:
+	case OMAP_LBFREE_CK:
+	case OMAP_LB_CK:
+		ret = __ck_get_clkm_rate(ck);
+		break;
+
+	case OMAP_MPUTIM_CK:
+		ck_get_input(ck, &parent);
+		ret = ck_get_rate(parent);
+		break;
+
+	case OMAP_MPUWD_CK:
+		/* Note that this evaluates to zero if source_clock is 12MHz. */
+		ret = source_clock / 14;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+ exit:
+	return ret;
+}
+
+int
+ck_enable(ck_t ck)
+{
+	volatile __u16 *reg;
+	int ret = -EINVAL, shift;
+	unsigned long flags;
+
+	if (!CK_IN_RANGE(ck))
+		goto exit;
+
+	if (ck_debug)
+		printk(KERN_DEBUG "%s: %s\n", __FUNCTION__, CK_NAME(ck));
+
+	ret = 0;
+
+	if (!CK_CAN_DISABLE(ck))
+		/* Then it must be on... */
+		goto exit;
+
+	spin_lock_irqsave(&clock_lock, flags);
+	reg = CK_ENABLE_REG(ck);
+	shift = CK_ENABLE_SHIFT(ck);
+	*reg |= (1 << shift);
+	spin_unlock_irqrestore(&clock_lock, flags);
+
+ exit:
+	return ret;
+}
+
+int
+ck_disable(ck_t ck)
+{
+	volatile __u16 *reg;
+	int ret = -EINVAL, shift;
+	unsigned long flags;
+
+	if (!CK_IN_RANGE(ck))
+		goto exit;
+
+	if (ck_debug)
+		printk(KERN_DEBUG "%s: %s\n", __FUNCTION__, CK_NAME(ck));
+
+	if (!CK_CAN_DISABLE(ck))
+		goto exit;
+
+	ret = 0;
+
+	if (ck == OMAP_CLKIN)
+		return -EINVAL;
+
+	spin_lock_irqsave(&clock_lock, flags);
+	reg = CK_ENABLE_REG(ck);
+	shift = CK_ENABLE_SHIFT(ck);
+	*reg &= ~(1 << shift);
+	spin_unlock_irqrestore(&clock_lock, flags);
+
+ exit:
+	return ret;
+}
+
+int ck_valid_rate(int rate)
+{
+	return test_bit(rate, (unsigned long *)&ck_valid_table);
+}
+
+static void
+__ck_make_lookup_table(void)
+{
+	__u8 m, d;
+
+	memset(ck_valid_table, 0, sizeof (ck_valid_table));
+
+	for (m = 1; m < 32; m++)
+		for (d = 1; d < 5; d++) {
+
+			int rate = ((source_clock * m) / (d));
+
+			if (rate > CK_MAX_PLL_FREQ)
+				continue;
+			if (test_bit(rate, (unsigned long *)&ck_valid_table))
+				continue;
+			set_bit(rate, (unsigned long *)&ck_valid_table);
+			ck_lookup_table[rate - 1] = (m << 2) | (d - 1);
+		}
+}
+
+int __init
+init_ck(void)
+{
+	__ck_make_lookup_table();
+
+	/* We want to be in syncronous scalable mode */
+	*ARM_SYSST = 0x1000;
+#if defined(CONFIG_OMAP_ARM_30MHZ)
+	*ARM_CKCTL = 0x1555;
+	*DPLL_CTL_REG = 0x2290;
+#elif defined(CONFIG_OMAP_ARM_60MHZ)
+	*ARM_CKCTL = 0x1005;
+	*DPLL_CTL_REG = 0x2290;
+#elif defined(CONFIG_OMAP_ARM_96MHZ)
+	*ARM_CKCTL = 0x1005;
+	*DPLL_CTL_REG = 0x2410;
+#elif defined(CONFIG_OMAP_ARM_120MHZ)
+	*ARM_CKCTL = 0x110a;
+	*DPLL_CTL_REG = 0x2510;
+#elif defined(CONFIG_OMAP_ARM_168MHZ)
+	*ARM_CKCTL = 0x110f;
+	*DPLL_CTL_REG = 0x2710;
+#elif defined(CONFIG_OMAP_ARM_182MHZ) && defined(CONFIG_ARCH_OMAP730)
+	*ARM_CKCTL = 0x250E;
+	*DPLL_CTL_REG = 0x2713;
+#elif defined(CONFIG_OMAP_ARM_192MHZ) && defined(CONFIG_ARCH_OMAP1610)
+	*ARM_CKCTL = 0x110f;
+	if (crystal_type == 2) {
+		source_clock = 13;	/* MHz */
+		*DPLL_CTL_REG = 0x2510;
+	} else
+		*DPLL_CTL_REG = 0x2810;
+#elif defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730)
+	*ARM_CKCTL = 0x250E;
+	*DPLL_CTL_REG = 0x2793;
+#else
+#error "OMAP MHZ not set, please run make xconfig"
+#endif
+
+	/* Turn off some other junk the bootloader might have turned on */
+	*ARM_CKCTL &= 0x0fff;	/* Turn off DSP, ARM_INTHCK, ARM_TIMXO */
+	*ARM_RSTCT1 = 0;	/* Put DSP/MPUI into reset until needed */
+	*ARM_RSTCT2 = 1;
+	*ARM_IDLECT1 = 0x400;
+
+	/*
+	 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
+	 * of the ARM_IDLECT2 register must be set to zero. The power-on
+	 * default value of this bit is one.
+	 */
+	*ARM_IDLECT2 = 0x0000;	/* Turn LCD clock off also */
+
+	/*
+	 * Only enable those clocks we will need, let the drivers
+	 * enable other clocks as necessary
+	 */
+	ck_enable(OMAP_MPUPER_CK);
+	ck_enable(OMAP_ARM_GPIO_CK);
+	ck_enable(OMAP_MPUXOR_CK);
+	//ck_set_rate(OMAP_MPUTIM_CK, OMAP_CLKIN);
+	ck_enable(OMAP_MPUTIM_CK);
+	start_mputimer1(0xffffffff);
+
+	return 0;
+}
+
+
+EXPORT_SYMBOL(ck_get_rate);
+EXPORT_SYMBOL(ck_set_rate);
+EXPORT_SYMBOL(ck_enable);
+EXPORT_SYMBOL(ck_disable);
diff -Nru a/arch/arm/mach-omap/common.c b/arch/arm/mach-omap/common.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/common.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,69 @@
+/*
+ * linux/arch/arm/mach-omap/common.c
+ *
+ * Code common to all OMAP machines.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/hardware.h>
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/arch/clocks.h>
+#include <asm/io.h>
+
+#include "common.h"
+
+/*
+ * Common OMAP I/O mapping
+ *
+ * The machine specific code may provide the extra mapping besides the
+ * default mapping provided here.
+ */
+
+static struct map_desc standard_io_desc[] __initdata = {
+ { IO_BASE,          IO_START,          IO_SIZE,          MT_DEVICE },
+ { OMAP_DSP_BASE,    OMAP_DSP_START,    OMAP_DSP_SIZE,    MT_DEVICE },
+ { OMAP_DSPREG_BASE, OMAP_DSPREG_START, OMAP_DSPREG_SIZE, MT_DEVICE },
+ { OMAP_SRAM_BASE,   OMAP_SRAM_START,   OMAP_SRAM_SIZE,   MT_DEVICE }
+};
+
+static int initialized = 0;
+
+static void __init _omap_map_io(void)
+{
+	initialized = 1;
+
+	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+
+	/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
+	 * on a Posted Write in the TIPB Bridge".
+	 */
+	__raw_writew(0x0, MPU_PUBLIC_TIPB_CNTL_REG);
+	__raw_writew(0x0, MPU_PRIVATE_TIPB_CNTL_REG);
+
+	/* Must init clocks early to assure that timer interrupt works
+	 */
+	init_ck();
+}
+
+/*
+ * This should only get called from board specific init
+ */
+void omap_map_io(void)
+{
+	if (!initialized)
+		_omap_map_io();
+}
+
+EXPORT_SYMBOL(omap_map_io);
+
diff -Nru a/arch/arm/mach-omap/common.h b/arch/arm/mach-omap/common.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/common.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,6 @@
+/*
+ * linux/arch/arm/mach-omap/common.h
+ */
+
+extern void omap_map_io(void);
+
diff -Nru a/arch/arm/mach-omap/dma.c b/arch/arm/mach-omap/dma.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/dma.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,560 @@
+/*
+ * linux/arch/arm/omap/dma.c
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ * Author: Juha Yrj�l� <juha.yrjola@nokia.com>
+ *
+ * Support functions for the OMAP internal DMA channels.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+
+#define OMAP_DMA_ACTIVE		0x01
+
+#define OMAP_DMA_CCR_EN		(1 << 7)
+
+#define OMAP_FUNC_MUX_ARM_BASE	(0xfffe1000 + 0xec)
+
+static int enable_1510_mode = 0;
+
+struct omap_dma_lch {
+	int dev_id;
+	u16 saved_csr;
+	u16 enabled_irqs;
+	const char *dev_name;
+	void (* callback)(int lch, u16 ch_status, void *data);
+	void *data;
+	long flags;
+};
+
+static int dma_chan_count;
+
+static spinlock_t dma_chan_lock;
+static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
+
+const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
+	INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
+	INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
+	INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
+	INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
+	INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
+};
+
+static inline int get_gdma_dev(int req)
+{
+	u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
+	int shift = ((req - 1) % 5) * 6;
+
+	return ((__raw_readl(reg) >> shift) & 0x3f) + 1;
+}
+
+static inline void set_gdma_dev(int req, int dev)
+{
+	u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
+	int shift = ((req - 1) % 5) * 6;
+	u32 l;
+
+	l = __raw_readl(reg);
+	l &= ~(0x3f << shift);
+	l |= (dev - 1) << shift;
+	__raw_writel(l, reg);
+}
+
+static void clear_lch_regs(int lch)
+{
+	int i;
+	u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
+
+	for (i = 0; i < 0x2c; i += 2)
+		__raw_writew(0, lch_base + i);
+}
+
+void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
+				  int frame_count, int sync_mode)
+{
+	u16 w;
+
+	w = __raw_readw(OMAP_DMA_CSDP_REG(lch));
+	w &= ~0x03;
+	w |= data_type;
+	__raw_writew(w, OMAP_DMA_CSDP_REG(lch));
+
+	w = __raw_readw(OMAP_DMA_CCR_REG(lch));
+	w &= ~(1 << 5);
+	if (sync_mode == OMAP_DMA_SYNC_FRAME)
+		w |= 1 << 5;
+	__raw_writew(w, OMAP_DMA_CCR_REG(lch));
+
+	w = __raw_readw(OMAP_DMA_CCR2_REG(lch));
+	w &= ~(1 << 2);
+	if (sync_mode == OMAP_DMA_SYNC_BLOCK)
+		w |= 1 << 2;
+	__raw_writew(w, OMAP_DMA_CCR2_REG(lch));
+
+	__raw_writew(elem_count, OMAP_DMA_CEN_REG(lch));
+	__raw_writew(frame_count, OMAP_DMA_CFN_REG(lch));
+
+}
+
+void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+			     unsigned long src_start)
+{
+	u16 w;
+
+	w = __raw_readw(OMAP_DMA_CSDP_REG(lch));
+	w &= ~(0x1f << 2);
+	w |= src_port << 2;
+	__raw_writew(w, OMAP_DMA_CSDP_REG(lch));
+
+	w = __raw_readw(OMAP_DMA_CCR_REG(lch));
+	w &= ~(0x03 << 12);
+	w |= src_amode << 12;
+	__raw_writew(w, OMAP_DMA_CCR_REG(lch));
+
+	__raw_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch));
+	__raw_writew(src_start, OMAP_DMA_CSSA_L_REG(lch));
+}
+
+void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+			      unsigned long dest_start)
+{
+	u16 w;
+
+	w = __raw_readw(OMAP_DMA_CSDP_REG(lch));
+	w &= ~(0x1f << 9);
+	w |= dest_port << 9;
+	__raw_writew(w, OMAP_DMA_CSDP_REG(lch));
+
+	w = __raw_readw(OMAP_DMA_CCR_REG(lch));
+	w &= ~(0x03 << 14);
+	w |= dest_amode << 14;
+	__raw_writew(w, OMAP_DMA_CCR_REG(lch));
+
+	__raw_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch));
+	__raw_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch));
+}
+
+void omap_start_dma(int lch)
+{
+	u16 w;
+
+	/* Read CSR to make sure it's cleared. */
+	w = __raw_readw(OMAP_DMA_CSR_REG(lch));
+	/* Enable some nice interrupts. */
+	__raw_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch));
+
+	w = __raw_readw(OMAP_DMA_CCR_REG(lch));
+	w |= OMAP_DMA_CCR_EN;
+	__raw_writew(w, OMAP_DMA_CCR_REG(lch));
+	dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
+}
+
+void omap_stop_dma(int lch)
+{
+	u16 w;
+
+	/* Disable all interrupts on the channel */
+	__raw_writew(0, OMAP_DMA_CICR_REG(lch));
+
+	w = __raw_readw(OMAP_DMA_CCR_REG(lch));
+	w &= ~OMAP_DMA_CCR_EN;
+	__raw_writew(w, OMAP_DMA_CCR_REG(lch));
+	dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
+}
+
+void omap_enable_dma_irq(int lch, u16 bits)
+{
+	dma_chan[lch].enabled_irqs |= bits;
+}
+
+void omap_disable_dma_irq(int lch, u16 bits)
+{
+	dma_chan[lch].enabled_irqs &= ~bits;
+}
+
+static int dma_handle_ch(int ch)
+{
+	u16 csr;
+
+	if (enable_1510_mode && ch >= 6) {
+		csr = dma_chan[ch].saved_csr;
+		dma_chan[ch].saved_csr = 0;
+	} else
+		csr = __raw_readw(OMAP_DMA_CSR_REG(ch));
+	if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
+		dma_chan[ch + 6].saved_csr = csr >> 7;
+		csr &= 0x7f;
+	}
+	if (!csr)
+		return 0;
+	if (unlikely(dma_chan[ch].dev_id == -1)) {
+		printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
+		       ch, csr);
+		return 0;
+	}
+	if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
+		printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id);
+	if (unlikely(csr & OMAP_DMA_DROP_IRQ))
+		printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n",
+		       dma_chan[ch].dev_id);
+	if (likely(csr & OMAP_DMA_BLOCK_IRQ))
+		dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
+	if (likely(dma_chan[ch].callback != NULL))
+		dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
+	return 1;
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+	int ch = ((int) dev_id) - 1;
+	int handled = 0;
+
+	for (;;) {
+		int handled_now = 0;
+
+		handled_now += dma_handle_ch(ch);
+		if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
+			handled_now += dma_handle_ch(ch + 6);
+		if (!handled_now)
+			break;
+		handled += handled_now;
+	}
+
+	return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+int omap_request_dma(int dev_id, const char *dev_name,
+		     void (* callback)(int lch, u16 ch_status, void *data),
+		     void *data, int *dma_ch_out)
+{
+	int ch, free_ch = -1;
+	unsigned long flags;
+	struct omap_dma_lch *chan;
+
+	spin_lock_irqsave(&dma_chan_lock, flags);
+	for (ch = 0; ch < dma_chan_count; ch++) {
+		if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
+			free_ch = ch;
+			if (dev_id == 0)
+				break;
+		}
+		if (dev_id != 0 && dma_chan[ch].dev_id == dev_id) {
+			spin_unlock_irqrestore(&dma_chan_lock, flags);
+			return -EAGAIN;
+		}
+	}
+	if (free_ch == -1) {
+		spin_unlock_irqrestore(&dma_chan_lock, flags);
+		return -EBUSY;
+	}
+	chan = dma_chan + free_ch;
+	chan->dev_id = dev_id;
+	clear_lch_regs(free_ch);
+	spin_unlock_irqrestore(&dma_chan_lock, flags);
+
+	chan->dev_id = dev_id;
+	chan->dev_name = dev_name;
+	chan->callback = callback;
+	chan->data = data;
+	chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+
+	if (cpu_is_omap1610()) {
+		/* If the sync device is set, configure it dynamically. */
+		if (dev_id != 0) {
+			set_gdma_dev(free_ch + 1, dev_id);
+			dev_id = free_ch + 1;
+		}
+		/* Disable the 1510 compatibility mode and set the sync device
+		 * id. */
+		__raw_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch));
+	} else {
+		__raw_writew(dev_id, OMAP_DMA_CCR_REG(free_ch));
+	}
+	*dma_ch_out = free_ch;
+
+	return 0;
+}
+
+void omap_free_dma(int ch)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dma_chan_lock, flags);
+	if (dma_chan[ch].dev_id == -1) {
+		printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch);
+		spin_unlock_irqrestore(&dma_chan_lock, flags);
+		return;
+	}
+	dma_chan[ch].dev_id = -1;
+	spin_unlock_irqrestore(&dma_chan_lock, flags);
+
+	/* Disable all DMA interrupts for the channel. */
+	__raw_writew(0, OMAP_DMA_CICR_REG(ch));
+	/* Make sure the DMA transfer is stopped. */
+	__raw_writew(0, OMAP_DMA_CCR_REG(ch));
+}
+
+int omap_dma_in_1510_mode(void)
+{
+	return enable_1510_mode;
+}
+
+
+static struct lcd_dma_info {
+	spinlock_t lock;
+	int reserved;
+	void (* callback)(u16 status, void *data);
+	void *cb_data;
+
+	unsigned long addr, size;
+	int rotate, data_type, xres, yres;
+} lcd_dma;
+
+void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+			 int data_type)
+{
+	lcd_dma.addr = addr;
+	lcd_dma.data_type = data_type;
+	lcd_dma.xres = fb_xres;
+	lcd_dma.yres = fb_yres;
+}
+
+static void set_b1_regs(void)
+{
+	unsigned long top, bottom;
+	int es;
+	u16 w, en, fn;
+	s16 ei;
+	s32 fi;
+	u32 l;
+
+	switch (lcd_dma.data_type) {
+	case OMAP_DMA_DATA_TYPE_S8:
+		es = 1;
+		break;
+	case OMAP_DMA_DATA_TYPE_S16:
+		es = 2;
+		break;
+	case OMAP_DMA_DATA_TYPE_S32:
+		es = 4;
+		break;
+	default:
+		BUG();
+		return;
+	}
+
+	if (lcd_dma.rotate == 0) {
+		top = lcd_dma.addr;
+		bottom = lcd_dma.addr + (lcd_dma.xres * lcd_dma.yres - 1) * es;
+		/* 1510 DMA requires the bottom address to be 2 more than the
+		 * actual last memory access location. */
+		if (omap_dma_in_1510_mode() &&
+		    lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+			bottom += 2;
+		en = lcd_dma.xres;
+		fn = lcd_dma.yres;
+		ei = 0;
+		fi = 0;
+	} else {
+		top = lcd_dma.addr + (lcd_dma.xres - 1) * es;
+		bottom = lcd_dma.addr + (lcd_dma.yres - 1) * lcd_dma.xres * es;
+		en = lcd_dma.yres;
+		fn = lcd_dma.xres;
+		ei = (lcd_dma.xres - 1) * es + 1;
+		fi = -(lcd_dma.xres * (lcd_dma.yres - 1) + 2) * 2 + 1;
+	}
+
+	if (omap_dma_in_1510_mode()) {
+		__raw_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
+		__raw_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
+		__raw_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
+		__raw_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
+
+		return;
+	}
+
+	/* 1610 regs */
+	__raw_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
+	__raw_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
+	__raw_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
+	__raw_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
+
+	__raw_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
+	__raw_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
+
+	w = __raw_readw(OMAP1610_DMA_LCD_CSDP);
+	w &= ~0x03;
+	w |= lcd_dma.data_type;
+	__raw_writew(w, OMAP1610_DMA_LCD_CSDP);
+
+	if (!lcd_dma.rotate)
+		return;
+
+	/* Rotation stuff */
+	l = __raw_readw(OMAP1610_DMA_LCD_CSDP);
+	/* Disable burst access */
+	l &= ~(0x03 << 7);
+	__raw_writew(l, OMAP1610_DMA_LCD_CSDP);
+
+	l = __raw_readw(OMAP1610_DMA_LCD_CCR);
+	/* Set the double-indexed addressing mode */
+	l |= (0x03 << 12);
+	__raw_writew(l, OMAP1610_DMA_LCD_CCR);
+
+	__raw_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
+	__raw_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
+	__raw_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
+}
+
+void omap_set_lcd_dma_b1_rotation(int rotate)
+{
+	if (omap_dma_in_1510_mode()) {
+		printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
+		BUG();
+		return;
+	}
+	lcd_dma.rotate = rotate;
+}
+
+int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+			 void *data)
+{
+	spin_lock_irq(&lcd_dma.lock);
+	if (lcd_dma.reserved) {
+		spin_unlock_irq(&lcd_dma.lock);
+		printk(KERN_ERR "LCD DMA channel already reserved\n");
+		BUG();
+		return -EBUSY;
+	}
+	lcd_dma.reserved = 1;
+	spin_unlock_irq(&lcd_dma.lock);
+	lcd_dma.callback = callback;
+	lcd_dma.cb_data = data;
+
+	return 0;
+}
+
+void omap_free_lcd_dma(void)
+{
+	spin_lock(&lcd_dma.lock);
+	if (!lcd_dma.reserved) {
+		spin_unlock(&lcd_dma.lock);
+		printk(KERN_ERR "LCD DMA is not reserved\n");
+		BUG();
+		return;
+	}
+	if (!enable_1510_mode)
+		__raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
+	lcd_dma.reserved = 0;
+	spin_unlock(&lcd_dma.lock);
+}
+
+void omap_start_lcd_dma(void)
+{
+	if (!enable_1510_mode) {
+		/* Set some reasonable defaults */
+		__raw_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
+		__raw_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
+		__raw_writew(0x5740, OMAP1610_DMA_LCD_CCR);
+	}
+	set_b1_regs();
+	if (!enable_1510_mode)
+		__raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR);
+}
+
+void omap_stop_lcd_dma(void)
+{
+	if (!enable_1510_mode)
+		__raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR);
+}
+
+static int __init omap_init_dma(void)
+{
+	int ch, r;
+
+	if (cpu_is_omap1510()) {
+		printk(KERN_INFO "DMA support for OMAP1510 initialized\n");
+		dma_chan_count = 9;
+		enable_1510_mode = 1;
+	} else if (cpu_is_omap1610()) {
+		printk(KERN_INFO "OMAP DMA hardware version %d\n",
+		       __raw_readw(OMAP_DMA_HW_ID_REG));
+		printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
+		       (__raw_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | __raw_readw(OMAP_DMA_CAPS_0_L_REG),
+		       (__raw_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | __raw_readw(OMAP_DMA_CAPS_1_L_REG),
+		       __raw_readw(OMAP_DMA_CAPS_2_REG), __raw_readw(OMAP_DMA_CAPS_3_REG),
+		       __raw_readw(OMAP_DMA_CAPS_4_REG));
+		if (!enable_1510_mode) {
+			u16 w;
+
+			/* Disable OMAP 3.0/3.1 compatibility mode. */
+			w = __raw_readw(OMAP_DMA_GSCR_REG);
+			w |= 1 << 3;
+			__raw_writew(w, OMAP_DMA_GSCR_REG);
+			dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
+		} else
+			dma_chan_count = 9;
+	} else {
+		dma_chan_count = 0;
+		return 0;
+	}
+
+	memset(&lcd_dma, 0, sizeof(lcd_dma));
+	spin_lock_init(&lcd_dma.lock);
+	spin_lock_init(&dma_chan_lock);
+	memset(&dma_chan, 0, sizeof(dma_chan));
+
+	for (ch = 0; ch < dma_chan_count; ch++) {
+		dma_chan[ch].dev_id = -1;
+		if (ch >= 6 && enable_1510_mode)
+			continue;
+
+		/* request_irq() doesn't like dev_id (ie. ch) being zero,
+		 * so we have to kludge around this. */
+		r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA",
+				(void *) (ch + 1));
+		if (r != 0) {
+			int i;
+
+			printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n",
+			       dma_irq[ch], r);
+			for (i = 0; i < ch; i++)
+				free_irq(dma_irq[i], (void *) (i + 1));
+			return r;
+		}
+	}
+
+	return 0;
+}
+arch_initcall(omap_init_dma);
+
+EXPORT_SYMBOL(omap_request_dma);
+EXPORT_SYMBOL(omap_free_dma);
+EXPORT_SYMBOL(omap_start_dma);
+EXPORT_SYMBOL(omap_stop_dma);
+EXPORT_SYMBOL(omap_set_dma_transfer_params);
+EXPORT_SYMBOL(omap_set_dma_src_params);
+EXPORT_SYMBOL(omap_set_dma_dest_params);
+
+EXPORT_SYMBOL(omap_request_lcd_dma);
+EXPORT_SYMBOL(omap_free_lcd_dma);
+EXPORT_SYMBOL(omap_start_lcd_dma);
+EXPORT_SYMBOL(omap_stop_lcd_dma);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
diff -Nru a/arch/arm/mach-omap/fpga.c b/arch/arm/mach-omap/fpga.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/fpga.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,209 @@
+/*
+ * linux/arch/arm/mach-omap/fpga.c
+ *
+ * Interrupt handler for OMAP-1510 FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/fpga.h>
+#include <asm/arch/gpio.h>
+
+unsigned char fpga_read(int reg)
+{
+	return __raw_readb(reg);
+}
+
+void fpga_write(unsigned char val, int reg)
+{
+	__raw_writeb(val, reg);
+}
+
+static void fpga_mask_irq(unsigned int irq)
+{
+	irq -= IH_FPGA_BASE;
+
+	if (irq < 8)
+		__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO)
+			      & ~(1 << irq)), OMAP1510P1_FPGA_IMR_LO);
+	else if (irq < 16)
+		__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI)
+			      & ~(1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI);
+	else
+		__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
+			      & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
+}
+
+
+static inline u32 get_fpga_unmasked_irqs(void)
+{
+	return
+		((__raw_readb(OMAP1510P1_FPGA_ISR_LO) &
+		  __raw_readb(OMAP1510P1_FPGA_IMR_LO))) |
+		((__raw_readb(OMAP1510P1_FPGA_ISR_HI) &
+		  __raw_readb(OMAP1510P1_FPGA_IMR_HI)) << 8) |
+		((__raw_readb(INNOVATOR_FPGA_ISR2) &
+		  __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
+}
+
+
+static void fpga_ack_irq(unsigned int irq)
+{
+	/* Don't need to explicitly ACK FPGA interrupts */
+}
+
+static void fpga_unmask_irq(unsigned int irq)
+{
+	irq -= IH_FPGA_BASE;
+
+	if (irq < 8)
+		__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_LO) | (1 << irq)),
+		     OMAP1510P1_FPGA_IMR_LO);
+	else if (irq < 16)
+		__raw_writeb((__raw_readb(OMAP1510P1_FPGA_IMR_HI)
+			      | (1 << (irq - 8))), OMAP1510P1_FPGA_IMR_HI);
+	else
+		__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
+			      | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
+}
+
+static void fpga_mask_ack_irq(unsigned int irq)
+{
+	fpga_mask_irq(irq);
+	fpga_ack_irq(irq);
+}
+
+void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
+			      struct pt_regs *regs)
+{
+	struct irqdesc *d;
+	u32 stat;
+	int fpga_irq;
+
+	/*
+	 * Acknowledge the parent IRQ.
+	 */
+	desc->chip->ack(irq);
+
+	for (;;) {
+		stat = get_fpga_unmasked_irqs();
+
+		if (!stat) {
+			break;
+		}
+
+		for (fpga_irq = IH_FPGA_BASE;
+			(fpga_irq < (IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
+			fpga_irq++, stat >>= 1) {
+			if (stat & 1) {
+				d = irq_desc + fpga_irq;
+				d->handle(fpga_irq, d, regs);
+				desc->chip->unmask(irq);
+			}
+		}
+	}
+}
+
+static struct irqchip omap_fpga_irq_ack = {
+	.ack		= fpga_mask_ack_irq,
+	.mask		= fpga_mask_irq,
+	.unmask		= fpga_unmask_irq,
+};
+
+
+static struct irqchip omap_fpga_irq = {
+	.ack		= fpga_ack_irq,
+	.mask		= fpga_mask_irq,
+	.unmask		= fpga_unmask_irq,
+};
+
+/*
+ * All of the FPGA interrupt request inputs except for the touchscreen are
+ * edge-sensitive; the touchscreen is level-sensitive.  The edge-sensitive
+ * interrupts are acknowledged as a side-effect of reading the interrupt
+ * status register from the FPGA.  The edge-sensitive interrupt inputs
+ * cause a problem with level interrupt requests, such as Ethernet.  The
+ * problem occurs when a level interrupt request is asserted while its
+ * interrupt input is masked in the FPGA, which results in a missed
+ * interrupt.
+ *
+ * In an attempt to workaround the problem with missed interrupts, the
+ * mask_ack routine for all of the FPGA interrupts has been changed from
+ * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
+ * being serviced is left unmasked.  We can do this because the FPGA cascade
+ * interrupt is installed with the SA_INTERRUPT flag, which leaves all
+ * interrupts masked at the CPU while an FPGA interrupt handler executes.
+ *
+ * Limited testing indicates that this workaround appears to be effective
+ * for the smc9194 Ethernet driver used on the Innovator.  It should work
+ * on other FPGA interrupts as well, but any drivers that explicitly mask
+ * interrupts at the interrupt controller via disable_irq/enable_irq
+ * could pose a problem.
+ */
+void fpga_init_irq(void)
+{
+	int i;
+
+	__raw_writeb(0, OMAP1510P1_FPGA_IMR_LO);
+	__raw_writeb(0, OMAP1510P1_FPGA_IMR_HI);
+	__raw_writeb(0, INNOVATOR_FPGA_IMR2);
+
+	for (i = IH_FPGA_BASE; i < (IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
+
+		if (i == INT_FPGA_TS) {
+			/*
+			 * The touchscreen interrupt is level-sensitive, so
+			 * we'll use the regular mask_ack routine for it.
+			 */
+			set_irq_chip(i, &omap_fpga_irq_ack);
+		}
+		else {
+			/*
+			 * All FPGA interrupts except the touchscreen are
+			 * edge-sensitive, so we won't mask them.
+			 */
+			set_irq_chip(i, &omap_fpga_irq);
+		}
+
+		set_irq_handler(i, do_level_IRQ);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	/*
+	 * The FPGA interrupt line is connected to GPIO13. Claim this pin for
+	 * the ARM.
+	 *
+	 * NOTE: For general GPIO/MPUIO access and interrupts, please see
+	 * gpio.[ch]
+	 */
+	omap_request_gpio(13);
+	omap_set_gpio_direction(13, 1);
+	omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
+	set_irq_chained_handler(INT_FPGA, innovator_fpga_IRQ_demux);
+}
+
+EXPORT_SYMBOL(fpga_init_irq);
+EXPORT_SYMBOL(fpga_read);
+EXPORT_SYMBOL(fpga_write);
diff -Nru a/arch/arm/mach-omap/gpio.c b/arch/arm/mach-omap/gpio.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/gpio.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,755 @@
+/*
+ *  linux/arch/arm/mach-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pm.h>
+#include <asm/mach/irq.h>
+
+#include <asm/io.h>
+
+/*
+ * OMAP1510 GPIO registers
+ */
+#define OMAP1510_GPIO_BASE		0xfffce000
+#define OMAP1510_GPIO_DATA_INPUT	0x00
+#define OMAP1510_GPIO_DATA_OUTPUT	0x04
+#define OMAP1510_GPIO_DIR_CONTROL	0x08
+#define OMAP1510_GPIO_INT_CONTROL	0x0c
+#define OMAP1510_GPIO_INT_MASK		0x10
+#define OMAP1510_GPIO_INT_STATUS	0x14
+#define OMAP1510_GPIO_PIN_CONTROL	0x18
+
+#define OMAP1510_IH_GPIO_BASE		64
+
+/*
+ * OMAP1610 specific GPIO registers
+ */
+#define OMAP1610_GPIO1_BASE		0xfffbe400
+#define OMAP1610_GPIO2_BASE		0xfffbec00
+#define OMAP1610_GPIO3_BASE		0xfffbb400
+#define OMAP1610_GPIO4_BASE		0xfffbbc00
+#define OMAP1610_GPIO_REVISION		0x0000
+#define OMAP1610_GPIO_SYSCONFIG		0x0010
+#define OMAP1610_GPIO_SYSSTATUS		0x0014
+#define OMAP1610_GPIO_IRQSTATUS1	0x0018
+#define OMAP1610_GPIO_IRQENABLE1	0x001c
+#define OMAP1610_GPIO_DATAIN		0x002c
+#define OMAP1610_GPIO_DATAOUT		0x0030
+#define OMAP1610_GPIO_DIRECTION		0x0034
+#define OMAP1610_GPIO_EDGE_CTRL1	0x0038
+#define OMAP1610_GPIO_EDGE_CTRL2	0x003c
+#define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
+#define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
+#define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
+#define OMAP1610_GPIO_SET_DATAOUT	0x00f0
+
+/*
+ * OMAP730 specific GPIO registers
+ */
+#define OMAP730_GPIO1_BASE		0xfffbc000
+#define OMAP730_GPIO2_BASE		0xfffbc800
+#define OMAP730_GPIO3_BASE		0xfffbd000
+#define OMAP730_GPIO4_BASE		0xfffbd800
+#define OMAP730_GPIO5_BASE		0xfffbe000
+#define OMAP730_GPIO6_BASE		0xfffbe800
+#define OMAP730_GPIO_DATA_INPUT		0x00
+#define OMAP730_GPIO_DATA_OUTPUT	0x04
+#define OMAP730_GPIO_DIR_CONTROL	0x08
+#define OMAP730_GPIO_INT_CONTROL	0x0c
+#define OMAP730_GPIO_INT_MASK		0x10
+#define OMAP730_GPIO_INT_STATUS		0x14
+
+#define OMAP_MPUIO_MASK         (~OMAP_MAX_GPIO_LINES & 0xff)
+
+struct gpio_bank {
+	u32 base;
+	u16 irq;
+	u16 virtual_irq_start;
+	u8 method;
+	u32 reserved_map;
+	spinlock_t lock;
+};
+
+#define METHOD_MPUIO		0
+#define METHOD_GPIO_1510	1
+#define METHOD_GPIO_1610	2
+#define METHOD_GPIO_730	3
+
+#ifdef CONFIG_ARCH_OMAP1610
+static struct gpio_bank gpio_bank_1610[5] = {
+	{ OMAP_MPUIO_BASE,     INT_MPUIO,	    IH_MPUIO_BASE,     METHOD_MPUIO},
+	{ OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,	    IH_GPIO_BASE,      METHOD_GPIO_1610 },
+	{ OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
+	{ OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
+	{ OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+static struct gpio_bank gpio_bank_1510[2] = {
+	{ OMAP_MPUIO_BASE,    INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
+	{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP730
+static struct gpio_bank gpio_bank_730[7] = {
+	{ OMAP_MPUIO_BASE,     INT_MPUIO,	    IH_MPUIO_BASE,	METHOD_MPUIO },
+	{ OMAP730_GPIO1_BASE,  INT_GPIO_BANK1,	    IH_GPIO_BASE,	METHOD_GPIO_730 },
+	{ OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,	METHOD_GPIO_730 },
+	{ OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,	METHOD_GPIO_730 },
+	{ OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,	METHOD_GPIO_730 },
+	{ OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
+	{ OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
+};
+#endif
+
+static struct gpio_bank *gpio_bank;
+static int gpio_bank_count;
+
+static inline struct gpio_bank *get_gpio_bank(int gpio)
+{
+#ifdef CONFIG_ARCH_OMAP1510
+	if (cpu_is_omap1510()) {
+		if (OMAP_GPIO_IS_MPUIO(gpio))
+			return &gpio_bank[0];
+		return &gpio_bank[1];
+	}
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+	if (cpu_is_omap1610()) {
+		if (OMAP_GPIO_IS_MPUIO(gpio))
+			return &gpio_bank[0];
+		return &gpio_bank[1 + (gpio >> 4)];
+	}
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+	if (cpu_is_omap730()) {
+		if (OMAP_GPIO_IS_MPUIO(gpio))
+			return &gpio_bank[0];
+		return &gpio_bank[1 + (gpio >> 5)];
+	}
+#endif
+}
+
+static inline int get_gpio_index(int gpio)
+{
+	if (cpu_is_omap730())
+		return gpio & 0x1f;
+	else
+		return gpio & 0x0f;
+}
+
+static inline int gpio_valid(int gpio)
+{
+	if (gpio < 0)
+		return -1;
+	if (OMAP_GPIO_IS_MPUIO(gpio)) {
+		if ((gpio & OMAP_MPUIO_MASK) > 16)
+			return -1;
+		return 0;
+	}
+#ifdef CONFIG_ARCH_OMAP1510
+	if (cpu_is_omap1510() && gpio < 16)
+		return 0;
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+	if (cpu_is_omap1610() && gpio < 64)
+		return 0;
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+	if (cpu_is_omap730() && gpio < 192)
+		return 0;
+#endif
+	return -1;
+}
+
+static int check_gpio(int gpio)
+{
+	if (unlikely(gpio_valid(gpio)) < 0) {
+		printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
+		dump_stack();
+		return -1;
+	}
+	return 0;
+}
+
+static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+{
+	u32 reg = bank->base;
+	u32 l;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_IO_CNTL;
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_DIR_CONTROL;
+		break;
+	case METHOD_GPIO_1610:
+		reg += OMAP1610_GPIO_DIRECTION;
+		break;
+	case METHOD_GPIO_730:
+		reg += OMAP730_GPIO_DIR_CONTROL;
+		break;
+	}
+	l = __raw_readl(reg);
+	if (is_input)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__raw_writel(l, reg);
+}
+
+void omap_set_gpio_direction(int gpio, int is_input)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	spin_lock(&bank->lock);
+	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
+	spin_unlock(&bank->lock);
+}
+
+static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+{
+	u32 reg = bank->base;
+	u32 l = 0;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_OUTPUT_REG;
+		l = __raw_readl(reg);
+		if (enable)
+			l |= 1 << gpio;
+		else
+			l &= ~(1 << gpio);
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_DATA_OUTPUT;
+		l = __raw_readl(reg);
+		if (enable)
+			l |= 1 << gpio;
+		else
+			l &= ~(1 << gpio);
+		break;
+	case METHOD_GPIO_1610:
+		if (enable)
+			reg += OMAP1610_GPIO_SET_DATAOUT;
+		else
+			reg += OMAP1610_GPIO_CLEAR_DATAOUT;
+		l = 1 << gpio;
+		break;
+	case METHOD_GPIO_730:
+		reg += OMAP730_GPIO_DATA_OUTPUT;
+		l = __raw_readl(reg);
+		if (enable)
+			l |= 1 << gpio;
+		else
+			l &= ~(1 << gpio);
+		break;
+	default:
+		BUG();
+		return;
+	}
+	__raw_writel(l, reg);
+}
+
+void omap_set_gpio_dataout(int gpio, int enable)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	spin_lock(&bank->lock);
+	_set_gpio_dataout(bank, get_gpio_index(gpio), enable);
+	spin_unlock(&bank->lock);
+}
+
+int omap_get_gpio_datain(int gpio)
+{
+	struct gpio_bank *bank;
+	u32 reg;
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+	bank = get_gpio_bank(gpio);
+	reg = bank->base;
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_INPUT_LATCH;
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_DATA_INPUT;
+		break;
+	case METHOD_GPIO_1610:
+		reg += OMAP1610_GPIO_DATAIN;
+		break;
+	default:
+		BUG();
+		return -1;
+	}
+	return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+}
+
+static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
+{
+	u32 reg = bank->base;
+	u32 l;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_GPIO_INT_EDGE_REG;
+		l = __raw_readl(reg);
+		if (edge == OMAP_GPIO_RISING_EDGE)
+			l |= 1 << gpio;
+		else
+			l &= ~(1 << gpio);
+		__raw_writel(l, reg);
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_INT_CONTROL;
+		l = __raw_readl(reg);
+		if (edge == OMAP_GPIO_RISING_EDGE)
+			l |= 1 << gpio;
+		else
+			l &= ~(1 << gpio);
+		__raw_writel(l, reg);
+		break;
+	case METHOD_GPIO_1610:
+		edge &= 0x03;
+		if (gpio & 0x08)
+			reg += OMAP1610_GPIO_EDGE_CTRL2;
+		else
+			reg += OMAP1610_GPIO_EDGE_CTRL1;
+		gpio &= 0x07;
+		l = __raw_readl(reg);
+		l &= ~(3 << (gpio << 1));
+		l |= edge << (gpio << 1);
+		__raw_writel(l, reg);
+		break;
+	case METHOD_GPIO_730:
+		reg += OMAP730_GPIO_INT_CONTROL;
+		l = __raw_readl(reg);
+		if (edge == OMAP_GPIO_RISING_EDGE)
+			l |= 1 << gpio;
+		else
+			l &= ~(1 << gpio);
+		__raw_writel(l, reg);
+		break;
+	default:
+		BUG();
+		return;
+	}
+}
+
+void omap_set_gpio_edge_ctrl(int gpio, int edge)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	spin_lock(&bank->lock);
+	_set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge);
+	spin_unlock(&bank->lock);
+}
+
+
+static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
+{
+	u32 reg = bank->base, l;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG);
+		return (l & (1 << gpio)) ?
+			OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
+	case METHOD_GPIO_1510:
+		l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
+		return (l & (1 << gpio)) ?
+			OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
+	case METHOD_GPIO_1610:
+		if (gpio & 0x08)
+			reg += OMAP1610_GPIO_EDGE_CTRL2;
+		else
+			reg += OMAP1610_GPIO_EDGE_CTRL1;
+		return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
+	case METHOD_GPIO_730:
+		l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
+		return (l & (1 << gpio)) ?
+			OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
+	default:
+		BUG();
+		return -1;
+	}
+}
+
+static void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
+{
+	u32 reg = bank->base;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		/* MPUIO irqstatus cannot be cleared one bit at a time,
+		 * so do nothing here */
+		return;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_INT_STATUS;
+		break;
+	case METHOD_GPIO_1610:
+		reg += OMAP1610_GPIO_IRQSTATUS1;
+		break;
+	case METHOD_GPIO_730:
+		reg += OMAP730_GPIO_INT_STATUS;
+		break;
+	default:
+		BUG();
+		return;
+	}
+	__raw_writel(1 << get_gpio_index(gpio), reg);
+}
+
+static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
+{
+	u32 reg = bank->base;
+	u32 l;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_GPIO_MASKIT;
+		l = __raw_readl(reg);
+		if (enable)
+			l &= ~(1 << gpio);
+		else
+			l |= 1 << gpio;
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_INT_MASK;
+		l = __raw_readl(reg);
+		if (enable)
+			l &= ~(1 << gpio);
+		else
+			l |= 1 << gpio;
+		break;
+	case METHOD_GPIO_1610:
+		if (enable) {
+			reg += OMAP1610_GPIO_SET_IRQENABLE1;
+			_clear_gpio_irqstatus(bank, gpio);
+		} else
+			reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
+		l = 1 << gpio;
+		break;
+	case METHOD_GPIO_730:
+		reg += OMAP730_GPIO_INT_MASK;
+		l = __raw_readl(reg);
+		if (enable)
+			l &= ~(1 << gpio);
+		else
+			l |= 1 << gpio;
+		break;
+	default:
+		BUG();
+		return;
+	}
+	__raw_writel(l, reg);
+}
+
+int omap_request_gpio(int gpio)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+
+	bank = get_gpio_bank(gpio);
+	spin_lock(&bank->lock);
+	if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
+		printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
+		dump_stack();
+		spin_unlock(&bank->lock);
+		return -1;
+	}
+	bank->reserved_map |= (1 << get_gpio_index(gpio));
+#ifdef CONFIG_ARCH_OMAP1510
+	if (bank->method == METHOD_GPIO_1510) {
+		u32 reg;
+
+		/* Claim the pin for the ARM */
+		reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
+		__raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
+	}
+#endif
+	spin_unlock(&bank->lock);
+
+	return 0;
+}
+
+void omap_free_gpio(int gpio)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	spin_lock(&bank->lock);
+	if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
+		printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
+		dump_stack();
+		spin_unlock(&bank->lock);
+		return;
+	}
+	bank->reserved_map &= ~(1 << get_gpio_index(gpio));
+	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
+	_set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
+	spin_unlock(&bank->lock);
+}
+
+static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
+			     struct pt_regs *regs)
+{
+	u32 isr_reg = 0;
+	struct gpio_bank *bank = (struct gpio_bank *) desc->data;
+
+	/*
+	 * Acknowledge the parent IRQ.
+	 */
+	desc->chip->ack(irq);
+
+	/* Since the level 1 GPIO interrupt cascade (IRQ14) is configured as
+	 * edge-sensitive, we need to unmask it here in order to avoid missing
+	 * any additional GPIO interrupts that might occur after the last time
+	 * we check for pending GPIO interrupts here.
+	 * We are relying on the fact that this interrupt handler was installed
+	 * with the SA_INTERRUPT flag so that interrupts are disabled at the
+	 * CPU while it is executing.
+	 */
+	desc->chip->unmask(irq);
+
+	if (bank->method == METHOD_MPUIO)
+		isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
+#ifdef CONFIG_ARCH_OMAP1510
+	if (bank->method == METHOD_GPIO_1510)
+		isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+	if (bank->method == METHOD_GPIO_1610)
+		isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+	if (bank->method == METHOD_GPIO_730)
+		isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
+#endif
+	for (;;) {
+		u32 isr = __raw_readl(isr_reg);
+		unsigned int gpio_irq;
+
+		if (!isr)
+			break;
+		gpio_irq = bank->virtual_irq_start;
+
+		for (; isr != 0; isr >>= 1, gpio_irq++) {
+			if (isr & 1) {
+				struct irqdesc *d = irq_desc + gpio_irq;
+				d->handle(gpio_irq, d, regs);
+			}
+		}
+	}
+}
+
+static void gpio_ack_irq(unsigned int irq)
+{
+	unsigned int gpio = irq - IH_GPIO_BASE;
+	struct gpio_bank *bank = get_gpio_bank(gpio);
+
+#ifdef CONFIG_ARCH_OMAP1510
+	if (bank->method == METHOD_GPIO_1510)
+		__raw_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS);
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+	if (bank->method == METHOD_GPIO_1610)
+		__raw_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+	if (bank->method == METHOD_GPIO_730)
+		__raw_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS);
+#endif
+}
+
+static void gpio_mask_irq(unsigned int irq)
+{
+	unsigned int gpio = irq - IH_GPIO_BASE;
+	struct gpio_bank *bank = get_gpio_bank(gpio);
+
+	_set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
+}
+
+static void gpio_unmask_irq(unsigned int irq)
+{
+	unsigned int gpio = irq - IH_GPIO_BASE;
+	struct gpio_bank *bank = get_gpio_bank(gpio);
+
+	if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == OMAP_GPIO_NO_EDGE) {
+		printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while no edge is set\n",
+		       gpio);
+		_set_gpio_edge_ctrl(bank, get_gpio_index(gpio), OMAP_GPIO_RISING_EDGE);
+	}
+	_set_gpio_irqenable(bank, get_gpio_index(gpio), 1);
+}
+
+static void mpuio_ack_irq(unsigned int irq)
+{
+	/* The ISR is reset automatically, so do nothing here. */
+}
+
+static void mpuio_mask_irq(unsigned int irq)
+{
+	unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+	struct gpio_bank *bank = get_gpio_bank(gpio);
+
+	_set_gpio_irqenable(bank, gpio, 0);
+}
+
+static void mpuio_unmask_irq(unsigned int irq)
+{
+	unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+	struct gpio_bank *bank = get_gpio_bank(gpio);
+
+	_set_gpio_irqenable(bank, gpio, 1);
+}
+
+static struct irqchip gpio_irq_chip = {
+	.ack	= gpio_ack_irq,
+	.mask	= gpio_mask_irq,
+	.unmask = gpio_unmask_irq,
+};
+
+static struct irqchip mpuio_irq_chip = {
+	.ack	= mpuio_ack_irq,
+	.mask	= mpuio_mask_irq,
+	.unmask = mpuio_unmask_irq
+};
+
+static int initialized = 0;
+
+static int __init _omap_gpio_init(void)
+{
+	int i;
+	struct gpio_bank *bank;
+
+	initialized = 1;
+
+#ifdef CONFIG_ARCH_OMAP1510
+	if (cpu_is_omap1510()) {
+		printk(KERN_INFO "OMAP1510 GPIO hardware\n");
+		gpio_bank_count = 2;
+		gpio_bank = gpio_bank_1510;
+	}
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+	if (cpu_is_omap1610()) {
+		int rev;
+
+		gpio_bank_count = 5;
+		gpio_bank = gpio_bank_1610;
+		rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+		printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
+		       (rev >> 4) & 0x0f, rev & 0x0f);
+	}
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+	if (cpu_is_omap730()) {
+		printk(KERN_INFO "OMAP730 GPIO hardware\n");
+		gpio_bank_count = 7;
+		gpio_bank = gpio_bank_730;
+	}
+#endif
+	for (i = 0; i < gpio_bank_count; i++) {
+		int j, gpio_count = 16;
+
+		bank = &gpio_bank[i];
+		bank->reserved_map = 0;
+		spin_lock_init(&bank->lock);
+		if (bank->method == METHOD_MPUIO) {
+			__raw_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
+		}
+#ifdef CONFIG_ARCH_OMAP1510
+		if (bank->method == METHOD_GPIO_1510) {
+			__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
+			__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
+		}
+#endif
+#ifdef CONFIG_ARCH_OMAP1610
+		if (bank->method == METHOD_GPIO_1610) {
+			__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
+			__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+		}
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+		if (bank->method == METHOD_GPIO_730) {
+			__raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
+			__raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
+
+			gpio_count = 32; /* 730 has 32-bit GPIOs */
+		}
+#endif
+		for (j = bank->virtual_irq_start;
+		     j < bank->virtual_irq_start + gpio_count; j++) {
+			if (bank->method == METHOD_MPUIO)
+				set_irq_chip(j, &mpuio_irq_chip);
+			else
+				set_irq_chip(j, &gpio_irq_chip);
+			set_irq_handler(j, do_level_IRQ);
+			set_irq_flags(j, IRQF_VALID);
+		}
+		set_irq_chained_handler(bank->irq, gpio_irq_handler);
+		set_irq_data(bank->irq, bank);
+	}
+
+	/* Enable system clock for GPIO module.
+	 * The CAM_CLK_CTRL_REG *is* really the right place. */
+	if (cpu_is_omap1610())
+		__raw_writel(__raw_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG);
+
+	return 0;
+}
+
+/*
+ * This may get called early from board specific init
+ */
+int omap_gpio_init(void)
+{
+	if (!initialized)
+		return _omap_gpio_init();
+	else
+		return 0;
+}
+
+EXPORT_SYMBOL(omap_gpio_init);
+EXPORT_SYMBOL(omap_request_gpio);
+EXPORT_SYMBOL(omap_free_gpio);
+
+arch_initcall(omap_gpio_init);
diff -Nru a/arch/arm/mach-omap/innovator1510.c b/arch/arm/mach-omap/innovator1510.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/innovator1510.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,99 @@
+/*
+ * linux/arch/arm/mach-omap/innovator1510.c
+ *
+ * Board specific inits for OMAP-1510 Innovator
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/clocks.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/fpga.h>
+
+#include "common.h"
+
+extern int omap_gpio_init(void);
+
+void innovator_init_irq(void)
+{
+	omap_init_irq();
+	omap_gpio_init();
+	fpga_init_irq();
+}
+
+static struct resource smc91x_resources[] = {
+	[0] = {
+		.start	= OMAP1510P1_FPGA_ETHR_START,	/* Physical */
+		.end	= OMAP1510P1_FPGA_ETHR_START + 16,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= INT_ETHER,
+		.end	= INT_ETHER,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smc91x_device = {
+	.name		= "smc91x",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smc91x_resources),
+	.resource	= smc91x_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&smc91x_device,
+};
+
+static void __init innovator_init(void)
+{
+	if (!machine_is_innovator())
+		return;
+
+	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+/* Only FPGA needs to be mapped here. All others are done with ioremap */
+static struct map_desc innovator_io_desc[] __initdata = {
+{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE,
+	MT_DEVICE },
+};
+
+static void __init innovator_map_io(void)
+{
+	omap_map_io();
+	iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc));
+
+	/* Dump the Innovator FPGA rev early - useful info for support. */
+	printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
+	       fpga_read(OMAP1510P1_FPGA_REV_HIGH),
+	       fpga_read(OMAP1510P1_FPGA_REV_LOW),
+	       fpga_read(OMAP1510P1_FPGA_BOARD_REV));
+}
+
+MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1510")
+	MAINTAINER("MontaVista Software, Inc.")
+	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
+	BOOT_PARAMS(0x10000100)
+	MAPIO(innovator_map_io)
+	INITIRQ(innovator_init_irq)
+	INIT_MACHINE(innovator_init)
+MACHINE_END
diff -Nru a/arch/arm/mach-omap/innovator1610.c b/arch/arm/mach-omap/innovator1610.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/innovator1610.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,91 @@
+/*
+ * linux/arch/arm/mach-omap/innovator1610.c
+ *
+ * This file contains Innovator-specific code.
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/irqs.h>
+
+#include "common.h"
+
+void
+innovator_init_irq(void)
+{
+	omap_init_irq();
+}
+
+static struct resource smc91x_resources[] = {
+	[0] = {
+		.start	= OMAP1610_ETHR_START,		/* Physical */
+		.end	= OMAP1610_ETHR_START + SZ_4K,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= 0,				/* Really GPIO 0 */
+		.end	= 0,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smc91x_device = {
+	.name		= "smc91x",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smc91x_resources),
+	.resource	= smc91x_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&smc91x_device,
+};
+
+static void __init innovator_init(void)
+{
+	if (!machine_is_innovator())
+		return;
+
+	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static struct map_desc innovator_io_desc[] __initdata = {
+{ OMAP1610_ETHR_BASE, OMAP1610_ETHR_START, OMAP1610_ETHR_SIZE,MT_DEVICE },
+{ OMAP1610_NOR_FLASH_BASE, OMAP1610_NOR_FLASH_START, OMAP1610_NOR_FLASH_SIZE,
+	MT_DEVICE },
+};
+
+static void __init innovator_map_io(void)
+{
+	omap_map_io();
+	iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc));
+}
+
+MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1610")
+	MAINTAINER("MontaVista Software, Inc.")
+	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
+	BOOT_PARAMS(0x10000100)
+	MAPIO(innovator_map_io)
+	INITIRQ(innovator_init_irq)
+	INIT_MACHINE(innovator_init)
+MACHINE_END
+
diff -Nru a/arch/arm/mach-omap/irq.c b/arch/arm/mach-omap/irq.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/irq.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,224 @@
+/*
+ * linux/arch/arm/mach-omap/irq.c
+ *
+ * Interrupt handler for OMAP-1510 and 1610
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Modified for OMAP-1610 by Tony Lindgren <tony.lindgren@nokia.com>
+ * GPIO interrupt handler moved to gpio.c for OMAP-1610 by Juha Yrjola
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/gpio.h>
+
+#include <asm/io.h>
+
+#define NUM_IRQS	IH_BOARD_BASE
+
+static void mask_irq(unsigned int irq);
+static void unmask_irq(unsigned int irq);
+static void ack_irq(unsigned int irq);
+
+static inline void
+write_ih(int level, int reg, u32 value)
+{
+	if (cpu_is_omap1510()) {
+		__raw_writel(value,
+			(IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) +
+				(reg))));
+	} else {
+		if (level) {
+			__raw_writel(value,
+				IO_ADDRESS(OMAP_IH2_BASE + ((level - 1) << 8) +
+					reg));
+		} else {
+			__raw_writel(value, IO_ADDRESS(OMAP_IH1_BASE + reg));
+		}
+	}
+}
+
+static inline u32
+read_ih(int level, int reg)
+{
+	if (cpu_is_omap1510()) {
+		return __raw_readl((IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE)
+					 + (reg))));
+	} else {
+		if (level) {
+			return __raw_readl(IO_ADDRESS(OMAP_IH2_BASE +
+					((level - 1) << 8) + reg));
+		} else {
+			return __raw_readl(IO_ADDRESS(OMAP_IH1_BASE + reg));
+		}
+	}
+}
+
+static inline int
+get_level(int irq)
+{
+	if (cpu_is_omap1510()) {
+		return (((irq) < IH2_BASE) ? 0 : 1);
+	} else {
+		if (irq < IH2_BASE)
+			return 0;
+		else {
+			return (irq >> 5);
+		}
+	}
+}
+
+static inline int
+get_irq_num(int irq)
+{
+	if (cpu_is_omap1510()) {
+		return (((irq) < IH2_BASE) ? irq : irq - IH2_BASE);
+	} else {
+		return irq & 0x1f;
+	}
+}
+
+static void
+mask_irq(unsigned int irq)
+{
+	int level = get_level(irq);
+	int irq_num = get_irq_num(irq);
+	u32 mask = read_ih(level, IRQ_MIR) | (1 << irq_num);
+	write_ih(level, IRQ_MIR, mask);
+}
+
+static void
+ack_irq(unsigned int irq)
+{
+	int level = get_level(irq);
+
+	if (level > 1)
+		level = 1;
+	do {
+		write_ih(level, IRQ_CONTROL_REG, 0x1);
+		/*
+		 * REVISIT: So says the TRM:
+		 *	if (level) write_ih(0, ITR, 0);
+		 */
+	} while (level--);
+}
+
+void
+unmask_irq(unsigned int irq)
+{
+	int level = get_level(irq);
+	int irq_num = get_irq_num(irq);
+	u32 mask = read_ih(level, IRQ_MIR) & ~(1 << irq_num);
+
+	write_ih(level, IRQ_MIR, mask);
+}
+
+static void
+mask_ack_irq(unsigned int irq)
+{
+	mask_irq(irq);
+	ack_irq(irq);
+}
+
+static struct irqchip omap_normal_irq = {
+	.ack		= mask_ack_irq,
+	.mask		= mask_irq,
+	.unmask		= unmask_irq,
+};
+
+static void
+irq_priority(int irq, int fiq, int priority, int trigger)
+{
+	int level, irq_num;
+	unsigned long reg_value, reg_addr;
+
+	level = get_level(irq);
+	irq_num = get_irq_num(irq);
+	/* FIQ is only available on level 0 interrupts */
+	fiq = level ? 0 : (fiq & 0x1);
+	reg_value = (fiq) | ((priority & 0x1f) << 2) |
+		((trigger & 0x1) << 1);
+	reg_addr = (IRQ_ILR0 + irq_num * 0x4);
+	write_ih(level, reg_addr, reg_value);
+}
+
+void __init
+omap_init_irq(void)
+{
+	int i, irq_count, irq_bank_count = 0;
+	uint *trigger;
+
+	if (cpu_is_omap1510()) {
+		static uint trigger_1510[2] = {
+			0xb3febfff, 0xffbfffed
+		};
+		irq_bank_count = 2;
+		irq_count = 64;
+		trigger = trigger_1510;
+	}
+	if (cpu_is_omap1610()) {
+		static uint trigger_1610[5] = {
+			0xb3fefe8f, 0xfffff7ff, 0xffffffff
+		};
+		irq_bank_count = 5;
+		irq_count = 160;
+		trigger = trigger_1610;
+	}
+	if (cpu_is_omap730()) {
+		static uint trigger_730[] = {
+			0xb3f8e22f, 0xfdb9c1f2, 0x800040f3
+		};
+		irq_bank_count = 3;
+		irq_count = 96;
+		trigger = trigger_730;
+	}
+
+	for (i = 0; i < irq_bank_count; i++) {
+		/* Mask and clear all interrupts */
+		write_ih(i, IRQ_MIR, ~0x0);
+		write_ih(i, IRQ_ITR, 0x0);
+	}
+
+	/* Clear any pending interrupts */
+	write_ih(1, IRQ_CONTROL_REG, 3);
+	write_ih(0, IRQ_CONTROL_REG, 3);
+
+	for (i = 0; i < irq_count; i++) {
+		set_irq_chip(i, &omap_normal_irq);
+		set_irq_handler(i, do_level_IRQ);
+		set_irq_flags(i, IRQF_VALID);
+
+		irq_priority(i, 0, 0, trigger[get_level(i)] >> get_irq_num(i) & 1);
+	}
+	unmask_irq(INT_IH2_IRQ);
+}
diff -Nru a/arch/arm/mach-omap/leds-innovator.c b/arch/arm/mach-omap/leds-innovator.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/leds-innovator.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,103 @@
+/*
+ * linux/arch/arm/mach-omap/leds-innovator.c
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+
+#include "leds.h"
+
+
+#define LED_STATE_ENABLED	1
+#define LED_STATE_CLAIMED	2
+
+static unsigned int led_state;
+static unsigned int hw_led_state;
+
+void innovator_leds_event(led_event_t evt)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	switch (evt) {
+	case led_start:
+		hw_led_state = 0;
+		led_state = LED_STATE_ENABLED;
+		break;
+
+	case led_stop:
+		led_state &= ~LED_STATE_ENABLED;
+		hw_led_state = 0;
+		break;
+
+	case led_claim:
+		led_state |= LED_STATE_CLAIMED;
+		hw_led_state = 0;
+		break;
+
+	case led_release:
+		led_state &= ~LED_STATE_CLAIMED;
+		hw_led_state = 0;
+		break;
+
+#ifdef CONFIG_LEDS_TIMER
+	case led_timer:
+		if (!(led_state & LED_STATE_CLAIMED))
+			hw_led_state ^= 0;
+		break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+	case led_idle_start:
+		if (!(led_state & LED_STATE_CLAIMED))
+			hw_led_state |= 0;
+		break;
+
+	case led_idle_end:
+		if (!(led_state & LED_STATE_CLAIMED))
+			hw_led_state &= ~0;
+		break;
+#endif
+
+	case led_halted:
+		break;
+
+	case led_green_on:
+		if (led_state & LED_STATE_CLAIMED)
+			hw_led_state &= ~0;
+		break;
+
+	case led_green_off:
+		if (led_state & LED_STATE_CLAIMED)
+			hw_led_state |= 0;
+		break;
+
+	case led_amber_on:
+		break;
+
+	case led_amber_off:
+		break;
+
+	case led_red_on:
+		if (led_state & LED_STATE_CLAIMED)
+			hw_led_state &= ~0;
+		break;
+
+	case led_red_off:
+		if (led_state & LED_STATE_CLAIMED)
+			hw_led_state |= 0;
+		break;
+
+	default:
+		break;
+	}
+
+	if (led_state & LED_STATE_ENABLED)
+		;
+
+	local_irq_restore(flags);
+}
diff -Nru a/arch/arm/mach-omap/leds-perseus2.c b/arch/arm/mach-omap/leds-perseus2.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/leds-perseus2.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,103 @@
+/*
+ * linux/arch/arm/mach-omap/leds-perseus2.c
+ *
+ * Copyright 2003 by Texas Instruments Incorporated
+ *
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/version.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/system.h>
+#include <asm/arch/omap-perseus2.h>
+
+#include "leds.h"
+
+void perseus2_leds_event(led_event_t evt)
+{
+	unsigned long flags;
+	static unsigned long hw_led_state = 0;
+
+	local_irq_save(flags);
+
+	switch (evt) {
+	case led_start:
+		hw_led_state |= OMAP730_FPGA_LED_STARTSTOP;
+		break;
+
+	case led_stop:
+		hw_led_state &= ~OMAP730_FPGA_LED_STARTSTOP;
+		break;
+
+	case led_claim:
+		hw_led_state |= OMAP730_FPGA_LED_CLAIMRELEASE;
+		break;
+
+	case led_release:
+		hw_led_state &= ~OMAP730_FPGA_LED_CLAIMRELEASE;
+		break;
+
+#ifdef CONFIG_LEDS_TIMER
+	case led_timer:
+		/*
+		 * Toggle Timer LED
+		 */
+		if (hw_led_state & OMAP730_FPGA_LED_TIMER)
+			hw_led_state &= ~OMAP730_FPGA_LED_TIMER;
+		else
+			hw_led_state |= OMAP730_FPGA_LED_TIMER;
+		break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+	case led_idle_start:
+		hw_led_state |= OMAP730_FPGA_LED_IDLE;
+		break;
+
+	case led_idle_end:
+		hw_led_state &= ~OMAP730_FPGA_LED_IDLE;
+		break;
+#endif
+
+	case led_halted:
+		if (hw_led_state & OMAP730_FPGA_LED_HALTED)
+			hw_led_state &= ~OMAP730_FPGA_LED_HALTED;
+		else
+			hw_led_state |= OMAP730_FPGA_LED_HALTED;
+		break;
+
+	case led_green_on:
+		break;
+
+	case led_green_off:
+		break;
+
+	case led_amber_on:
+		break;
+
+	case led_amber_off:
+		break;
+
+	case led_red_on:
+		break;
+
+	case led_red_off:
+		break;
+
+	default:
+		break;
+	}
+
+
+	/*
+	 *  Actually burn the LEDs
+	 */
+	__raw_writew(~hw_led_state & 0xffff, OMAP730_FPGA_LEDS);
+
+	local_irq_restore(flags);
+}
diff -Nru a/arch/arm/mach-omap/leds.c b/arch/arm/mach-omap/leds.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/leds.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-omap/leds.c
+ *
+ * OMAP LEDs dispatcher
+ */
+#include <linux/init.h>
+
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include "leds.h"
+
+static int __init
+omap1510_leds_init(void)
+{
+	if (machine_is_innovator())
+		leds_event = innovator_leds_event;
+
+	leds_event(led_start);
+	return 0;
+}
+
+__initcall(omap1510_leds_init);
diff -Nru a/arch/arm/mach-omap/leds.h b/arch/arm/mach-omap/leds.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/leds.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,2 @@
+extern void innovator_leds_event(led_event_t evt);
+extern void perseus2_leds_event(led_event_t evt);
diff -Nru a/arch/arm/mach-omap/mux.c b/arch/arm/mach-omap/mux.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/mux.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,124 @@
+/*
+ * linux/arch/arm/mach-omap/mux.c
+ *
+ * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+
+#define __MUX_C__
+#include <asm/arch/mux.h>
+
+static spinlock_t mux_spin_lock = SPIN_LOCK_UNLOCKED;
+
+/*
+ * Sets the Omap MUX and PULL_DWN registers based on the table
+ */
+int omap_cfg_reg(const reg_cfg_t reg_cfg)
+{
+#ifdef CONFIG_OMAP_MUX
+	unsigned long flags;
+	reg_cfg_set *cfg;
+	unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
+		pull_orig = 0, pull = 0;
+
+	cfg = &reg_cfg_table[reg_cfg];
+
+	/*
+	 * We do a pretty long section here with lock on, but pin muxing
+	 * should only happen on driver init for each driver, so it's not time
+	 * critical.
+	 */
+	spin_lock_irqsave(&mux_spin_lock, flags);
+
+	/* Check the mux register in question */
+	if (cfg->mux_reg) {
+		reg_orig = __raw_readl(cfg->mux_reg);
+
+		/* The mux registers always seem to be 3 bits long */
+		reg = reg_orig & ~(0x7 << cfg->mask_offset);
+
+		reg |= (cfg->mask << cfg->mask_offset);
+
+		__raw_writel(reg, cfg->mux_reg);
+	}
+
+	/* Check for pull up or pull down selection on 1610 */
+	if (!cpu_is_omap1510()) {
+		if (cfg->pu_pd_reg && cfg->pull_val) {
+			pu_pd_orig = __raw_readl(cfg->pu_pd_reg);
+			if (cfg->pu_pd_val) {
+				/* Use pull up */
+				pu_pd = pu_pd_orig | (1 << cfg->pull_bit);
+			} else {
+				/* Use pull down */
+				pu_pd = pu_pd_orig & ~(1 << cfg->pull_bit);
+			}
+			__raw_writel(pu_pd, cfg->pu_pd_reg);
+		}
+	}
+
+	/* Check for an associated pull down register */
+	if (cfg->pull_reg) {
+		pull_orig = __raw_readl(cfg->pull_reg);
+
+		if (cfg->pull_val) {
+			/* Low bit = pull enabled */
+			pull = pull_orig & ~(1 << cfg->pull_bit);
+		} else {
+			/* High bit = pull disabled */
+			pull = pull_orig | (1 << cfg->pull_bit);
+		}
+
+		__raw_writel(pull, cfg->pull_reg);
+	}
+
+#ifdef CONFIG_OMAP_MUX_DEBUG
+	if (cfg->debug) {
+		printk("Omap: Setting register %s\n", cfg->name);
+		printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+		       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
+
+		if (!cpu_is_omap1510()) {
+			if (cfg->pu_pd_reg && cfg->pull_val) {
+				printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+				       cfg->pu_pd_name, cfg->pu_pd_reg,
+				       pu_pd_orig, pu_pd);
+			}
+		}
+
+		printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+		       cfg->pull_name, cfg->pull_reg, pull_orig, pull);
+	}
+#endif
+
+	spin_unlock_irqrestore(&mux_spin_lock, flags);
+
+#endif
+	return 0;
+}
+
+EXPORT_SYMBOL(omap_cfg_reg);
diff -Nru a/arch/arm/mach-omap/ocpi.c b/arch/arm/mach-omap/ocpi.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/ocpi.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,116 @@
+/*
+ * linux/arch/arm/mach-omap/ocpi.c
+ *
+ * Minimal OCP bus support for OMAP-1610
+ *
+ * Copyright (C) 2003 - 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define OCPI_BASE		0xfffec320
+#define OCPI_FAULT		(OCPI_BASE + 0x00)
+#define OCPI_CMD_FAULT		(OCPI_BASE + 0x04)
+#define OCPI_SINT0		(OCPI_BASE + 0x08)
+#define OCPI_TABORT		(OCPI_BASE + 0x0c)
+#define OCPI_SINT1		(OCPI_BASE + 0x10)
+#define OCPI_PROT		(OCPI_BASE + 0x14)
+#define OCPI_SEC		(OCPI_BASE + 0x18)
+
+#define EN_OCPI_CK		(1 << 0)
+#define IDLOCPI_ARM		(1 << 1)
+
+/* USB OHCI OCPI access error registers */
+#define HOSTUEADDR	0xfffba0e0
+#define HOSTUESTATUS	0xfffba0e4
+
+/*
+ * Enables device access to OMAP buses via the OCPI bridge
+ * FIXME: Add locking
+ */
+int ocpi_enable(void)
+{
+	unsigned int val;
+
+	/* Make sure there's clock for OCPI */
+	val = __raw_readl(ARM_IDLECT3);
+	val |= EN_OCPI_CK;
+	val &= ~IDLOCPI_ARM;
+	__raw_writel(val, ARM_IDLECT3);
+
+	/* Enable access for OHCI in OCPI */
+	val = __raw_readl(OCPI_PROT);
+	val &= ~0xff;
+	//val &= (1 << 0);	/* Allow access only to EMIFS */
+	__raw_writel(val, OCPI_PROT);
+
+	val = __raw_readl(OCPI_SEC);
+	val &= ~0xff;
+	__raw_writel(val, OCPI_SEC);
+
+	val = __raw_readl(OCPI_SEC);
+	val |= 0;
+	__raw_writel(val, OCPI_SEC);
+
+	val = __raw_readl(OCPI_SINT0);
+	val |= 0;
+	__raw_writel(val, OCPI_SINT1);
+
+	return 0;
+}
+EXPORT_SYMBOL(ocpi_enable);
+
+int ocpi_status(void)
+{
+	printk("OCPI: addr: 0x%08x cmd: 0x%08x\n"
+	       "      ohci-addr: 0x%08x ohci-status: 0x%08x\n",
+	       __raw_readl(OCPI_FAULT), __raw_readl(OCPI_CMD_FAULT),
+	       __raw_readl(HOSTUEADDR), __raw_readl(HOSTUESTATUS));
+
+	return 1;
+}
+EXPORT_SYMBOL(ocpi_status);
+
+static int __init omap_ocpi_init(void)
+{
+	ocpi_enable();
+	printk("OMAP OCPI interconnect driver loaded\n");
+
+	return 0;
+}
+
+static void __exit omap_ocpi_exit(void)
+{
+	/* FIXME: Disable OCPI */
+}
+
+MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
+MODULE_DESCRIPTION("OMAP OCPI bus controller module");
+MODULE_LICENSE("GPL");
+module_init(omap_ocpi_init);
+module_exit(omap_ocpi_exit);
diff -Nru a/arch/arm/mach-omap/omap-generic.c b/arch/arm/mach-omap/omap-generic.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/omap-generic.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,77 @@
+/*
+ * linux/arch/arm/mach-omap/generic.c
+ *
+ * Modified from innovator.c
+ *
+ * Code for generic OMAP board. Should work on many OMAP systems where
+ * the device drivers take care of all the necessary hardware initialization.
+ * Do not put any board specific code to this file; create a new machine
+ * type if you need custom low-level initializations.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/clocks.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "common.h"
+
+static void __init omap_generic_init_irq(void)
+{
+	omap_init_irq();
+}
+
+/*
+ * Muxes the serial ports on
+ */
+static void __init omap_early_serial_init(void)
+{
+	omap_cfg_reg(UART1_TX);
+	omap_cfg_reg(UART1_RTS);
+
+	omap_cfg_reg(UART2_TX);
+	omap_cfg_reg(UART2_RTS);
+
+	omap_cfg_reg(UART3_TX);
+	omap_cfg_reg(UART3_RX);
+}
+
+static void __init omap_generic_init(void)
+{
+	if (!machine_is_omap_generic())
+		return;
+
+	/*
+	 * Make sure the serial ports are muxed on at this point.
+	 * You have to mux them off in device drivers later on
+	 * if not needed.
+	 */
+	if (cpu_is_omap1510()) {
+		omap_early_serial_init();
+	}
+}
+
+static void __init omap_generic_map_io(void)
+{
+	omap_map_io();
+}
+
+MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610")
+	MAINTAINER("Tony Lindgren <tony@atomide.com>")
+	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
+	BOOT_PARAMS(0x10000100)
+	MAPIO(omap_generic_map_io)
+	INITIRQ(omap_generic_init_irq)
+	INIT_MACHINE(omap_generic_init)
+MACHINE_END
diff -Nru a/arch/arm/mach-omap/omap-perseus2.c b/arch/arm/mach-omap/omap-perseus2.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-omap/omap-perseus2.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,116 @@
+/*
+ * linux/arch/arm/mach-omap/omap-perseus2.c
+ *
+ * Modified from omap-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/clocks.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mux.h>
+
+#include <asm/arch/omap-perseus2.h>
+
+#include "common.h"
+
+void omap_perseus2_init_irq(void)
+{
+	omap_init_irq();
+}
+
+static struct resource smc91x_resources[] = {
+	[0] = {
+		.start	= OMAP730_FPGA_ETHR_START,	/* Physical */
+		.end	= OMAP730_FPGA_ETHR_START + SZ_4K,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= 0,
+		.end	= 0,
+		.flags	= INT_ETHER,
+	},
+};
+
+static struct platform_device smc91x_device = {
+	.name		= "smc91x",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smc91x_resources),
+	.resource	= smc91x_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&smc91x_device,
+};
+
+static void __init omap_perseus2_init(void)
+{
+	if (!machine_is_omap_perseus2())
+		return;
+
+	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+/* Only FPGA needs to be mapped here. All others are done with ioremap */
+static struct map_desc omap_perseus2_io_desc[] __initdata = {
+	{OMAP730_FPGA_BASE, OMAP730_FPGA_START, OMAP730_FPGA_SIZE,
+	 MT_DEVICE},
+};
+
+static void __init omap_perseus2_map_io(void)
+{
+	omap_map_io();
+	iotable_init(omap_perseus2_io_desc,
+		     ARRAY_SIZE(omap_perseus2_io_desc));
+
+	/* Early, board-dependent init */
+
+	/*
+	 * Hold GSM Reset until needed
+	 */
+	*DSP_M_CTL &= ~1;
+
+	/*
+	 * UARTs -> done automagically by 8250 driver
+	 */
+
+	/*
+	 * CSx timings, GPIO Mux ... setup
+	 */
+
+	/* Flash: CS0 timings setup */
+	*((volatile __u32 *) OMAP_FLASH_CFG_0) = 0x0000fff3;
+	*((volatile __u32 *) OMAP_FLASH_ACFG_0) = 0x00000088;
+
+	/*
+	 * Ethernet support trough the debug board
+	 * CS1 timings setup
+	 */
+	*((volatile __u32 *) OMAP_FLASH_CFG_1) = 0x0000fff3;
+	*((volatile __u32 *) OMAP_FLASH_ACFG_1) = 0x00000000;
+
+	/*
+	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+	 * It is used as the Ethernet controller interrupt
+	 */
+	*((volatile __u32 *) PERSEUS2_IO_CONF_9) &= 0x1FFFFFFF;
+}
+
+MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
+	MAINTAINER("Kevin Hilman <k-hilman@ti.com>")
+	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
+	BOOT_PARAMS(0x10000100)
+	MAPIO(omap_perseus2_map_io)
+	INITIRQ(omap_perseus2_init_irq)
+	INIT_MACHINE(omap_perseus2_init)
+MACHINE_END
diff -Nru a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/Kconfig	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,25 @@
+menu "S3C2410 Implementations"
+
+config ARCH_BAST
+	bool "Simtec Electronics BAST (EB2410ITX)"
+	depends on ARCH_S3C2410
+	help
+	  Say Y here if you are using the Simtec Electronics EB2410ITX
+	  development board (also known as BAST)
+
+	  Product page: <http://www.simtec.co.uk/products/EB2410ITX/>.
+
+config ARCH_H1940
+	bool "IPAQ H1940"
+	depends on ARCH_S3C2410
+	help
+	  Say Y here if you are using the HP IPAQ H1940
+	  <http://www.handhelds.org/projects/h1940.html>.
+
+config MACH_VR1000
+	bool "Simtec VR1000"
+	depends on ARCH_S3C2410
+	help
+	  Say Y here if you are using the Simtec VR1000 board.
+
+endmenu
diff -Nru a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/Makefile	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,18 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y			:= s3c2410.o irq.o
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+obj-$(CONFIG_ARCH_BAST)    += mach-bast.o
+obj-$(CONFIG_MACH_H1940)   += mach-h1940.o
+obj-$(CONFIG_ARCH_H1940)   += mach-h1940.o
+obj-$(CONFIG_MACH_VR1000)  += mach-vr1000.o
+
+#obj-$(CONFIG_PCI)	+=$(pci-y)
+#obj-$(CONFIG_LEDS)	+=$(leds-y)
diff -Nru a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/bast-irq.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,132 @@
+/* linux/arch/arm/mach-s3c2410/bast-irq.c
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.simtec.co.uk/products/EB2410ITX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Modifications:
+ *     08-Jan-2003 BJD  Moved from central IRQ code
+ */
+
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/irq.h>
+#include <asm/hardware/s3c2410/irq.h>
+
+#if 0
+#include <asm/debug-ll.h>
+#endif
+
+#define irqdbf(x...)
+#define irqdbf2(x...)
+
+
+/* handle PC104 ISA interrupts from the system CPLD */
+
+/* table of ISA irq nos to the relevant mask... zero means
+ * the irq is not implemented
+*/
+static unsigned char bast_pc104_irqmasks[] = {
+	0,   /* 0 */
+	0,   /* 1 */
+	0,   /* 2 */
+	1,   /* 3 */
+	0,   /* 4 */
+	2,   /* 5 */
+	0,   /* 6 */
+	4,   /* 7 */
+	0,   /* 8 */
+	0,   /* 9 */
+	8,   /* 10 */
+	0,   /* 11 */
+	0,   /* 12 */
+	0,   /* 13 */
+	0,   /* 14 */
+	0,   /* 15 */
+};
+
+static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
+
+static void
+bast_pc104_mask(unsigned int irqno)
+{
+	unsigned long temp;
+
+	temp = __raw_readb(BAST_VA_PC104_IRQMASK);
+	temp &= ~bast_pc104_irqmasks[irqno];
+	__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
+
+	if (temp == 0)
+		bast_extint_mask(IRQ_ISA);
+}
+
+static void
+bast_pc104_ack(unsigned int irqno)
+{
+	bast_extint_ack(IRQ_ISA);
+}
+
+static void
+bast_pc104_unmask(unsigned int irqno)
+{
+	unsigned long temp;
+
+	temp = __raw_readb(BAST_VA_PC104_IRQMASK);
+	temp |= bast_pc104_irqmasks[irqno];
+	__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
+
+	bast_extint_unmask(IRQ_ISA);
+}
+
+static struct bast_pc104_chip = {
+	.mask	     = bast_pc104_mask,
+	.unmask	     = bast_pc104_unmask,
+	.ack	     = bast_pc104_ack
+};
+
+static void
+bast_irq_pc104_demux(unsigned int irq,
+		     struct irqdesc *desc,
+		     struct pt_regs *regs)
+{
+	unsigned int stat;
+	unsigned int irqno;
+	int i;
+
+	stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf;
+
+	for (i = 0; i < 4 && stat != 0; i++) {
+		if (stat & 1) {
+			irqno = bast_pc104_irqs[i];
+			desc = irq_desc + irqno;
+
+			desc->handle(irqno, desc, regs);
+		}
+
+		stat >>= 1;
+	}
+}
diff -Nru a/arch/arm/mach-s3c2410/bast.h b/arch/arm/mach-s3c2410/bast.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/bast.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,2 @@
+
+extern void bast_init_irq(void);
diff -Nru a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/irq.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,598 @@
+/* linux/arch/arm/mach-s3c2410/irq.c
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/irq.h>
+
+#include <asm/arch/regs-irq.h>
+#include <asm/arch/regs-lcd.h>
+
+#if 0
+#include <asm/debug-ll.h>
+#endif
+
+#define irqdbf(x...)
+#define irqdbf2(x...)
+
+static void
+s3c_irq_mask(unsigned int irqno)
+{
+	unsigned long mask;
+
+	irqno -= IRQ_EINT0;
+
+	mask = __raw_readl(S3C2410_INTMSK);
+	mask |= 1UL << irqno;
+	__raw_writel(mask, S3C2410_INTMSK);
+}
+
+static inline void
+s3c_irq_ack(unsigned int irqno)
+{
+	unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+
+	__raw_writel(bitval, S3C2410_SRCPND);
+	__raw_writel(bitval, S3C2410_INTPND);
+}
+
+static inline void
+s3c_irq_maskack(unsigned int irqno)
+{
+	unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
+	unsigned long mask;
+
+	mask = __raw_readl(S3C2410_INTMSK);
+	__raw_writel(mask|bitval, S3C2410_INTMSK);
+
+	__raw_writel(bitval, S3C2410_SRCPND);
+	__raw_writel(bitval, S3C2410_INTPND);
+}
+
+
+static void
+s3c_irq_unmask(unsigned int irqno)
+{
+	unsigned long mask;
+
+	if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
+		irqdbf2("s3c_irq_unmask %d\n", irqno);
+
+	irqno -= IRQ_EINT0;
+
+	mask = __raw_readl(S3C2410_INTMSK);
+	mask &= ~(1UL << irqno);
+	__raw_writel(mask, S3C2410_INTMSK);
+}
+
+static struct irqchip s3c_irq_level_chip = {
+	.ack	   = s3c_irq_maskack,
+	.mask	   = s3c_irq_mask,
+	.unmask	   = s3c_irq_unmask
+};
+
+static struct irqchip s3c_irq_chip = {
+	.ack	   = s3c_irq_ack,
+	.mask	   = s3c_irq_mask,
+	.unmask	   = s3c_irq_unmask
+};
+
+/* S3C2410_EINTMASK
+ * S3C2410_EINTPEND
+ */
+
+#define EXTINT_OFF (IRQ_EINT4 - 4)
+
+static void
+s3c_irqext_mask(unsigned int irqno)
+{
+	unsigned long mask;
+
+	irqno -= EXTINT_OFF;
+
+	mask = __raw_readl(S3C2410_EINTMASK);
+	mask |= ( 1UL << irqno);
+	__raw_writel(mask, S3C2410_EINTMASK);
+
+	if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
+		/* check to see if all need masking */
+
+		if ((mask & (0xf << 4)) == (0xf << 4)) {
+			/* all masked, mask the parent */
+			s3c_irq_mask(IRQ_EINT4t7);
+		}
+	} else {
+		/* todo: the same check as above for the rest of the irq regs...*/
+
+	}
+}
+
+static void
+s3c_irqext_ack(unsigned int irqno)
+{
+	unsigned long req;
+	unsigned long bit;
+	unsigned long mask;
+
+	bit = 1UL << (irqno - EXTINT_OFF);
+
+
+	mask = __raw_readl(S3C2410_EINTMASK);
+
+	__raw_writel(bit, S3C2410_EINTPEND);
+
+	req = __raw_readl(S3C2410_EINTPEND);
+	req &= ~mask;
+
+	/* not sure if we should be acking the parent irq... */
+
+	if (irqno <= IRQ_EINT7 ) {
+		if ((req & 0xf0) == 0)
+			s3c_irq_ack(IRQ_EINT4t7);
+	} else {
+		if ((req >> 8) == 0)
+			s3c_irq_ack(IRQ_EINT8t23);
+	}
+}
+
+static void
+s3c_irqext_unmask(unsigned int irqno)
+{
+	unsigned long mask;
+
+	irqno -= EXTINT_OFF;
+
+	mask = __raw_readl(S3C2410_EINTMASK);
+	mask &= ~( 1UL << irqno);
+	__raw_writel(mask, S3C2410_EINTMASK);
+
+	s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
+}
+
+/* todo - put type handler in here */
+
+static int
+s3c_irqext_type(unsigned int irq, unsigned int type)
+{
+	irqdbf("s3c_irqext_type: called for irq %d, type %d\n", irq, type);
+
+	return 0;
+}
+
+static struct irqchip s3c_irqext_chip = {
+	.mask	    = s3c_irqext_mask,
+	.unmask	    = s3c_irqext_unmask,
+	.ack	    = s3c_irqext_ack,
+	.type	    = s3c_irqext_type
+};
+
+/* mask values for the parent registers for each of the interrupt types */
+
+#define INTMSK_UART0	 (1UL << (IRQ_UART0 - IRQ_EINT0))
+#define INTMSK_UART1	 (1UL << (IRQ_UART1 - IRQ_EINT0))
+#define INTMSK_UART2	 (1UL << (IRQ_UART2 - IRQ_EINT0))
+#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
+#define INTMSK_LCD	 (1UL << (IRQ_LCD - IRQ_EINT0))
+
+static inline void
+s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
+		int subcheck)
+{
+	unsigned long mask;
+	unsigned long submask;
+
+	submask = __raw_readl(S3C2410_INTSUBMSK);
+	mask = __raw_readl(S3C2410_INTMSK);
+
+	submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
+
+	/* check to see if we need to mask the parent IRQ */
+
+	if ((submask  & subcheck) == subcheck) {
+		__raw_writel(mask | parentbit, S3C2410_INTMSK);
+	}
+
+	/* write back masks */
+	__raw_writel(submask, S3C2410_INTSUBMSK);
+
+}
+
+static inline void
+s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
+{
+	unsigned long mask;
+	unsigned long submask;
+
+	submask = __raw_readl(S3C2410_INTSUBMSK);
+	mask = __raw_readl(S3C2410_INTMSK);
+
+	submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
+	mask &= ~parentbit;
+
+	/* write back masks */
+	__raw_writel(submask, S3C2410_INTSUBMSK);
+	__raw_writel(mask, S3C2410_INTMSK);
+}
+
+
+static inline void
+s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
+{
+	unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
+
+	s3c_irqsub_mask(irqno, parentmask, group);
+
+	__raw_writel(bit, S3C2410_SUBSRCPND);
+
+	/* only ack parent if we've got all the irqs (seems we must
+	 * ack, all and hope that the irq system retriggers ok when
+	 * the interrupt goes off again)
+	 */
+
+	if (1) {
+		__raw_writel(parentmask, S3C2410_SRCPND);
+		__raw_writel(parentmask, S3C2410_INTPND);
+	}
+}
+
+
+/* UART0 */
+
+static void
+s3c_irq_uart0_mask(unsigned int irqno)
+{
+	s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
+}
+
+static void
+s3c_irq_uart0_unmask(unsigned int irqno)
+{
+	s3c_irqsub_unmask(irqno, INTMSK_UART0);
+}
+
+static void
+s3c_irq_uart0_ack(unsigned int irqno)
+{
+	s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
+}
+
+static struct irqchip s3c_irq_uart0 = {
+	.mask	    = s3c_irq_uart0_mask,
+	.unmask	    = s3c_irq_uart0_unmask,
+	.ack	    = s3c_irq_uart0_ack,
+};
+
+/* UART1 */
+
+static void
+s3c_irq_uart1_mask(unsigned int irqno)
+{
+	s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
+}
+
+static void
+s3c_irq_uart1_unmask(unsigned int irqno)
+{
+	s3c_irqsub_unmask(irqno, INTMSK_UART1);
+}
+
+static void
+s3c_irq_uart1_ack(unsigned int irqno)
+{
+	s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
+}
+
+static struct irqchip s3c_irq_uart1 = {
+	.mask	    = s3c_irq_uart1_mask,
+	.unmask	    = s3c_irq_uart1_unmask,
+	.ack	    = s3c_irq_uart1_ack,
+};
+
+/* UART2 */
+
+static void
+s3c_irq_uart2_mask(unsigned int irqno)
+{
+	s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
+}
+
+static void
+s3c_irq_uart2_unmask(unsigned int irqno)
+{
+	s3c_irqsub_unmask(irqno, INTMSK_UART2);
+}
+
+static void
+s3c_irq_uart2_ack(unsigned int irqno)
+{
+	s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
+}
+
+static struct irqchip s3c_irq_uart2 = {
+	.mask	    = s3c_irq_uart2_mask,
+	.unmask	    = s3c_irq_uart2_unmask,
+	.ack	    = s3c_irq_uart2_ack,
+};
+
+/* ADC and Touchscreen */
+
+static void
+s3c_irq_adc_mask(unsigned int irqno)
+{
+	s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
+}
+
+static void
+s3c_irq_adc_unmask(unsigned int irqno)
+{
+	s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
+}
+
+static void
+s3c_irq_adc_ack(unsigned int irqno)
+{
+	s3c_irqsub_maskack(irqno, INTMSK_ADCPARENT, 3 << 9);
+}
+
+static struct irqchip s3c_irq_adc = {
+	.mask	    = s3c_irq_adc_mask,
+	.unmask	    = s3c_irq_adc_unmask,
+	.ack	    = s3c_irq_adc_ack,
+};
+
+#if 0
+/* LCD (todo) */
+
+static void
+s3c_irq_lcd_mask(unsigned int irqno)
+{
+
+}
+
+static void
+s3c_irq_lcd_unmask(unsigned int irqno)
+{
+
+}
+
+static void
+s3c_irq_lcd_ack(unsigned int irqno)
+{
+
+}
+
+static struct irqchip s3c_irq_lcd = {
+	.mask	    = s3c_irq_lcd_mask,
+	.unmask	    = s3c_irq_lcd_unmask,
+	.ack	    = s3c_irq_lcd_ack,
+};
+#endif
+
+/* irq demux */
+
+
+static void s3c_irq_demux_uart(unsigned int start,
+			       struct pt_regs *regs)
+{
+	unsigned int subsrc, submsk;
+	unsigned int offset = start - IRQ_S3CUART_RX0;
+	struct irqdesc *desc;
+
+	/* read the current pending interrupts, and the mask
+	 * for what it is available */
+
+	subsrc = __raw_readl(S3C2410_SUBSRCPND);
+	submsk = __raw_readl(S3C2410_INTSUBMSK);
+
+	irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
+		start, offset, subsrc, submsk);
+
+	subsrc &= ~submsk;
+	subsrc >>= offset;
+	subsrc &= 7;
+
+	if (subsrc != 0) {
+		desc = irq_desc + start;
+
+		if (subsrc & 1)
+			desc->handle(start, desc, regs);
+
+		desc++;
+
+		if (subsrc & 2)
+			desc->handle(start+1, desc, regs);
+
+		desc++;
+
+		if (subsrc & 4)
+			desc->handle(start+2, desc, regs);
+	}
+}
+
+/* uart demux entry points */
+
+static void
+s3c_irq_demux_uart0(unsigned int irq,
+		    struct irqdesc *desc,
+		    struct pt_regs *regs)
+{
+	irq = irq;
+	s3c_irq_demux_uart(IRQ_S3CUART_RX0, regs);
+}
+
+static void
+s3c_irq_demux_uart1(unsigned int irq,
+		    struct irqdesc *desc,
+		    struct pt_regs *regs)
+{
+	irq = irq;
+	s3c_irq_demux_uart(IRQ_S3CUART_RX1, regs);
+}
+
+static void
+s3c_irq_demux_uart2(unsigned int irq,
+		    struct irqdesc *desc,
+		    struct pt_regs *regs)
+{
+	irq = irq;
+	s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
+}
+
+
+
+void __init s3c2410_init_irq(void)
+{
+	unsigned long pend;
+	int irqno;
+	int i;
+
+	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
+
+	/* first, clear all interrupts pending... */
+
+	for (i = 0; i < 4; i++) {
+		pend = __raw_readl(S3C2410_EINTPEND);
+		if (pend == 0)
+			break;
+		__raw_writel(pend, S3C2410_EINTPEND);
+		printk("irq: clearing pending ext status %08x\n", (int)pend);
+	}
+
+	for (i = 0; i < 4; i++) {
+		pend = __raw_readl(S3C2410_INTPND);
+		if (pend == 0)
+			break;
+		__raw_writel(pend, S3C2410_SRCPND);
+		__raw_writel(pend, S3C2410_INTPND);
+		printk("irq: clearing pending status %08x\n", (int)pend);
+	}
+
+	for (i = 0; i < 4; i++) {
+		pend = __raw_readl(S3C2410_SUBSRCPND);
+
+		if (pend == 0)
+			break;
+
+		printk("irq: clearing subpending status %08x\n", (int)pend);
+		__raw_writel(pend, S3C2410_SUBSRCPND);
+	}
+
+	/* register the main interrupts */
+
+	irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
+
+	for (irqno = IRQ_EINT0; irqno < IRQ_ADCPARENT; irqno++) {
+		/* set all the s3c2410 internal irqs */
+
+		switch (irqno) {
+
+		case IRQ_EINT4t7:
+		case IRQ_EINT8t23:
+			/* these are already dealt with, so should never
+			 * appear */
+			break;
+
+			/* deal with the special IRQs (cascaded) */
+
+		case IRQ_UART0:
+		case IRQ_UART1:
+		case IRQ_UART2:
+		case IRQ_LCD:
+		case IRQ_ADCPARENT:
+			set_irq_chip(irqno, &s3c_irq_level_chip);
+			set_irq_handler(irqno, do_level_IRQ);
+			break;
+
+		case IRQ_RESERVED6:
+		case IRQ_RESERVED24:
+			/* no IRQ here */
+			break;
+
+		default:
+			//irqdbf("registering irq %d (s3c irq)\n", irqno);
+			set_irq_chip(irqno, &s3c_irq_chip);
+			set_irq_handler(irqno, do_edge_IRQ);
+			set_irq_flags(irqno, IRQF_VALID);
+		}
+	}
+
+	/* setup the cascade irq handlers */
+
+	set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
+	set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
+	set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
+	//set_irq_chained_handler(IRQ_LCD, s3c_irq_demux_);
+	//set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_);
+
+
+	/* external interrupts */
+
+	for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
+		irqdbf("registering irq %d (extended s3c irq)\n", irqno);
+		set_irq_chip(irqno, &s3c_irqext_chip);
+		set_irq_handler(irqno, do_edge_IRQ);
+		set_irq_flags(irqno, IRQF_VALID);
+	}
+
+	/* register the uart interrupts */
+
+	irqdbf("s3c2410: registering external interrupts\n");
+
+	for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
+		irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
+		set_irq_chip(irqno, &s3c_irq_uart0);
+		set_irq_handler(irqno, do_level_IRQ);
+		set_irq_flags(irqno, IRQF_VALID);
+	}
+
+	for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
+		irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
+		set_irq_chip(irqno, &s3c_irq_uart1);
+		set_irq_handler(irqno, do_level_IRQ);
+		set_irq_flags(irqno, IRQF_VALID);
+	}
+
+	for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
+		irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
+		set_irq_chip(irqno, &s3c_irq_uart2);
+		set_irq_handler(irqno, do_level_IRQ);
+		set_irq_flags(irqno, IRQF_VALID);
+	}
+
+	for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
+		irqdbf("registering irq %d (s3c adc irq)\n", irqno);
+		set_irq_chip(irqno, &s3c_irq_adc);
+		set_irq_handler(irqno, do_edge_IRQ);
+		set_irq_flags(irqno, IRQF_VALID);
+	}
+
+	irqdbf("s3c2410: registered interrupt handlers\n");
+}
diff -Nru a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/mach-bast.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,194 @@
+/* linux/arch/arm/mach-s3c2410/mach-bast.c
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.simtec.co.uk/products/EB2410ITX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *     16-May-2003 BJD  Created initial version
+ *     16-Aug-2003 BJD  Fixed header files and copyright, added URL
+ *     05-Sep-2003 BJD  Moved to v2.6 kernel
+ *     06-Jan-2003 BJD  Updates for <arch/map.h>
+ *     18-Jan-2003 BJD  Added serial port configuration
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/bast-map.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+//#include <asm/debug-ll.h>
+#include <asm/arch/regs-serial.h>
+
+#include "s3c2410.h"
+
+/* macros for virtual address mods for the io space entries */
+#define VA_C5(item) ((item) + BAST_VAM_CS5)
+#define VA_C4(item) ((item) + BAST_VAM_CS4)
+#define VA_C3(item) ((item) + BAST_VAM_CS3)
+#define VA_C2(item) ((item) + BAST_VAM_CS2)
+
+/* macros to modify the physical addresses for io space */
+
+#define PA_CS2(item) ((item) + S3C2410_CS2)
+#define PA_CS3(item) ((item) + S3C2410_CS3)
+#define PA_CS4(item) ((item) + S3C2410_CS4)
+#define PA_CS5(item) ((item) + S3C2410_CS5)
+
+static struct map_desc bast_iodesc[] __initdata = {
+  /* ISA IO areas */
+
+  { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO),	   SZ_16M, MT_DEVICE },
+  { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO),	   SZ_16M, MT_DEVICE },
+
+  /* we could possibly compress the next set down into a set of smaller tables
+   * pagetables, but that would mean using an L2 section, and it still means
+   * we cannot actually feed the same register to an LDR due to 16K spacing
+   */
+
+  /* bast CPLD control registers, and external interrupt controls */
+  { BAST_VA_CTRL1, BAST_PA_CTRL1,		   SZ_1M, MT_DEVICE },
+  { BAST_VA_CTRL2, BAST_PA_CTRL2,		   SZ_1M, MT_DEVICE },
+  { BAST_VA_CTRL3, BAST_PA_CTRL3,		   SZ_1M, MT_DEVICE },
+  { BAST_VA_CTRL4, BAST_PA_CTRL4,		   SZ_1M, MT_DEVICE },
+
+  /* PC104 IRQ mux */
+  { BAST_VA_PC104_IRQREQ,  BAST_PA_PC104_IRQREQ,   SZ_1M, MT_DEVICE },
+  { BAST_VA_PC104_IRQRAW,  BAST_PA_PC104_IRQRAW,   SZ_1M, MT_DEVICE },
+  { BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK,  SZ_1M, MT_DEVICE },
+
+  /* onboard 8bit lcd port */
+
+  { BAST_VA_LCD_RCMD1,  BAST_PA_LCD_RCMD1,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_WCMD1,  BAST_PA_LCD_WCMD1,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_RDATA1, BAST_PA_LCD_RDATA1,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_WDATA1, BAST_PA_LCD_WDATA1,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_RCMD2,  BAST_PA_LCD_RCMD2,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_WCMD2,  BAST_PA_LCD_WCMD2,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_RDATA2, BAST_PA_LCD_RDATA2,	   SZ_1M, MT_DEVICE },
+  { BAST_VA_LCD_WDATA2, BAST_PA_LCD_WDATA2,	   SZ_1M, MT_DEVICE },
+
+  /* peripheral space... one for each of fast/slow/byte/16bit */
+  /* note, ide is only decoded in word space, even though some registers
+   * are only 8bit */
+
+  /* slow, byte */
+  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
+  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
+  { VA_C2(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET),  SZ_1M,  MT_DEVICE },
+  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
+  { VA_C2(BAST_VA_DM9000),  PA_CS2(BAST_PA_DM9000),   SZ_1M,  MT_DEVICE },
+  { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
+  { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
+  { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+
+  /* slow, word */
+  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
+  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
+  { VA_C3(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET),  SZ_1M,  MT_DEVICE },
+  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
+  { VA_C3(BAST_VA_DM9000),  PA_CS3(BAST_PA_DM9000),   SZ_1M,  MT_DEVICE },
+  { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
+  { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
+  { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+
+  /* fast, byte */
+  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
+  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
+  { VA_C4(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET),  SZ_1M,  MT_DEVICE },
+  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
+  { VA_C4(BAST_VA_DM9000),  PA_CS4(BAST_PA_DM9000),   SZ_1M,  MT_DEVICE },
+  { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
+  { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
+  { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+
+  /* fast, word */
+  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
+  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
+  { VA_C5(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET),  SZ_1M,  MT_DEVICE },
+  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
+  { VA_C5(BAST_VA_DM9000),  PA_CS5(BAST_PA_DM9000),   SZ_1M,  MT_DEVICE },
+  { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
+  { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
+  { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+};
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+/* base baud rate for all our UARTs */
+static unsigned long bast_serial_clock = 24*1000*1000;
+
+static struct s3c2410_uartcfg bast_uartcfgs[] = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.clock	     = &bast_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.clock	     = &bast_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	},
+	/* port 2 is not actually used */
+	[2] = {
+		.hwport	     = 2,
+		.flags	     = 0,
+		.clock	     = &bast_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	}
+};
+
+
+void __init bast_map_io(void)
+{
+	s3c2410_map_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
+	s3c2410_uartcfgs = bast_uartcfgs;
+}
+
+void __init bast_init_irq(void)
+{
+	//llprintk("bast_init_irq:\n");
+
+	s3c2410_init_irq();
+
+}
+
+MACHINE_START(BAST, "Simtec-BAST")
+     MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
+     BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
+     BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
+     MAPIO(bast_map_io)
+     INITIRQ(bast_init_irq)
+MACHINE_END
diff -Nru a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/mach-h1940.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,100 @@
+/* linux/arch/arm/mach-s3c2410/mach-ipaq.c
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.handhelds.org/projects/h1940.html
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *     16-May-2003 BJD  Created initial version
+ *     16-Aug-2003 BJD  Fixed header files and copyright, added URL
+ *     05-Sep-2003 BJD  Moved to v2.6 kernel
+ *     06-Jan-2003 BJD  Updates for <arch/map.h>
+ *     18-Jan-2003 BJD  Added serial port configuration
+ *     17-Feb-2003 BJD  Copied to mach-ipaq.c
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+//#include <asm/debug-ll.h>
+#include <asm/arch/regs-serial.h>
+
+#include "s3c2410.h"
+
+static struct map_desc ipaq_iodesc[] __initdata = {
+	/* nothing here yet */
+};
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.clock	     = &s3c2410_hclk,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x51,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.clock	     = &s3c2410_hclk,
+		.ucon	     = 0x245,
+		.ulcon	     = 0x03,
+		.ufcon	     = 0x00,
+	},
+	/* IR port */
+	[2] = {
+		.hwport	     = 2,
+		.flags	     = 0,
+		.clock	     = &s3c2410_hclk,
+		.ucon	     = 0x3c5,
+		.ulcon	     = 0x43,
+		.ufcon	     = 0x51,
+	}
+};
+
+
+void __init ipaq_map_io(void)
+{
+	s3c2410_map_io(ipaq_iodesc, ARRAY_SIZE(ipaq_iodesc));
+	s3c2410_uartcfgs = ipaq_uartcfgs;
+}
+
+void __init ipaq_init_irq(void)
+{
+	//llprintk("ipaq_init_irq:\n");
+
+	s3c2410_init_irq();
+
+}
+
+MACHINE_START(H1940, "IPAQ-H1940")
+     MAINTAINER("Ben Dooks <ben@fluff.org>")
+     BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
+     BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
+     MAPIO(ipaq_map_io)
+     INITIRQ(ipaq_init_irq)
+MACHINE_END
diff -Nru a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,164 @@
+/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *     16-May-2003 BJD  Created initial version
+ *     16-Aug-2003 BJD  Fixed header files and copyright, added URL
+ *     05-Sep-2003 BJD  Moved to v2.6 kernel
+ *     06-Jan-2003 BJD  Updates for <arch/map.h>
+ *     18-Jan-2003 BJD  Added serial port configuration
+ *     05-Apr-2004 BJD  Copied to make mach-vr1000.c
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/bast-map.h>
+#include <asm/arch/vr1000-map.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+//#include <asm/debug-ll.h>
+#include <asm/arch/regs-serial.h>
+
+#include "s3c2410.h"
+
+/* macros for virtual address mods for the io space entries */
+#define VA_C5(item) ((item) + BAST_VAM_CS5)
+#define VA_C4(item) ((item) + BAST_VAM_CS4)
+#define VA_C3(item) ((item) + BAST_VAM_CS3)
+#define VA_C2(item) ((item) + BAST_VAM_CS2)
+
+/* macros to modify the physical addresses for io space */
+
+#define PA_CS2(item) ((item) + S3C2410_CS2)
+#define PA_CS3(item) ((item) + S3C2410_CS3)
+#define PA_CS4(item) ((item) + S3C2410_CS4)
+#define PA_CS5(item) ((item) + S3C2410_CS5)
+
+static struct map_desc vr1000_iodesc[] __initdata = {
+  /* ISA IO areas */
+
+  { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO),	   SZ_16M, MT_DEVICE },
+  { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO),	   SZ_16M, MT_DEVICE },
+
+  /* we could possibly compress the next set down into a set of smaller tables
+   * pagetables, but that would mean using an L2 section, and it still means
+   * we cannot actually feed the same register to an LDR due to 16K spacing
+   */
+
+  /* bast CPLD control registers, and external interrupt controls */
+  { VR1000_VA_CTRL1, VR1000_PA_CTRL1,		       SZ_1M, MT_DEVICE },
+  { VR1000_VA_CTRL2, VR1000_PA_CTRL2,		       SZ_1M, MT_DEVICE },
+  { VR1000_VA_CTRL3, VR1000_PA_CTRL3,		       SZ_1M, MT_DEVICE },
+  { VR1000_VA_CTRL4, VR1000_PA_CTRL4,		       SZ_1M, MT_DEVICE },
+
+  /* peripheral space... one for each of fast/slow/byte/16bit */
+  /* note, ide is only decoded in word space, even though some registers
+   * are only 8bit */
+
+  /* slow, byte */
+  { VA_C2(VR1000_VA_DM9000),  PA_CS2(VR1000_PA_DM9000),	  SZ_1M,  MT_DEVICE },
+  { VA_C2(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),	  SZ_1M,  MT_DEVICE },
+  { VA_C2(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),	  SZ_1M,  MT_DEVICE },
+  { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+
+  /* slow, word */
+  { VA_C3(VR1000_VA_DM9000),  PA_CS3(VR1000_PA_DM9000),	  SZ_1M,  MT_DEVICE },
+  { VA_C3(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),	  SZ_1M,  MT_DEVICE },
+  { VA_C3(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),	  SZ_1M,  MT_DEVICE },
+  { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+
+  /* fast, byte */
+  { VA_C4(VR1000_VA_DM9000),  PA_CS4(VR1000_PA_DM9000),	  SZ_1M,  MT_DEVICE },
+  { VA_C4(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),	  SZ_1M,  MT_DEVICE },
+  { VA_C4(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),	  SZ_1M,  MT_DEVICE },
+  { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+
+  /* fast, word */
+  { VA_C5(VR1000_VA_DM9000),  PA_CS5(VR1000_PA_DM9000),	  SZ_1M,  MT_DEVICE },
+  { VA_C5(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),	  SZ_1M,  MT_DEVICE },
+  { VA_C5(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),	  SZ_1M,  MT_DEVICE },
+  { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
+  { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
+};
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+/* base baud rate for all our UARTs */
+static unsigned long vr1000_serial_clock = 3692307;
+
+static struct s3c2410_uartcfg vr1000_uartcfgs[] = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.clock	     = &vr1000_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.clock	     = &vr1000_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	},
+	/* port 2 is not actually used */
+	[2] = {
+		.hwport	     = 2,
+		.flags	     = 0,
+		.clock	     = &vr1000_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	}
+};
+
+
+void __init vr1000_map_io(void)
+{
+	s3c2410_map_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
+	s3c2410_uartcfgs = vr1000_uartcfgs;
+}
+
+void __init vr1000_init_irq(void)
+{
+	//llprintk("vr1000init_irq:\n");
+
+	s3c2410_init_irq();
+
+}
+
+MACHINE_START(VR1000, "Simtec-VR1000")
+     MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
+     BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
+     BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
+     MAPIO(vr1000_map_io)
+     INITIRQ(vr1000_init_irq)
+MACHINE_END
diff -Nru a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/s3c2410.c	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,191 @@
+/* linux/arch/arm/mach-s3c2410/s3c2410.c
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://www.simtec.co.uk/products/EB2410ITX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *     16-May-2003 BJD  Created initial version
+ *     16-Aug-2003 BJD  Fixed header files and copyright, added URL
+ *     05-Sep-2003 BJD  Moved to kernel v2.6
+ *     18-Jan-2003 BJD  Added serial port configuration
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/regs-clock.h>
+#include <asm/arch/regs-serial.h>
+
+int s3c2410_clock_tick_rate = 12*1000*1000;  /* current timers at 12MHz */
+
+/* serial port setup */
+
+struct s3c2410_uartcfg *s3c2410_uartcfgs;
+
+/* clock info */
+
+unsigned long s3c2410_fclk;
+unsigned long s3c2410_hclk;
+unsigned long s3c2410_pclk;
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
+
+#define IODESC_ENT(x) { S3C2410_VA_##x, S3C2410_PA_##x, S3C2410_SZ_##x, MT_DEVICE }
+
+static struct map_desc s3c2410_iodesc[] __initdata = {
+  IODESC_ENT(IRQ),
+  IODESC_ENT(MEMCTRL),
+  IODESC_ENT(USBHOST),
+  IODESC_ENT(DMA),
+  IODESC_ENT(CLKPWR),
+  IODESC_ENT(LCD),
+  IODESC_ENT(NAND),
+  IODESC_ENT(UART),
+  IODESC_ENT(TIMER),
+  IODESC_ENT(USBDEV),
+  IODESC_ENT(WATCHDOG),
+  IODESC_ENT(IIC),
+  IODESC_ENT(IIS),
+  IODESC_ENT(GPIO),
+  IODESC_ENT(RTC),
+  IODESC_ENT(ADC),
+  IODESC_ENT(SPI),
+  IODESC_ENT(SDI)
+};
+
+static struct resource s3c_uart0_resource[] = {
+	[0] = {
+		.start = S3C2410_PA_UART0,
+		.end   = S3C2410_PA_UART0 + 0x3fff,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_S3CUART_RX0,
+		.end   = IRQ_S3CUART_ERR0,
+		.flags = IORESOURCE_IRQ,
+	}
+
+};
+
+static struct resource s3c_uart1_resource[] = {
+	[0] = {
+		.start = S3C2410_PA_UART1,
+		.end   = S3C2410_PA_UART1 + 0x3fff,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_S3CUART_RX1,
+		.end   = IRQ_S3CUART_ERR1,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+static struct resource s3c_uart2_resource[] = {
+	[0] = {
+		.start = S3C2410_PA_UART2,
+		.end   = S3C2410_PA_UART2 + 0x3fff,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_S3CUART_RX2,
+		.end   = IRQ_S3CUART_ERR2,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+/* our uart devices */
+
+static struct platform_device s3c_uart0 = {
+	.name		  = "s3c2410-uart",
+	.id		  = 0,
+	.num_resources	  = ARRAY_SIZE(s3c_uart0_resource),
+	.resource	  = s3c_uart0_resource,
+};
+
+
+static struct platform_device s3c_uart1 = {
+	.name		  = "s3c2410-uart",
+	.id		  = 1,
+	.num_resources	  = ARRAY_SIZE(s3c_uart1_resource),
+	.resource	  = s3c_uart1_resource,
+};
+
+static struct platform_device s3c_uart2 = {
+	.name		  = "s3c2410-uart",
+	.id		  = 2,
+	.num_resources	  = ARRAY_SIZE(s3c_uart2_resource),
+	.resource	  = s3c_uart2_resource,
+};
+
+static struct platform_device *uart_devices[] __initdata = {
+	&s3c_uart0,
+	&s3c_uart1,
+	&s3c_uart2
+};
+
+void __init s3c2410_map_io(struct map_desc *mach_desc, int size)
+{
+	unsigned long tmp;
+
+	/* register our io-tables */
+
+	iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
+	iotable_init(mach_desc, size);
+
+	/* now we've got our machine bits initialised, work out what
+	 * clocks we've got */
+
+	s3c2410_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), 12*MHZ);
+
+	tmp = __raw_readl(S3C2410_CLKDIVN);
+	//printk("tmp=%08x, fclk=%d\n", tmp, s3c2410_fclk);
+
+	/* work out clock scalings */
+
+	s3c2410_hclk = s3c2410_fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
+	s3c2410_pclk = s3c2410_hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
+
+	/* print brieft summary of clocks, etc */
+
+	printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
+	       print_mhz(s3c2410_fclk), print_mhz(s3c2410_hclk),
+	       print_mhz(s3c2410_pclk));
+}
+
+
+static int __init s3c2410_init(void)
+{
+	int ret;
+
+	printk("S3C2410: Initialising architecture\n");
+
+	ret = platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices));
+
+	return ret;
+}
+
+arch_initcall(s3c2410_init);
diff -Nru a/arch/arm/mach-s3c2410/s3c2410.h b/arch/arm/mach-s3c2410/s3c2410.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/arm/mach-s3c2410/s3c2410.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,6 @@
+
+
+extern void s3c2410_map_io(struct map_desc *, int count);
+
+extern void s3c2410_init_irq(void);
+
diff -Nru a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
--- a/arch/arm/mm/Kconfig	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/mm/Kconfig	Thu Apr  8 14:54:32 2004
@@ -58,8 +58,9 @@
 
 # ARM920T
 config CPU_ARM920T
-	bool "Support ARM920T processor"
-	depends on ARCH_INTEGRATOR
+	bool "Support ARM920T processor" if !ARCH_S3C2410
+	depends on ARCH_INTEGRATOR || ARCH_S3C2410
+	default y if ARCH_S3C2410
 	select CPU_32v4
 	select CPU_ABRT_EV4T
 	select CPU_CACHE_V4WT
@@ -67,7 +68,9 @@
 	select CPU_TLB_V4WBI
 	help
 	  The ARM920T is licensed to be produced by numerous vendors,
-	  and is used in the Maverick EP9312.  More information at
+	  and is used in the Maverick EP9312 and the Samsung S3C2410.
+
+	  More information on the Maverick EP9312 at
 	  <http://linuxdevices.com/products/PD2382866068.html>.
 
 	  Say Y if you want support for the ARM920T processor.
diff -Nru a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
--- a/arch/arm/mm/fault-armv.c	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/mm/fault-armv.c	Thu Apr  8 14:54:32 2004
@@ -226,9 +226,11 @@
 {
 	struct list_head *l;
 	struct mm_struct *mm = vma->vm_mm;
-	unsigned long pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
+	unsigned long pgoff;
 	int aliases = 0;
 
+	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
+
 	/*
 	 * If we have any shared mappings that are in the same mm
 	 * space, then we need to handle them specially to maintain
@@ -242,7 +244,7 @@
 
 		/*
 		 * If this VMA is not in our MM, we can ignore it.
-		 * Note that we intentionally don't mask out the VMA
+		 * Note that we intentionally mask out the VMA
 		 * that we are fixing up.
 		 */
 		if (mpnt->vm_mm != mm || mpnt == vma)
diff -Nru a/arch/arm/mm/tlb-v4wbi.S b/arch/arm/mm/tlb-v4wbi.S
--- a/arch/arm/mm/tlb-v4wbi.S	Thu Apr  8 14:54:32 2004
+++ b/arch/arm/mm/tlb-v4wbi.S	Thu Apr  8 14:54:32 2004
@@ -10,7 +10,7 @@
  *  ARM architecture version 4 and version 5 TLB handling functions.
  *  These assume a split I/D TLBs, with a write buffer.
  *
- *  Processors: ARM920 ARM922 ARM926 XScale
+ *  Processors: ARM920 ARM922 ARM925 ARM926 XScale
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
diff -Nru a/include/asm-arm/arch-adifcc/vmalloc.h b/include/asm-arm/arch-adifcc/vmalloc.h
--- a/include/asm-arm/arch-adifcc/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-adifcc/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (0xe8000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-cl7500/vmalloc.h b/include/asm-arm/arch-cl7500/vmalloc.h
--- a/include/asm-arm/arch-cl7500/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-cl7500/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,7 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
-
diff -Nru a/include/asm-arm/arch-clps711x/vmalloc.h b/include/asm-arm/arch-clps711x/vmalloc.h
--- a/include/asm-arm/arch-clps711x/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-clps711x/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -29,6 +29,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-ebsa110/vmalloc.h b/include/asm-arm/arch-ebsa110/vmalloc.h
--- a/include/asm-arm/arch-ebsa110/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-ebsa110/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -19,6 +19,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
--- a/include/asm-arm/arch-ebsa285/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -24,6 +24,3 @@
 #else
 #define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
 #endif
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h
--- a/include/asm-arm/arch-epxa10db/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-epxa10db/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -29,6 +29,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-integrator/vmalloc.h b/include/asm-arm/arch-integrator/vmalloc.h
--- a/include/asm-arm/arch-integrator/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-integrator/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -29,6 +29,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h
--- a/include/asm-arm/arch-iop3xx/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-iop3xx/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (0xe8000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-l7200/vmalloc.h b/include/asm-arm/arch-l7200/vmalloc.h
--- a/include/asm-arm/arch-l7200/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-l7200/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-nexuspci/vmalloc.h b/include/asm-arm/arch-nexuspci/vmalloc.h
--- a/include/asm-arm/arch-nexuspci/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-nexuspci/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-omap/bus.h b/include/asm-arm/arch-omap/bus.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/bus.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,97 @@
+/*
+ * linux/include/asm-arm/arch-omap/bus.h
+ *
+ * Virtual bus for OMAP. Allows better power management, such as managing
+ * shared clocks, and mapping of bus addresses to Local Bus addresses.
+ *
+ * See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for
+ * examples on how to register drivers to this bus.
+ *
+ * Copyright (C) 2003 - 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ * Portions of code based on sa1111.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_OMAP_BUS_H
+#define __ASM_ARM_ARCH_OMAP_BUS_H
+
+extern struct bus_type omap_bus_types[];
+
+/*
+ * Description for physical device
+ */
+struct omap_dev {
+	struct device	dev;		/* Standard device description */
+	char		*name;
+	unsigned int	devid;		/* OMAP device id */
+	unsigned int	busid;		/* OMAP virtual busid */
+	struct resource res;		/* Standard resource description */
+	void		*mapbase;	/* OMAP physical address */
+	unsigned int	irq[6];		/* OMAP interrupts */
+	u64		*dma_mask;	/* Used by USB OHCI only */
+};
+
+#define OMAP_DEV(_d)	container_of((_d), struct omap_dev, dev)
+
+#define omap_get_drvdata(d)	dev_get_drvdata(&(d)->dev)
+#define omap_set_drvdata(d,p)	dev_set_drvdata(&(d)->dev, p)
+
+/*
+ * Description for device driver
+ */
+struct omap_driver {
+	struct device_driver	drv;	/* Standard driver description */
+	unsigned int		devid;	/* OMAP device id for bus */
+	unsigned int		busid;	/* OMAP virtual busid */
+	unsigned int		clocks; /* OMAP shared clocks */
+	int (*probe)(struct omap_dev *);
+	int (*remove)(struct omap_dev *);
+	int (*suspend)(struct omap_dev *, u32);
+	int (*resume)(struct omap_dev *);
+};
+
+#define OMAP_DRV(_d)	container_of((_d), struct omap_driver, drv)
+#define OMAP_DRIVER_NAME(_omapdev) ((_omapdev)->dev.driver->name)
+
+/*
+ * Device ID numbers for bus types
+ */
+#define OMAP_OCP_DEVID_USB	0
+#define OMAP_TIPB_DEVID_LCD	1
+#define OMAP_TIPB_DEVID_MMC	2
+
+/*
+ * Virtual bus definitions for OMAP
+ */
+#define OMAP_NR_BUSES	2
+
+#define OMAP_BUS_NAME_TIPB	"tipb"
+#define OMAP_BUS_NAME_LBUS	"lbus"
+
+enum {
+	OMAP_BUS_TIPB = 0,
+	OMAP_BUS_LBUS,
+};
+
+/* See arch/arm/mach-omap/bus.c for the rest of the bus definitions. */
+
+extern int omap_driver_register(struct omap_driver *driver);
+extern void omap_driver_unregister(struct omap_driver *driver);
+extern int omap_device_register(struct omap_dev *odev);
+extern void omap_device_unregister(struct omap_dev *odev);
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/clocks.h b/include/asm-arm/arch-omap/clocks.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/clocks.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,216 @@
+/*
+ * OMAP clock interface
+ *
+ * Copyright (C) 2001 RidgeRun, Inc
+ * Written by Gordon McNutt <gmcnutt@ridgerun.com>
+ * Updated 2004 for Linux 2.6 by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARM_CLOCKS_H
+#define __ASM_ARM_CLOCKS_H
+
+#include <linux/config.h>
+
+/* ARM_CKCTL bit shifts */
+#define PERDIV			0
+#define LCDDIV			2
+#define ARMDIV			4
+#define DSPDIV			6
+#define TCDIV			8
+#define DSPMMUDIV		10
+#define ARM_TIMXO		12
+#define EN_DSPCK		13
+#define ARM_INTHCK_SEL		14 /* REVISIT: Where is this used? */
+
+/* ARM_IDLECT1 bit shifts */
+#define IDLWDT_ARM	0
+#define IDLXORP_ARM	1
+#define IDLPER_ARM	2
+#define IDLLCD_ARM	3
+#define IDLLB_ARM	4
+#define IDLHSAB_ARM	5
+#define IDLIF_ARM	6
+#define IDLDPLL_ARM	7
+#define IDLAPI_ARM	8
+#define IDLTIM_ARM	9
+#define SETARM_IDLE	11
+
+/* ARM_IDLECT2 bit shifts */
+#define EN_WDTCK	0
+#define EN_XORPCK	1
+#define EN_PERCK	2
+#define EN_LCDCK	3
+#define EN_LBCK		4
+#define EN_HSABCK	5
+#define EN_APICK	6
+#define EN_TIMCK	7
+#define DMACK_REQ	8
+#define EN_GPIOCK	9
+#define EN_LBFREECK	10
+
+/*
+ * OMAP clocks
+ */
+typedef enum {
+	/* Fixed system clock */
+	OMAP_CLKIN = 0,
+
+	/* DPLL1 */
+	OMAP_CK_GEN1, OMAP_CK_GEN2, OMAP_CK_GEN3,
+
+	/* TC usually needs to be checked before anything else */
+	OMAP_TC_CK,
+
+	/* CLKM1 */
+	OMAP_ARM_CK, OMAP_MPUPER_CK, OMAP_ARM_GPIO_CK, OMAP_MPUXOR_CK,
+	OMAP_MPUTIM_CK, OMAP_MPUWD_CK,
+
+	/* CLKM2 */
+	OMAP_DSP_CK, OMAP_DSPMMU_CK,
+#if 0
+	/* Accessible only from the dsp */
+	OMAP_DSPPER_CK, OMAP_GPIO_CK, OMAP_DSPXOR_CK, OMAP_DSPTIM_CK,
+	OMAP_DSPWD_CK, OMAP_UART_CK,
+#endif
+	/* CLKM3 */
+	OMAP_DMA_CK, OMAP_API_CK, OMAP_HSAB_CK, OMAP_LBFREE_CK,
+	OMAP_LB_CK, OMAP_LCD_CK
+} ck_t;
+
+typedef enum {
+	/* Reset the MPU */
+	OMAP_ARM_RST,
+
+	/* Reset the DSP */
+	OMAP_DSP_RST,
+
+	/* Reset priority registers, EMIF config, and MPUI control logic */
+	OMAP_API_RST,
+
+	/* Reset DSP, MPU, and Peripherals */
+	OMAP_SW_RST,
+} reset_t;
+
+#define OMAP_CK_MIN			OMAP_CLKIN
+#define OMAP_CK_MAX			OMAP_LCD_CK
+
+#if defined(CONFIG_OMAP_ARM_30MHZ)
+#define OMAP_CK_MAX_RATE		30
+#elif defined(CONFIG_OMAP_ARM_60MHZ)
+#define OMAP_CK_MAX_RATE		60
+#elif defined(CONFIG_OMAP_ARM_96MHZ)
+#define OMAP_CK_MAX_RATE		96
+#elif defined(CONFIG_OMAP_ARM_120MHZ)
+#define OMAP_CK_MAX_RATE		120
+#elif defined(CONFIG_OMAP_ARM_168MHZ)
+#define OMAP_CK_MAX_RATE		168
+#elif defined(CONFIG_OMAP_ARM_182MHZ)
+#define OMAP_CK_MAX_RATE		182
+#elif defined(CONFIG_OMAP_ARM_192MHZ)
+#define OMAP_CK_MAX_RATE		192
+#elif defined(CONFIG_OMAP_ARM_195MHZ)
+#define OMAP_CK_MAX_RATE		195
+#endif
+
+#define CK_DPLL_MASK			0x0fe0
+
+/* Shared by CK and DSPC */
+#define MPUI_STROBE_MAX_1509		24
+#define MPUI_STROBE_MAX_1510		30
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clock interface functions
+ * ----------------------------------------------------------------------------
+ */
+
+/*  Clock initialization.  */
+int init_ck(void);
+
+/*
+ * For some clocks you have a choice of which "parent" clocks they are derived
+ * from. Use this to select a "parent". See the platform documentation for
+ * valid combinations.
+ */
+int ck_can_set_input(ck_t);
+int ck_set_input(ck_t ck, ck_t input);
+int ck_get_input(ck_t ck, ck_t *input);
+
+/*
+ * Use this to set a clock rate. If other clocks are derived from this one,
+ * their rates will all change too. If this is a derived clock and I can't
+ * change it to match your request unless I also change the parent clock, then
+ * tough luck -- I won't change the parent automatically. I'll return an error
+ * if I can't get the clock within 10% of what you want. Otherwise I'll return
+ * the value I actually set it to. If I have to switch parents to get the rate
+ * then I will do this automatically (since it only affects this clock and its
+ * descendants).
+ */
+int ck_can_set_rate(ck_t);
+int ck_set_rate(ck_t ck, int val_in_mhz);
+int ck_get_rate(ck_t ck);
+
+/*
+ * Use this to get a bitmap of available rates for the clock. Caller allocates
+ *  the buffer and passes in the length. Clock module fills up to len bytes of
+ *  the buffer & passes back actual bytes used.
+ */
+int ck_get_rates(ck_t ck, void *buf, int len);
+int ck_valid_rate(int rate);
+
+/*
+ * Idle a clock. What happens next depends on the clock ;). For example, if
+ * you idle the ARM_CK you might well end up in sleep mode on some platforms.
+ * If you try to idle a clock that doesn't support it I'll return an error.
+ * Note that idling a clock does not always take affect until certain h/w
+ * conditions are met. Consult the platform specs to learn more.
+ */
+int ck_can_idle(ck_t);
+int ck_idle(ck_t);
+int ck_activate(ck_t);
+int ck_is_idle(ck_t);
+
+/*
+ * Enable/disable a clock. I'll return an error if the h/w doesn't support it.
+ * If you disable a clock being used by an active device then you probably
+ * just screwed it. YOU are responsible for making sure this doesn't happen.
+ */
+int ck_can_disable(ck_t);
+int ck_enable(ck_t);
+int ck_disable(ck_t);
+int ck_is_enabled(ck_t);
+
+/* Enable/reset ARM peripherals (remove/set reset signal) */
+void ck_enable_peripherals(void);
+void ck_reset_peripherals(void);
+
+/* Generate/clear a MPU or DSP reset */
+void ck_generate_reset(reset_t reset);
+void ck_release_from_reset(reset_t reset);
+
+/* This gets a string representation of the clock's name. Useful for proc. */
+char *ck_get_name(ck_t);
+
+extern void start_mputimer1(unsigned long);
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/dma.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,224 @@
+/*
+ *  linux/include/asm-arm/arch-omap/dma.h
+ *
+ *  Copyright (C) 2003 Nokia Corporation
+ *  Author: Juha Yrj�l� <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS			0xffffffff
+
+#define OMAP_LOGICAL_DMA_CH_COUNT	17
+
+#define OMAP_DMA_NO_DEVICE		0
+#define OMAP_DMA_MCSI1_TX		1
+#define OMAP_DMA_MCSI1_RX		2
+#define OMAP_DMA_I2C_RX			3
+#define OMAP_DMA_I2C_TX			4
+#define OMAP_DMA_EXT_NDMA_REQ		5
+#define OMAP_DMA_EXT_NDMA_REQ2		6
+#define OMAP_DMA_UWIRE_TX		7
+#define OMAP_DMA_MCBSP1_DMA_TX		8
+#define OMAP_DMA_MCBSP1_DMA_RX		9
+#define OMAP_DMA_MCBSP3_DMA_TX		10
+#define OMAP_DMA_MCBSP3_DMA_RX		11
+#define OMAP_DMA_UART1_TX		12
+#define OMAP_DMA_UART1_RX		13
+#define OMAP_DMA_UART2_TX		14
+#define OMAP_DMA_UART2_RX		15
+#define OMAP_DMA_MCBSP2_TX		16
+#define OMAP_DMA_MCBSP2_RX		17
+#define OMAP_DMA_UART3_TX		18
+#define OMAP_DMA_UART3_RX		19
+#define OMAP_DMA_CAMERA_IF_RX		20
+#define OMAP_DMA_MMC_TX			21
+#define OMAP_DMA_MMC_RX			22
+#define OMAP_DMA_NAND			23
+#define OMAP_DMA_IRQ_LCD_LINE		24
+#define OMAP_DMA_MEMORY_STICK		25
+#define OMAP_DMA_USB_W2FC_RX0		26
+#define OMAP_DMA_USB_W2FC_RX1		27
+#define OMAP_DMA_USB_W2FC_RX2		28
+#define OMAP_DMA_USB_W2FC_TX0		29
+#define OMAP_DMA_USB_W2FC_TX1		30
+#define OMAP_DMA_USB_W2FC_TX2		31
+
+/* These are only for 1610 */
+#define OMAP_DMA_CRYPTO_DES_IN		32
+#define OMAP_DMA_SPI_TX			33
+#define OMAP_DMA_SPI_RX			34
+#define OMAP_DMA_CRYPTO_HASH		35
+#define OMAP_DMA_CCP_ATTN		36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY	37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0	38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0	39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1	40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1	41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2	42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2	43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3	44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3	45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4	46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4	47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5	48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5	49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6	50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6	51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7	52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7	53
+#define OMAP_DMA_MMC2_TX		54
+#define OMAP_DMA_MMC2_RX		55
+#define OMAP_DMA_CRYPTO_DES_OUT		56
+
+
+#define OMAP_DMA_BASE			0xfffed800
+#define OMAP_DMA_GCR_REG		(OMAP_DMA_BASE + 0x400)
+#define OMAP_DMA_GSCR_REG		(OMAP_DMA_BASE + 0x404)
+#define OMAP_DMA_GRST_REG		(OMAP_DMA_BASE + 0x408)
+#define OMAP_DMA_HW_ID_REG		(OMAP_DMA_BASE + 0x442)
+#define OMAP_DMA_PCH2_ID_REG		(OMAP_DMA_BASE + 0x444)
+#define OMAP_DMA_PCH0_ID		(OMAP_DMA_BASE + 0x446)
+#define OMAP_DMA_PCH1_ID		(OMAP_DMA_BASE + 0x448)
+#define OMAP_DMA_PCHG_ID		(OMAP_DMA_BASE + 0x44a)
+#define OMAP_DMA_PCHD_ID		(OMAP_DMA_BASE + 0x44c)
+#define OMAP_DMA_CAPS_0_U_REG		(OMAP_DMA_BASE + 0x44e)
+#define OMAP_DMA_CAPS_0_L_REG		(OMAP_DMA_BASE + 0x450)
+#define OMAP_DMA_CAPS_1_U_REG		(OMAP_DMA_BASE + 0x452)
+#define OMAP_DMA_CAPS_1_L_REG		(OMAP_DMA_BASE + 0x454)
+#define OMAP_DMA_CAPS_2_REG		(OMAP_DMA_BASE + 0x456)
+#define OMAP_DMA_CAPS_3_REG		(OMAP_DMA_BASE + 0x458)
+#define OMAP_DMA_CAPS_4_REG		(OMAP_DMA_BASE + 0x45a)
+#define OMAP_DMA_PCH2_SR_REG		(OMAP_DMA_BASE + 0x460)
+#define OMAP_DMA_PCH0_SR_REG		(OMAP_DMA_BASE + 0x480)
+#define OMAP_DMA_PCH1_SR_REG		(OMAP_DMA_BASE + 0x482)
+#define OMAP_DMA_PCHD_SR_REG		(OMAP_DMA_BASE + 0x4c0)
+
+#define OMAP1510_DMA_LCD_CTRL		0xfffedb00
+#define OMAP1510_DMA_LCD_TOP_F1_L	0xfffedb02
+#define OMAP1510_DMA_LCD_TOP_F1_U	0xfffedb04
+#define OMAP1510_DMA_LCD_BOT_F1_L	0xfffedb06
+#define OMAP1510_DMA_LCD_BOT_F1_U	0xfffedb08
+
+#define OMAP1610_DMA_LCD_CSDP		0xfffee3c0
+#define OMAP1610_DMA_LCD_CCR		0xfffee3c2
+#define OMAP1610_DMA_LCD_CTRL		0xfffee3c4
+#define OMAP1610_DMA_LCD_TOP_B1_L	0xfffee3c8
+#define OMAP1610_DMA_LCD_TOP_B1_U	0xfffee3ca
+#define OMAP1610_DMA_LCD_BOT_B1_L	0xfffee3cc
+#define OMAP1610_DMA_LCD_BOT_B1_U	0xfffee3ce
+#define OMAP1610_DMA_LCD_TOP_B2_L	0xfffee3d0
+#define OMAP1610_DMA_LCD_TOP_B2_U	0xfffee3d2
+#define OMAP1610_DMA_LCD_BOT_B2_L	0xfffee3d4
+#define OMAP1610_DMA_LCD_BOT_B2_U	0xfffee3d6
+#define OMAP1610_DMA_LCD_SRC_EI_B1	0xfffee3d8
+#define OMAP1610_DMA_LCD_SRC_FI_B1_L	0xfffee3da
+#define OMAP1610_DMA_LCD_SRC_EN_B1	0xfffee3e0
+#define OMAP1610_DMA_LCD_SRC_FN_B1	0xfffee3e4
+#define OMAP1610_DMA_LCD_LCH_CTRL	0xfffee3ea
+#define OMAP1610_DMA_LCD_SRC_FI_B1_U	0xfffee3f4
+
+
+/* Every LCh has its own set of the registers below */
+#define OMAP_DMA_CSDP_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
+#define OMAP_DMA_CCR_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
+#define OMAP_DMA_CICR_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
+#define OMAP_DMA_CSR_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
+#define OMAP_DMA_CSSA_L_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP_DMA_CSSA_U_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP_DMA_CDSA_L_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP_DMA_CDSA_U_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP_DMA_CEN_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
+#define OMAP_DMA_CFN_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
+#define OMAP_DMA_CSFI_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
+#define OMAP_DMA_CSEI_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
+#define OMAP_DMA_CSAC_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
+#define OMAP_DMA_CDAC_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
+#define OMAP_DMA_CDEI_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
+#define OMAP_DMA_CDFI_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
+#define OMAP_DMA_COLOR_L_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP_DMA_COLOR_U_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP_DMA_CCR2_REG(n)		(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP_DMA_CLNK_CTRL_REG(n)	(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
+#define OMAP_DMA_LCH_CTRL_REG(n)	(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+
+#define OMAP_DMA_TOUT_IRQ		(1 << 0)
+#define OMAP_DMA_DROP_IRQ		(1 << 1)
+#define OMAP_DMA_HALF_IRQ		(1 << 2)
+#define OMAP_DMA_FRAME_IRQ		(1 << 3)
+#define OMAP_DMA_LAST_IRQ		(1 << 4)
+#define OMAP_DMA_BLOCK_IRQ		(1 << 5)
+#define OMAP_DMA_SYNC_IRQ		(1 << 6)
+
+#define OMAP_DMA_DATA_TYPE_S8		0x00
+#define OMAP_DMA_DATA_TYPE_S16		0x01
+#define OMAP_DMA_DATA_TYPE_S32		0x02
+
+#define OMAP_DMA_SYNC_ELEMENT		0x00
+#define OMAP_DMA_SYNC_FRAME		0x01
+#define OMAP_DMA_SYNC_BLOCK		0x02
+
+#define OMAP_DMA_PORT_EMIFF		0x00
+#define OMAP_DMA_PORT_EMIFS		0x01
+#define OMAP_DMA_PORT_OCP_T1		0x02
+#define OMAP_DMA_PORT_TIPB		0x03
+#define OMAP_DMA_PORT_OCP_T2		0x04
+#define OMAP_DMA_PORT_MPUI		0x05
+
+#define OMAP_DMA_AMODE_CONSTANT		0x00
+#define OMAP_DMA_AMODE_POST_INC		0x01
+#define OMAP_DMA_AMODE_SINGLE_IDX	0x02
+#define OMAP_DMA_AMODE_DOUBLE_IDX	0x03
+
+/* LCD DMA block numbers */
+enum {
+	OMAP_LCD_DMA_B1_TOP,
+	OMAP_LCD_DMA_B1_BOTTOM,
+	OMAP_LCD_DMA_B2_TOP,
+	OMAP_LCD_DMA_B2_BOTTOM
+};
+
+extern int omap_request_dma(int dev_id, const char *dev_name,
+			    void (* callback)(int lch, u16 ch_status, void *data),
+			    void *data, int *dma_ch);
+extern void omap_enable_dma_irq(int ch, u16 irq_bits);
+extern void omap_disable_dma_irq(int ch, u16 irq_bits);
+extern void omap_free_dma(int ch);
+extern void omap_start_dma(int lch);
+extern void omap_stop_dma(int lch);
+extern void omap_set_dma_transfer_params(int lch, int data_type,
+					 int elem_count, int frame_count,
+					 int sync_mode);
+extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+				    unsigned long src_start);
+extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+				     unsigned long dest_start);
+
+/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
+extern int omap_dma_in_1510_mode(void);
+
+/* LCD DMA functions */
+extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+				void *data);
+extern void omap_free_lcd_dma(void);
+extern void omap_start_lcd_dma(void);
+extern void omap_stop_lcd_dma(void);
+extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+				int data_type);
+extern void omap_set_lcd_dma_b1_rotation(int rotate);
+
+#endif /* __ASM_ARCH_DMA_H */
diff -Nru a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/fpga.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,26 @@
+/*
+ * linux/include/asm-arm/arch-omap/fpga.h
+ *
+ * Interrupt handler for OMAP-1510 FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_FPGA_H
+#define __ASM_ARCH_OMAP_FPGA_H
+
+extern void fpga_init_irq(void);
+extern unsigned char fpga_read(int reg);
+extern void fpga_write(unsigned char val, int reg);
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/gpio.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,68 @@
+/*
+ * linux/include/asm-arm/arch-omap/gpio.h
+ *
+ * OMAP GPIO handling defines and functions
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ *
+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPIO_H
+#define __ASM_ARCH_OMAP_GPIO_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+
+#define OMAP_MPUIO_BASE			0xfffb5000
+#define OMAP_MPUIO_INPUT_LATCH		0x00
+#define OMAP_MPUIO_OUTPUT_REG		0x04
+#define OMAP_MPUIO_IO_CNTL		0x08
+#define OMAP_MPUIO_KBR_LATCH		0x10
+#define OMAP_MPUIO_KBC_REG		0x14
+#define OMAP_MPUIO_GPIO_EVENT_MODE_REG	0x18
+#define OMAP_MPUIO_GPIO_INT_EDGE_REG	0x1c
+#define OMAP_MPUIO_KBD_INT		0x20
+#define OMAP_MPUIO_GPIO_INT		0x24
+#define OMAP_MPUIO_KBD_MASKIT		0x28
+#define OMAP_MPUIO_GPIO_MASKIT		0x2c
+#define OMAP_MPUIO_GPIO_DEBOUNCING_REG	0x30
+#define OMAP_MPUIO_LATCH_REG		0x34
+
+#define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
+#define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
+
+#define OMAP_GPIO_IRQ(nr)	(OMAP_GPIO_IS_MPUIO(nr) ? \
+				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
+				 IH_GPIO_BASE + ((nr) & 0x3f))
+
+/* For EDGECTRL */
+#define OMAP_GPIO_NO_EDGE	  0x00
+#define OMAP_GPIO_FALLING_EDGE	  0x01
+#define OMAP_GPIO_RISING_EDGE	  0x02
+#define OMAP_GPIO_BOTH_EDGES	  0x03
+
+extern int omap_request_gpio(int gpio);
+extern void omap_free_gpio(int gpio);
+extern void omap_set_gpio_direction(int gpio, int is_input);
+extern void omap_set_gpio_dataout(int gpio, int enable);
+extern int omap_get_gpio_datain(int gpio);
+extern void omap_set_gpio_edge_ctrl(int gpio, int edge);
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/hardware.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,327 @@
+/*
+ * linux/include/asm-arm/arch-omap/hardware.h
+ *
+ * Hardware definitions for TI OMAP processors and boards
+ *
+ * NOTE: Please put device driver specific defines into a separate header
+ *	 file for each driver.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <linux/config.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#endif
+#include <asm/mach-types.h>
+
+/*
+ * ----------------------------------------------------------------------------
+ * I/O mapping
+ * ----------------------------------------------------------------------------
+ */
+#define IO_BASE			0xFFFB0000	/* Virtual */
+#define IO_SIZE			0x40000
+#define IO_START		0xFFFB0000	/* Physical */
+
+#define PCIO_BASE		0
+
+#define IO_ADDRESS(x)		((x))
+
+/*
+ * ---------------------------------------------------------------------------
+ * Processor differentiation
+ * ---------------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_ARCH_OMAP730
+#include "omap730.h"
+#define cpu_is_omap730()	(1)
+#else
+#define cpu_is_omap730()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+#include "omap1510.h"
+#define cpu_is_omap1510()	(1)
+#else
+#define cpu_is_omap1510()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1610
+#include "omap1610.h"
+#define cpu_is_omap1610()	(1)
+#else
+#define cpu_is_omap1610()	(0)
+#endif
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board differentiation
+ * ---------------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_OMAP_INNOVATOR
+#include "omap-innovator.h"
+#define omap_is_innovator()	(1)
+#else
+#define omap_is_innovator()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H2
+#include "omap-h2.h"
+#define omap_is_h2()		(1)
+#else
+#define omap_is_h2()		(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#include "omap-perseus2.h"
+#define omap_is_perseus2()	(1)
+#else
+#define omap_is_perseus2()	(0)
+#endif
+
+/*
+ * ---------------------------------------------------------------------------
+ * Common definitions for all OMAP processors
+ * NOTE: Put all processor or board specific parts to the special header
+ *	 files.
+ * ---------------------------------------------------------------------------
+ */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP_DSP_BASE		0xE0000000
+#define OMAP_DSP_SIZE		0x50000
+#define OMAP_DSP_START		0xE0000000
+
+#define OMAP_DSPREG_BASE	0xE1000000
+#define OMAP_DSPREG_SIZE	SZ_128K
+#define OMAP_DSPREG_START	0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_RESET_BASE	(0xfffece00)
+#define ARM_CKCTL		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
+#define ARM_IDLECT1		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
+#define ARM_IDLECT2		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
+#define ARM_EWUPCT		(volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
+#define ARM_RSTCT1		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
+#define ARM_RSTCT2		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
+#define ARM_SYSST		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
+
+#define CK_RATEF		1
+#define CK_IDLEF		2
+#define CK_ENABLEF		4
+#define CK_SELECTF		8
+#define SETARM_IDLE_SHIFT
+
+/* DPLL control registers */
+#define DPLL_CTL_REG		(volatile __u16 *)(0xfffecf00)
+#define CK_DPLL1		(volatile __u16 *)(0xfffecf00)
+
+/* ULPD */
+#define ULPD_REG_BASE		(0xfffe0800)
+#define ULPD_IT_STATUS_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x14)
+#define ULPD_CLOCK_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x30)
+#define ULPD_SOFT_REQ_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x34)
+#define ULPD_DPLL_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x50)
+#define ULPD_CAM_CLK_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x7c)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Timers
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_32kHz_TIMER_BASE 0xfffb9000
+
+/* 32k Timer Registers */
+#define TIMER32k_CR		0x08
+#define TIMER32k_TVR		0x00
+#define TIMER32k_TCR		0x04
+
+/* 32k Timer Control Register definition */
+#define TIMER32k_TSS		(1<<0)
+#define TIMER32k_TRB		(1<<1)
+#define TIMER32k_INT		(1<<2)
+#define TIMER32k_ARL		(1<<3)
+
+/* MPU Timer base addresses */
+#define OMAP_MPUTIMER_BASE	0xfffec500
+#define OMAP_MPUTIMER_OFF	0x00000100
+
+#define OMAP_TIMER1_BASE	0xfffec500
+#define OMAP_TIMER2_BASE	0xfffec600
+#define OMAP_TIMER3_BASE	0xfffec700
+#define OMAP_WATCHDOG_BASE	0xfffec800
+
+/* MPU Timer Registers */
+#define CNTL_TIMER		0
+#define LOAD_TIM		4
+#define READ_TIM		8
+
+/* CNTL_TIMER register bits */
+#define MPUTIM_FREE		(1<<6)
+#define MPUTIM_CLOCK_ENABLE	(1<<5)
+#define MPUTIM_PTV_MASK		(0x7<<PTV_BIT)
+#define MPUTIM_PTV_BIT		2
+#define MPUTIM_AR		(1<<1)
+#define MPUTIM_ST		(1<<0)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_IH1_BASE		0xfffecb00
+#define OMAP_IH2_BASE		0xfffe0000
+#define OMAP_ITR		0x0
+#define OMAP_MASK		0x4
+
+#define IRQ_ITR			0x00
+#define IRQ_MIR			0x04
+#define IRQ_SIR_IRQ		0x10
+#define IRQ_SIR_FIQ		0x14
+#define IRQ_CONTROL_REG		0x18
+#define IRQ_ISR			0x9c
+#define IRQ_ILR0		0x1c
+
+/* OMAP-1610 specific interrupt handler registers */
+#define OMAP_IH2_SECT1		(OMAP_IH2_BASE)
+#define OMAP_IH2_SECT2		(OMAP_IH2_BASE + 0x100)
+#define OMAP_IH2_SECT3		(OMAP_IH2_BASE + 0x200)
+#define OMAP_IH2_SECT4		(OMAP_IH2_BASE + 0x300)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Traffic controller memory interface
+ * ---------------------------------------------------------------------------
+ */
+#define TCMIF_BASE		0xfffecc00
+#define IMIF_PRIO		(TCMIF_BASE + 0x00)
+#define EMIFS_PRIO_REG		(TCMIF_BASE + 0x04)
+#define EMIFF_PRIO_REG		(TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG_REG	(TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG	(TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG	(TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG	(TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG	(TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
+#define EMIFF_MRS		(TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1		(TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2		(TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3		(TCMIF_BASE + 0x30)
+#define TC_ENDIANISM		(TCMIF_BASE + 0x34)
+#define EMIFF_SDRAM_CONFIG_2	(TCMIF_BASE + 0x3c)
+#define EMIF_CFG_DYNAMIC_WS	(TCMIF_BASE + 0x40)
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define MOD_CONF_CTRL_0		0xfffe1080
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin multiplexing registers
+ * ----------------------------------------------------------------------------
+ */
+#define FUNC_MUX_CTRL_0		0xfffe1000
+#define FUNC_MUX_CTRL_1		0xfffe1004
+#define FUNC_MUX_CTRL_2		0xfffe1008
+#define COMP_MODE_CTRL_0	0xfffe100c
+#define FUNC_MUX_CTRL_3		0xfffe1010
+#define FUNC_MUX_CTRL_4		0xfffe1014
+#define FUNC_MUX_CTRL_5		0xfffe1018
+#define FUNC_MUX_CTRL_6		0xfffe101C
+#define FUNC_MUX_CTRL_7		0xfffe1020
+#define FUNC_MUX_CTRL_8		0xfffe1024
+#define FUNC_MUX_CTRL_9		0xfffe1028
+#define FUNC_MUX_CTRL_A		0xfffe102C
+#define FUNC_MUX_CTRL_B		0xfffe1030
+#define FUNC_MUX_CTRL_C		0xfffe1034
+#define FUNC_MUX_CTRL_D		0xfffe1038
+#define PULL_DWN_CTRL_0		0xfffe1040
+#define PULL_DWN_CTRL_1		0xfffe1044
+#define PULL_DWN_CTRL_2		0xfffe1048
+#define PULL_DWN_CTRL_3		0xfffe104c
+
+/* OMAP-1610 specific multiplexing registers */
+#define FUNC_MUX_CTRL_E		0xfffe1090
+#define FUNC_MUX_CTRL_F		0xfffe1094
+#define FUNC_MUX_CTRL_10	0xfffe1098
+#define FUNC_MUX_CTRL_11	0xfffe109c
+#define FUNC_MUX_CTRL_12	0xfffe10a0
+#define PU_PD_SEL_0		0xfffe10b4
+#define PU_PD_SEL_1		0xfffe10b8
+#define PU_PD_SEL_2		0xfffe10bc
+#define PU_PD_SEL_3		0xfffe10c0
+#define PU_PD_SEL_4		0xfffe10c4
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_PUBLIC_CNTL_BASE		0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL_REG	(TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL_REG	(TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ----------------------------------------------------------------------------
+ * DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+/*  MPUI Interface Registers */
+#define MPUI_CTRL_REG		(volatile __u32 *)(0xfffec900)
+#define MPUI_DEBUG_ADDR		(volatile __u32 *)(0xfffec904)
+#define MPUI_DEBUG_DATA		(volatile __u32 *)(0xfffec908)
+#define MPUI_DEBUG_FLAG		(volatile __u16 *)(0xfffec90c)
+#define MPUI_STATUS_REG		(volatile __u16 *)(0xfffec910)
+#define MPUI_DSP_STATUS_REG	(volatile __u16 *)(0xfffec914)
+#define MPUI_DSP_BOOT_CONFIG	(volatile __u16 *)(0xfffec918)
+#define MPUI_DSP_API_CONFIG	(volatile __u16 *)(0xfffec91c)
+
+#endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
diff -Nru a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/io.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm-arm/arch-omap/io.h
+ *
+ * Copied from linux/include/asm-arm/arch-sa1100/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997	RMK	Created.
+ *  07-04-1999	RMK	Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)			(PCIO_BASE + (a))
+#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_isa(a)		((unsigned long)(a))
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/irqs.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,262 @@
+/*
+ *  linux/include/asm-arm/arch-omap/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *	 are different.
+ */
+
+#ifndef __ASM_ARCH_OMAP1510_IRQS_H
+#define __ASM_ARCH_OMAP1510_IRQS_H
+
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_IH2_IRQ		0
+#define INT_CAMERA		1
+#define INT_FIQ			3
+#define INT_RTDX		6
+#define INT_DSP_MMU_ABORT	7
+#define INT_HOST		8
+#define INT_ABORT		9
+#define INT_DSP_MAILBOX1	10
+#define INT_DSP_MAILBOX2	11
+#define INT_BRIDGE_PRIV		13
+#define INT_GPIO_BANK1		14
+#define INT_UART3		15
+#define INT_TIMER3		16
+#define INT_DMA_CH0_6		19
+#define INT_DMA_CH1_7		20
+#define INT_DMA_CH2_8		21
+#define INT_DMA_CH3		22
+#define INT_DMA_CH4		23
+#define INT_DMA_CH5		24
+#define INT_DMA_LCD		25
+#define INT_TIMER1		26
+#define INT_WD_TIMER		27
+#define INT_BRIDGE_PUB		28
+#define INT_TIMER2		30
+#define INT_LCD_CTRL		31
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_RES2		2
+#define INT_1510_SPI_TX		4
+#define INT_1510_SPI_RX		5
+#define INT_1510_RES12		12
+#define INT_1510_LB_MMU		17
+#define INT_1510_RES18		18
+#define INT_1510_LOCAL_BUS	29
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_FIQ	2
+#define INT_1610_McBSP2_TX	4
+#define INT_1610_McBSP2_RX	5
+#define INT_1610_LCD_LINE	12
+#define INT_1610_GPTIMER1	17
+#define INT_1610_GPTIMER2	18
+#define INT_1610_SSR_FIFO_0	29
+
+/*
+ * OMAP-730 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_730_IH2_FIQ		0
+#define INT_730_IH2_IRQ		1
+#define INT_730_USB_NON_ISO	2
+#define INT_730_USB_ISO		3
+#define INT_730_ICR		4
+#define INT_730_EAC		5
+#define INT_730_GPIO_BANK1	6
+#define INT_730_GPIO_BANK2	7
+#define INT_730_GPIO_BANK3	8
+#define INT_730_McBSP2TX	10
+#define INT_730_McBSP2RX	11
+#define INT_730_McBSP2RX_OVF	12
+#define INT_730_LCD_LINE	14
+#define INT_730_GSM_PROTECT	15
+#define INT_730_TIMER3		16
+#define INT_730_GPIO_BANK5	17
+#define INT_730_GPIO_BANK6	18
+#define INT_730_SPGIO_WR	29
+
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE		32
+
+#define INT_KEYBOARD		(1 + IH2_BASE)
+#define INT_uWireTX		(2 + IH2_BASE)
+#define INT_uWireRX		(3 + IH2_BASE)
+#define INT_I2C			(4 + IH2_BASE)
+#define INT_MPUIO		(5 + IH2_BASE)
+#define INT_USB_HHC_1		(6 + IH2_BASE)
+#define INT_McBSP3TX		(10 + IH2_BASE)
+#define INT_McBSP3RX		(11 + IH2_BASE)
+#define INT_McBSP1TX		(12 + IH2_BASE)
+#define INT_McBSP1RX		(13 + IH2_BASE)
+#define INT_UART1		(14 + IH2_BASE)
+#define INT_UART2		(15 + IH2_BASE)
+#define INT_BT_MCSI1TX		(16 + IH2_BASE)
+#define INT_BT_MCSI1RX		(17 + IH2_BASE)
+#define INT_USB_W2FC		(20 + IH2_BASE)
+#define INT_1WIRE		(21 + IH2_BASE)
+#define INT_OS_TIMER		(22 + IH2_BASE)
+#define INT_MMC			(23 + IH2_BASE)
+#define INT_GAUGE_32K		(24 + IH2_BASE)
+#define INT_RTC_TIMER		(25 + IH2_BASE)
+#define INT_RTC_ALARM		(26 + IH2_BASE)
+#define INT_MEM_STICK		(27 + IH2_BASE)
+#define INT_DSP_MMU		(28 + IH2_BASE)
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE)
+#define INT_1510_COM_SPI_RO	(31 + IH2_BASE)
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC		(0 + IH2_BASE)
+#define INT_1610_USB_HHC_2	(7 + IH2_BASE)
+#define INT_1610_USB_OTG	(8 + IH2_BASE)
+#define INT_1610_SoSSI		(9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH	(19 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF	(31 + IH2_BASE)
+#define INT_1610_GPIO_BANK2	(40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3	(41 + IH2_BASE)
+#define INT_1610_MMC2		(42 + IH2_BASE)
+#define INT_1610_GPIO_BANK4	(48 + IH2_BASE)
+#define INT_1610_SPI		(49 + IH2_BASE)
+#define INT_1610_DMA_CH6	(53 + IH2_BASE)
+#define INT_1610_DMA_CH7	(54 + IH2_BASE)
+#define INT_1610_DMA_CH8	(55 + IH2_BASE)
+#define INT_1610_DMA_CH9	(56 + IH2_BASE)
+#define INT_1610_DMA_CH10	(57 + IH2_BASE)
+#define INT_1610_DMA_CH11	(58 + IH2_BASE)
+#define INT_1610_DMA_CH12	(59 + IH2_BASE)
+#define INT_1610_DMA_CH13	(60 + IH2_BASE)
+#define INT_1610_DMA_CH14	(61 + IH2_BASE)
+#define INT_1610_DMA_CH15	(62 + IH2_BASE)
+#define INT_1610_NAND		(63 + IH2_BASE)
+
+/*
+ * OMAP-730 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_730_HW_ERRORS	(0 + IH2_BASE)
+#define INT_730_NFIQ_PWR_FAIL	(1 + IH2_BASE)
+#define INT_730_CFCD		(2 + IH2_BASE)
+#define INT_730_CFIREQ		(3 + IH2_BASE)
+#define INT_730_I2C		(4 + IH2_BASE)
+#define INT_730_PCC		(5 + IH2_BASE)
+#define INT_730_MPU_EXT_NIRQ	(6 + IH2_BASE)
+#define INT_730_SPI_100K_1	(7 + IH2_BASE)
+#define INT_730_SYREN_SPI	(8 + IH2_BASE)
+#define INT_730_VLYNQ		(9 + IH2_BASE)
+#define INT_730_GPIO_BANK4	(10 + IH2_BASE)
+#define INT_730_McBSP1TX	(11 + IH2_BASE)
+#define INT_730_McBSP1RX	(12 + IH2_BASE)
+#define INT_730_McBSP1RX_OF	(13 + IH2_BASE)
+#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_730_UART_MODEM_1	(15 + IH2_BASE)
+#define INT_730_MCSI		(16 + IH2_BASE)
+#define INT_730_uWireTX		(17 + IH2_BASE)
+#define INT_730_uWireRX		(18 + IH2_BASE)
+#define INT_730_SMC_CD		(19 + IH2_BASE)
+#define INT_730_SMC_IREQ	(20 + IH2_BASE)
+#define INT_730_HDQ_1WIRE	(21 + IH2_BASE)
+#define INT_730_TIMER32K	(22 + IH2_BASE)
+#define INT_730_MMC_SDIO	(23 + IH2_BASE)
+#define INT_730_UPLD		(24 + IH2_BASE)
+#define INT_730_RTC_TIMER	(25 + IH2_BASE)
+#define INT_730_RTC_ALARM	(26 + IH2_BASE)
+#define INT_730_USB_HHC_1	(27 + IH2_BASE)
+#define INT_730_USB_HHC_2	(28 + IH2_BASE)
+#define INT_730_USB_GENI	(29 + IH2_BASE)
+#define INT_730_USB_OTG		(30 + IH2_BASE)
+#define INT_730_CAMERA_IF	(31 + IH2_BASE)
+#define INT_730_RNG		(32 + IH2_BASE)
+#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_730_DBB_RF_EN	(34 + IH2_BASE)
+#define INT_730_MPUIO_KEYPAD	(35 + IH2_BASE)
+#define INT_730_SHA1_MD5	(36 + IH2_BASE)
+#define INT_730_SPI_100K_2	(37 + IH2_BASE)
+#define INT_730_RNG_IDLE	(38 + IH2_BASE)
+#define INT_730_MPUIO		(39 + IH2_BASE)
+#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF	(40 + IH2_BASE)
+#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_730_LLPC_OE_RISING	(42 + IH2_BASE)
+#define INT_730_LLPC_VSYNC	(43 + IH2_BASE)
+#define INT_730_WAKE_UP_REQ	(46 + IH2_BASE)
+#define INT_730_DMA_CH6		(53 + IH2_BASE)
+#define INT_730_DMA_CH7		(54 + IH2_BASE)
+#define INT_730_DMA_CH8		(55 + IH2_BASE)
+#define INT_730_DMA_CH9		(56 + IH2_BASE)
+#define INT_730_DMA_CH10	(57 + IH2_BASE)
+#define INT_730_DMA_CH11	(58 + IH2_BASE)
+#define INT_730_DMA_CH12	(59 + IH2_BASE)
+#define INT_730_DMA_CH13	(60 + IH2_BASE)
+#define INT_730_DMA_CH14	(61 + IH2_BASE)
+#define INT_730_DMA_CH15	(62 + IH2_BASE)
+#define INT_730_NAND		(63 + IH2_BASE)
+
+/* OMAP-730 differences */
+#ifdef CONFIG_ARCH_OMAP730
+#undef	INT_IH2_IRQ
+#define INT_IH2_IRQ		INT_730_IH2_IRQ
+#undef	INT_KEYBOARD
+#define INT_KEYBOARD		INT_730_MPUIO_KEYPAD
+#undef	INT_UART1
+#define INT_UART1		INT_730_UART_MODEM_1
+#undef	INT_UART2
+#define INT_UART2		INT_730_UART_MODEM_IRDA_2
+#undef	INT_MPUIO
+#define INT_MPUIO		INT_730_MPUIO
+#undef	INT_RTC_TIMER
+#define INT_RTC_TIMER		INT_730_RTC_TIMER
+#undef	INT_RTC_ALARM
+#define INT_RTC_ALARM		INT_730_RTC_ALARM
+#endif
+
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES	192
+#define IH_GPIO_BASE		(128 + IH2_BASE)
+#define IH_MPUIO_BASE		(OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define IH_BOARD_BASE		(16 + IH_MPUIO_BASE)
+
+#ifndef __ASSEMBLY__
+extern void omap_init_irq(void);
+#endif
+
+/*
+ * The definition of NR_IRQS is in board-specific header file, which is
+ * included via hardware.h
+ */
+#include <asm/arch/hardware.h>
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/memory.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,92 @@
+/*
+ * linux/include/asm-arm/arch-omap/memory.h
+ *
+ * Memory map for OMAP-1510 and 1610
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE		(0xbf000000UL)
+#define TASK_SIZE_26		(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE	(0x40000000)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET		(0xC0000000UL)
+#define PHYS_OFFSET		(0x10000000UL)
+
+/*
+ * OMAP-1510 Local Bus address offset
+ */
+#define OMAP1510_LB_OFFSET	(0x30000000UL)
+
+/*
+ * The DRAM is contiguous.
+ */
+#define __virt_to_phys__is_a_macro
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt__is_a_macro
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
+
+/*
+ * Conversion between SDRAM and fake PCI bus, used by USB
+ * NOTE: Physical address must be converted to Local Bus address
+ *	 on OMAP-1510 only
+ */
+#define __virt_to_bus__is_a_macro
+#define __bus_to_virt__is_a_macro
+
+/*
+ * Bus address is physical address, except for OMAP-1510 Local Bus.
+ */
+#define __virt_to_bus(x)	__virt_to_phys(x)
+#define __bus_to_virt(x)	__phys_to_virt(x)
+
+/*
+ * OMAP-1510 bus address is translated into a Local Bus address if the
+ * OMAP bus type is lbus. See dmadev_uses_omap_lbus().
+ */
+#ifdef CONFIG_ARCH_OMAP1510
+#define bus_to_lbus(x)	((x) + (OMAP1510_LB_OFFSET - PHYS_OFFSET))
+#define lbus_to_bus(x)	((x) - (OMAP1510_LB_OFFSET - PHYS_OFFSET))
+#endif
+
+#define PHYS_TO_NID(addr) (0)
+#endif
+
diff -Nru a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/mux.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,462 @@
+/*
+ * linux/include/asm-arm/arch-omap/mux.h
+ *
+ * Table of the Omap register configurations for the FUNC_MUX and
+ * PULL_DWN combinations.
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: Please use the following naming style for new pin entries.
+ *	 For example, W8_1610_MMC2_DAT0, where:
+ *	 - W8	     = ball
+ *	 - 1610	     = 1510 or 1610, none if common for both 1510 and 1610
+ *	 - MMC2_DAT0 = function
+ *
+ * Change log:
+ *   Added entry for the I2C interface. (02Feb 2004)
+ *   Copyright (C) 2004 Texas Instruments
+ *
+ *   Added entry for the keypad and uwire CS1. (09Mar 2004)
+ *   Copyright (C) 2004 Texas Instruments
+ *
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+#define PU_PD_SEL_NA	0	/* No pu_pd reg availabe */
+
+#define DEBUG_MUX
+
+#ifdef DEBUG_MUX
+#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
+					.mux_reg = FUNC_MUX_CTRL_##reg, \
+					.mask_offset = mode_offset, \
+					.mask = mode,
+
+#define PULL_REG(reg, bit, status)	.pull_name = "PULL_DWN_CTRL_"#reg, \
+					.pull_reg = PULL_DWN_CTRL_##reg, \
+					.pull_bit = bit, \
+					.pull_val = status,
+
+#define PU_PD_REG(reg, status)		.pu_pd_name = "PU_PD_SEL_"#reg, \
+					.pu_pd_reg = PU_PD_SEL_##reg, \
+					.pu_pd_val = status,
+
+#else
+
+#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
+					.mask_offset = mode_offset, \
+					.mask = mode,
+
+#define PULL_REG(reg, bit, status)	.pull_reg = PULL_DWN_CTRL_##reg, \
+					.pull_bit = bit, \
+					.pull_val = status,
+
+#define PU_PD_REG(reg, status)		.pu_pd_reg = PU_PD_SEL_##reg, \
+					.pu_pd_val = status,
+
+#endif // DEBUG_MUX
+
+#define MUX_CFG(desc, mux_reg, mode_offset, mode,	\
+		pull_reg, pull_bit, pull_status,	\
+		pu_pd_reg, pu_pd_status, debug_status)	\
+{							\
+	.name =	 desc,					\
+	.debug = debug_status,				\
+	MUX_REG(mux_reg, mode_offset, mode)		\
+	PULL_REG(pull_reg, pull_bit, pull_status)	\
+	PU_PD_REG(pu_pd_reg, pu_pd_status)		\
+},
+
+#define PULL_DISABLED	0
+#define PULL_ENABLED	1
+
+#define PULL_DOWN	0
+#define PULL_UP		1
+
+typedef struct {
+	char *name;
+	unsigned char busy;
+	unsigned char debug;
+
+	const char *mux_reg_name;
+	const unsigned int mux_reg;
+	const unsigned char mask_offset;
+	const unsigned char mask;
+
+	const char *pull_name;
+	const unsigned int pull_reg;
+	const unsigned char pull_val;
+	const unsigned char pull_bit;
+
+	const char *pu_pd_name;
+	const unsigned int pu_pd_reg;
+	const unsigned char pu_pd_val;
+} reg_cfg_set;
+
+/*
+ * Lookup table for FUNC_MUX and PULL_DWN register combinations for each
+ * device. See also reg_cfg_table below for the register values.
+ */
+typedef enum {
+	/* UART1 (BT_UART_GATING)*/
+	UART1_TX = 0,
+	UART1_RTS,
+
+	/* UART2 (COM_UART_GATING)*/
+	UART2_TX,
+	UART2_RX,
+	UART2_CTS,
+	UART2_RTS,
+
+	/* UART3 (GIGA_UART_GATING) */
+	UART3_TX,
+	UART3_RX,
+	UART3_CTS,
+	UART3_RTS,
+	UART3_CLKREQ,
+	UART3_BCLK,	/* 12MHz clock out */
+
+	/* USB master generic */
+	R18_USB_VBUS,
+	R18_1510_USB_GPIO0,
+	W4_USB_PUEN,
+	W4_USB_CLKO,
+
+	/* USB1 master */
+	USB1_SUSP,
+	USB1_SEO,
+	USB1_TXEN,
+	USB1_TXD,
+	USB1_VP,
+	USB1_VM,
+	USB1_RCV,
+	USB1_SPEED,
+
+	/* USB2 master */
+	USB2_SUSP,
+	USB2_VP,
+	USB2_TXEN,
+	USB2_VM,
+	USB2_RCV,
+	USB2_SEO,
+	USB2_TXD,
+
+	/* OMAP-1510 GPIO */
+	R18_1510_GPIO0,
+	R19_1510_GPIO1,
+	M14_1510_GPIO2,
+
+	/* MPUIO */
+	MPUIO2,
+	MPUIO4,
+	MPUIO5,
+	T20_1610_MPUIO5,
+	W11_1610_MPUIO6,
+	V10_1610_MPUIO7,
+	W11_1610_MPUIO9,
+	V10_1610_MPUIO10,
+	W10_1610_MPUIO11,
+	E20_1610_MPUIO13,
+	U20_1610_MPUIO14,
+	E19_1610_MPUIO15,
+
+	/* MCBSP2 */
+	MCBSP2_CLKR,
+	MCBSP2_CLKX,
+	MCBSP2_DR,
+	MCBSP2_DX,
+	MCBSP2_FSR,
+	MCBSP2_FSX,
+
+	/* MCBSP3 */
+	MCBSP3_CLKX,
+
+	/* Misc ballouts */
+	BALLOUT_V8_ARMIO3,
+
+	/* OMAP-1610 MMC2 */
+	W8_1610_MMC2_DAT0,
+	V8_1610_MMC2_DAT1,
+	W15_1610_MMC2_DAT2,
+	R10_1610_MMC2_DAT3,
+	Y10_1610_MMC2_CLK,
+	Y8_1610_MMC2_CMD,
+	V9_1610_MMC2_CMDDIR,
+	V5_1610_MMC2_DATDIR0,
+	W19_1610_MMC2_DATDIR1,
+	R18_1610_MMC2_CLKIN,
+
+	/* OMAP-1610 External Trace Interface */
+	M19_1610_ETM_PSTAT0,
+	L15_1610_ETM_PSTAT1,
+	L18_1610_ETM_PSTAT2,
+	L19_1610_ETM_D0,
+	J19_1610_ETM_D6,
+	J18_1610_ETM_D7,
+
+	/* OMAP-1610 GPIO */
+	P20_1610_GPIO4,
+	V9_1610_GPIO7,
+	N19_1610_GPIO13,
+	P10_1610_GPIO22,
+	V5_1610_GPIO24,
+	AA20_1610_GPIO_41,
+
+	/* OMAP-1610 uWire */
+	V19_1610_UWIRE_SCLK,
+	U18_1610_UWIRE_SDI,
+	W21_1610_UWIRE_SDO,
+	N14_1610_UWIRE_CS0,
+	P15_1610_UWIRE_CS0,
+	N15_1610_UWIRE_CS1,
+
+	/* First MMC */
+	MMC_CMD,
+	MMC_DAT1,
+	MMC_DAT2,
+	MMC_DAT0,
+	MMC_CLK,
+	MMC_DAT3,
+
+	/* OMAP-1610 USB0 alternate pin configuration */
+	W9_USB0_TXEN,
+	AA9_USB0_VP,
+	Y5_USB0_RCV,
+	R9_USB0_VM,
+	V6_USB0_TXD,
+	W5_USB0_SE0,
+	V9_USB0_SPEED,
+	V9_USB0_SUSP,
+
+	/* USB2 */
+	W9_USB2_TXEN,
+	AA9_USB2_VP,
+	Y5_USB2_RCV,
+	R9_USB2_VM,
+	V6_USB2_TXD,
+	W5_USB2_SE0,
+
+	/* UART1 1610 */
+
+	R13_1610_UART1_TX,
+	V14_1610_UART1_RX,
+	R14_1610_UART1_CTS,
+	AA15_1610_UART1_RTS,
+
+	/* I2C OMAP-1610 */
+	I2C_SCL,
+	I2C_SDA,
+
+	/* Keypad */
+	F18_1610_KBC0,
+	D20_1610_KBC1,
+	D19_1610_KBC2,
+	E18_1610_KBC3,
+	C21_1610_KBC4,
+	G18_1610_KBR0,
+	F19_1610_KBR1,
+	H14_1610_KBR2,
+	E20_1610_KBR3,
+	E19_1610_KBR4,
+	N19_1610_KBR5,
+
+} reg_cfg_t;
+
+#ifdef __MUX_C__
+
+/*
+ * Table of various FUNC_MUX and PULL_DWN combinations for each device.
+ * See also reg_cfg_t above for the lookup table.
+ */
+static reg_cfg_set reg_cfg_table[] = {
+/*
+ *	 description		mux  mode   mux	 pull pull  pull  pu_pd	 pu  dbg
+ *				reg  offset mode reg  bit   ena	  reg
+ */
+MUX_CFG("UART1_TX",		 9,   21,    1,	  2,   3,   0,	 NA,	 0,  0)
+MUX_CFG("UART1_RTS",		 9,   12,    1,	  2,   0,   0,	 NA,	 0,  0)
+
+/* UART2 (COM_UART_GATING), conflicts with USB2 */
+MUX_CFG("UART2_TX",		 C,   27,    1,	  3,   3,   0,	 NA,	 0,  0)
+MUX_CFG("UART2_RX",		 C,   18,    0,	  3,   1,   1,	 NA,	 0,  0)
+MUX_CFG("UART2_CTS",		 C,   21,    0,	  3,   1,   1,	 NA,	 0,  0)
+MUX_CFG("UART2_RTS",		 C,   24,    1,	  3,   2,   0,	 NA,	 0,  0)
+
+/* UART3 (GIGA_UART_GATING) */
+MUX_CFG("UART3_TX",		 6,    0,    1,	  0,  30,   0,	 NA,	 0,  0)
+MUX_CFG("UART3_RX",		 6,    3,    0,	  0,  31,   1,	 NA,	 0,  0)
+MUX_CFG("UART3_CTS",		 5,   12,    2,	  0,  24,   0,	 NA,	 0,  0)
+MUX_CFG("UART3_RTS",		 5,   15,    2,	  0,  25,   0,	 NA,	 0,  0)
+MUX_CFG("UART3_CLKREQ",		 9,   27,    0,	  2,   5,   0,	 NA,	 0,  0)
+MUX_CFG("UART3_BCLK",		 A,    0,    0,	  2,   6,   0,	 NA,	 0,  0)
+
+/* USB internal master generic */
+MUX_CFG("R18_USB_VBUS",		 7,    9,    2,	  1,  11,   0,	 NA,	 0,  1)
+MUX_CFG("R18_1510_USB_GPIO0",	 7,    9,    0,	  1,  11,   1,	 NA,	 0,  1)
+MUX_CFG("W4_USB_PUEN",		 D,    3,    0,	  3,   5,   1,	 NA,	 0,  1)
+MUX_CFG("W4_USB_CLKO",		 D,    3,    1,	  3,   5,   0,	 NA,	 0,  1)
+
+/* USB1 master */
+MUX_CFG("USB1_SUSP",		 8,   27,    2,	  1,  27,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_SE0",		 9,    0,    2,	  1,  28,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_TXEN",		 9,    3,    2,	  1,  29,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_TXD",		 9,   24,    1,	  2,   4,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_VP",		 A,    3,    1,	  2,   7,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_VM",		 A,    6,    1,	  2,   8,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_RCV",		 A,    9,    1,	  2,   9,   0,	 NA,	 0,  1)
+MUX_CFG("USB1_SPEED",		 A,   12,    2,	  2,  10,   0,	 NA,	 0,  1)
+
+/* USB2 master */
+MUX_CFG("USB2_SUSP",		 B,    3,    1,	  2,  17,   0,	 NA,	 0,  1)
+MUX_CFG("USB2_VP",		 B,    6,    1,	  2,  18,   0,	 NA,	 0,  1)
+MUX_CFG("USB2_TXEN",		 B,    9,    1,	  2,  19,   0,	 NA,	 0,  1)
+MUX_CFG("USB2_VM",		 C,   18,    1,	  3,   0,   0,	 NA,	 0,  1)
+MUX_CFG("USB2_RCV",		 C,   21,    1,	  3,   1,   0,	 NA,	 0,  1)
+MUX_CFG("USB2_SE0",		 C,   24,    2,	  3,   2,   0,	 NA,	 0,  1)
+MUX_CFG("USB2_TXD",		 C,   27,    2,	  3,   3,   0,	 NA,	 0,  1)
+
+/* OMAP-1510 GPIO */
+MUX_CFG("R18_1510_GPIO0",	 7,    9,   0,	  1,  11,   1,	  0,	 0,  1)
+MUX_CFG("R19_1510_GPIO1",	 7,    6,   0,	  1,  10,   1,	  0,	 0,  1)
+MUX_CFG("M14_1510_GPIO2",	 7,    3,   0,	  1,   9,   1,	  0,	 0,  1)
+
+/* MPUIO */
+MUX_CFG("MPUIO2",		 7,   18,    0,	  1,   1,   1,	 NA,	 0,  1)
+MUX_CFG("MPUIO4",		 7,   15,    0,	  1,  13,   1,	 NA,	 0,  1)
+MUX_CFG("MPUIO5",		 7,   12,    0,	  1,  12,   1,	 NA,	 0,  1)
+
+MUX_CFG("T20_1610_MPUIO5",	 7,   12,    0,	  1,  12,   0,	  3,	 0,  1)
+MUX_CFG("W11_1610_MPUIO6",	10,   15,    2,	  3,   8,   0,	  3,	 0,  1)
+MUX_CFG("V10_1610_MPUIO7",	 A,   24,    2,	  2,  14,   0,	  2,	 0,  1)
+MUX_CFG("W11_1610_MPUIO9",	10,   15,    1,	  3,   8,   0,	  3,	 0,  1)
+MUX_CFG("V10_1610_MPUIO10",	 A,   24,    1,	  2,  14,   0,	  2,	 0,  1)
+MUX_CFG("W10_1610_MPUIO11",	 A,   18,    2,	  2,  11,   0,	  2,	 0,  1)
+MUX_CFG("E20_1610_MPUIO13",	 3,   21,    1,	  0,   7,   0,	  0,	 0,  1)
+MUX_CFG("U20_1610_MPUIO14",	 9,    6,    6,	  0,  30,   0,	  0,	 0,  1)
+MUX_CFG("E19_1610_MPUIO15",	 3,   18,    1,	  0,   6,   0,	  0,	 0,  1)
+
+/* MCBSP2 */
+MUX_CFG("MCBSP2_CLKR",		 C,    6,    0,	  2,  27,   1,	 NA,	 0,  1)
+MUX_CFG("MCBSP2_CLKX",		 C,    9,    0,	  2,  29,   1,	 NA,	 0,  1)
+MUX_CFG("MCBSP2_DR",		 C,    0,    0,	  2,  26,   1,	 NA,	 0,  1)
+MUX_CFG("MCBSP2_DX",		 C,   15,    0,	  2,  31,   1,	 NA,	 0,  1)
+MUX_CFG("MCBSP2_FSR",		 C,   12,    0,	  2,  30,   1,	 NA,	 0,  1)
+MUX_CFG("MCBSP2_FSX",		 C,    3,    0,	  2,  27,   1,	 NA,	 0,  1)
+
+/* MCBSP3 NOTE: Mode must 1 for clock */
+MUX_CFG("MCBSP3_CLKX",		 9,    3,    1,	  1,  29,   0,	 NA,	 0,  1)
+
+/* Misc ballouts */
+MUX_CFG("BALLOUT_V8_ARMIO3",	 B,   18,    0,	  2,  25,   1,	 NA,	 0,  1)
+
+/* OMAP-1610 MMC2 */
+MUX_CFG("W8_1610_MMC2_DAT0",	 B,   21,    6,	  2,  23,   1,	  2,	 1,  1)
+MUX_CFG("V8_1610_MMC2_DAT1",	 B,   27,    6,	  2,  25,   1,	  2,	 1,  1)
+MUX_CFG("W15_1610_MMC2_DAT2",	 9,   12,    6,	  2,   5,   1,	  2,	 1,  1)
+MUX_CFG("R10_1610_MMC2_DAT3",	 B,   18,    6,	  2,  22,   1,	  2,	 1,  1)
+MUX_CFG("Y10_1610_MMC2_CLK",	 B,    3,    6,	  2,  17,   0,	  2,	 0,  1)
+MUX_CFG("Y8_1610_MMC2_CMD",	 B,   24,    6,	  2,  24,   1,	  2,	 1,  1)
+MUX_CFG("V9_1610_MMC2_CMDDIR",	 B,   12,    6,	  2,  20,   0,	  2,	 1,  1)
+MUX_CFG("V5_1610_MMC2_DATDIR0",	 B,   15,    6,	  2,  21,   0,	  2,	 1,  1)
+MUX_CFG("W19_1610_MMC2_DATDIR1", 8,   15,    6,	  1,  23,   0,	  1,	 1,  1)
+MUX_CFG("R18_1610_MMC2_CLKIN",	 7,    9,    6,	  1,  11,   0,	  1,	11,  1)
+
+/* OMAP-1610 External Trace Interface */
+MUX_CFG("M19_1610_ETM_PSTAT0",	 5,   27,    1,	  0,  29,   0,	  0,	 0,  1)
+MUX_CFG("L15_1610_ETM_PSTAT1",	 5,   24,    1,	  0,  28,   0,	  0,	 0,  1)
+MUX_CFG("L18_1610_ETM_PSTAT2",	 5,   21,    1,	  0,  27,   0,	  0,	 0,  1)
+MUX_CFG("L19_1610_ETM_D0",	 5,   18,    1,	  0,  26,   0,	  0,	 0,  1)
+MUX_CFG("J19_1610_ETM_D6",	 5,    0,    1,	  0,  20,   0,	  0,	 0,  1)
+MUX_CFG("J18_1610_ETM_D7",	 5,   27,    1,	  0,  19,   0,	  0,	 0,  1)
+
+/* OMAP-1610 GPIO */
+MUX_CFG("P20_1610_GPIO4",	 6,   27,    0,	  1,   7,   0,	  1,	 1,  1)
+MUX_CFG("V9_1610_GPIO7",	 B,   12,    1,	  2,  20,   0,	  2,	 1,  1)
+MUX_CFG("N19_1610_GPIO13",	 6,   12,    0,	  1,   2,   0,	  1,	 1,  1)
+MUX_CFG("P10_1610_GPIO22",	 C,    0,    7,	  2,  26,   0,	  2,	 1,  1)
+MUX_CFG("V5_1610_GPIO24",	 B,   15,    7,	  2,  21,   0,	  2,	 1,  1)
+MUX_CFG("AA20_1610_GPIO_41",	 9,    9,    7,	  1,  31,   0,	  1,	 1,  1)
+
+/* OMAP-1610 uWire */
+MUX_CFG("V19_1610_UWIRE_SCLK",	 8,    6,    0,	  1,  20,   0,	  1,	 1,  1)
+MUX_CFG("U18_1610_UWIRE_SDI",	 8,    0,    0,	  1,  18,   0,	  1,	 1,  1)
+MUX_CFG("W21_1610_UWIRE_SDO",	 8,    3,    0,	  1,  19,   0,	  1,	 1,  1)
+MUX_CFG("N14_1610_UWIRE_CS0",	 8,    9,    1,	  1,  21,   0,	  1,	 1,  1)
+MUX_CFG("P15_1610_UWIRE_CS3",	 8,   12,    1,	  1,  22,   0,	  1,	 1,  1)
+MUX_CFG("N15_1610_UWIRE_CS1",	 7,   18,    2,	  0,   0,   0,	  0,	 0,  0)
+
+/* First MMC interface, same on 1510 and 1610 */
+MUX_CFG("MMC_CMD",		 A,   27,    0,	  2,  15,   1,	  2,	 1,  1)
+MUX_CFG("MMC_DAT1",		 A,   24,    0,	  2,  14,   1,	  2,	 1,  1)
+MUX_CFG("MMC_DAT2",		 A,   18,    0,	  2,  12,   1,	  2,	 1,  1)
+MUX_CFG("MMC_DAT0",		 B,    0,    0,	  2,  16,   1,	  2,	 1,  1)
+MUX_CFG("MMC_CLK",		 A,   21,    0,	  0,   0,   0,	  0,	 0,  1)
+MUX_CFG("MMC_DAT3",		10,   15,    0,	  3,   8,   1,	  3,	 1,  1)
+
+/* OMAP-1610 USB0 alternate configuration */
+MUX_CFG("W9_USB0_TXEN",		 B,   9,     5,	  2,  19,   0,	  2,	 0,  1)
+MUX_CFG("AA9_USB0_VP",		 B,   6,     5,	  2,  18,   0,	  2,	 0,  1)
+MUX_CFG("Y5_USB0_RCV",		 C,  21,     5,	  3,   1,   0,	  1,	 0,  1)
+MUX_CFG("R9_USB0_VM",		 C,  18,     5,	  3,   0,   0,	  3,	 0,  1)
+MUX_CFG("V6_USB0_TXD",		 C,  27,     5,	  3,   3,   0,	  3,	 0,  1)
+MUX_CFG("W5_USB0_SE0",		 C,  24,     5,	  3,   2,   0,	  3,	 0,  1)
+MUX_CFG("V9_USB0_SPEED",	 B,  12,     5,	  2,  20,   0,	  2,	 0,  1)
+MUX_CFG("Y10_USB0_SUSP",	 B,   3,     5,	  2,  17,   0,	  2,	 0,  1)
+
+/* USB2 interface */
+MUX_CFG("W9_USB2_TXEN",		 B,   9,     1,	  0,   0,   0,	 NA,	 0,  1)
+MUX_CFG("AA9_USB2_VP",		 B,   6,     1,	  0,   0,   0,	 NA,	 0,  1)
+MUX_CFG("Y5_USB2_RCV",		 C,  21,     1,	  0,   0,   0,	 NA,	 0,  1)
+MUX_CFG("R8_USB2_VM",		 C,  18,     1,	  0,   0,   0,	 NA,	 0,  1)
+MUX_CFG("V6_USB2_TXD",		 C,  27,     2,	  0,   0,   0,	 NA,	 0,  1)
+MUX_CFG("W5_USB2_SE0",		 C,  24,     2,	  0,   0,   0,	 NA,	 0,  1)
+
+
+/* UART1 */
+MUX_CFG("R13_1610_UART1_TX",	 A,  12,     6,	  2,  10,   0,	  2,	10,  1)
+MUX_CFG("V14_1610_UART1_RX",	 9,  18,     0,	  2,   2,   0,	  2,	 2,  1)
+MUX_CFG("R14_1610_UART1_CTS",	 9,  15,     0,	  2,   1,   0,	  2,	 1,  1)
+MUX_CFG("AA15_1610_UART1_RTS",	 9,  12,     1,	  2,   0,   0,	  2,	 0,  1)
+
+/* I2C interface */
+MUX_CFG("I2C_SCL",		 7,  24,     0,	  0,   0,   0,	  0,	 0,  0)
+MUX_CFG("I2C_SDA",		 7,  27,     0,	  0,   0,   0,	  0,	 0,  0)
+
+/* Keypad */
+MUX_CFG("F18_1610_KBC0",	 3,  15,     0,	  0,   5,   1,	  0,	 0,  0)
+MUX_CFG("D20_1610_KBC1",	 3,  12,     0,	  0,   4,   1,	  0,	 0,  0)
+MUX_CFG("D19_1610_KBC2",	 3,   9,     0,	  0,   3,   1,	  0,	 0,  0)
+MUX_CFG("E18_1610_KBC3",	 3,   6,     0,	  0,   2,   1,	  0,	 0,  0)
+MUX_CFG("C21_1610_KBC4",	 3,   3,     0,	  0,   1,   1,	  0,	 0,  0)
+MUX_CFG("G18_1610_KBR0",	 4,   0,     0,	  0,   10,  1,	  0,	 1,  0)
+MUX_CFG("F19_1610_KBR1",	 3,   27,    0,	  0,   9,   1,	  0,	 1,  0)
+MUX_CFG("H14_1610_KBR2",	 3,   24,    0,	  0,   8,   1,	  0,	 1,  0)
+MUX_CFG("E20_1610_KBR3",	 3,   21,    0,	  0,   7,   1,	  0,	 1,  0)
+MUX_CFG("E19_1610_KBR4",	 3,   18,    0,	  0,   6,   1,	  0,	 1,  0)
+MUX_CFG("N19_1610_KBR5",	 6,  12,     1,	  1,   2,   1,	  1,	 1,  0)
+
+};
+
+#endif	/* __MUX_C__ */
+
+extern int omap_cfg_reg(reg_cfg_t reg_cfg);
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/omap-h2.h b/include/asm-arm/arch-omap/omap-h2.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/omap-h2.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-arm/arch-omap/omap-h2.h
+ *
+ * Hardware definitions for TI OMAP1610 H2 board.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H2_H
+#define __ASM_ARCH_OMAP_H2_H
+
+/* Placeholder for H2 specific defines */
+
+#endif /*  __ASM_ARCH_OMAP_H2_H */
+
diff -Nru a/include/asm-arm/arch-omap/omap-innovator.h b/include/asm-arm/arch-omap/omap-innovator.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/omap-innovator.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,214 @@
+/*
+ * linux/include/asm-arm/arch-omap/omap-innovator.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
+#define __ASM_ARCH_OMAP_INNOVATOR_H
+
+#if defined (CONFIG_ARCH_OMAP1510)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510P1_FPGA_BASE			0xE8000000	/* Virtual */
+#define OMAP1510P1_FPGA_SIZE			SZ_4K
+#define OMAP1510P1_FPGA_START			0x08000000	/* Physical */
+
+/* Revision */
+#define OMAP1510P1_FPGA_REV_LOW			(OMAP1510P1_FPGA_BASE + 0x0)
+#define OMAP1510P1_FPGA_REV_HIGH		(OMAP1510P1_FPGA_BASE + 0x1)
+
+#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL	(OMAP1510P1_FPGA_BASE + 0x2)
+#define OMAP1510P1_FPGA_LED_DIGIT		(OMAP1510P1_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI			(OMAP1510P1_FPGA_BASE + 0x4)
+#define OMAP1510P1_FPGA_POWER			(OMAP1510P1_FPGA_BASE + 0x5)
+
+/* Interrupt status */
+#define OMAP1510P1_FPGA_ISR_LO			(OMAP1510P1_FPGA_BASE + 0x6)
+#define OMAP1510P1_FPGA_ISR_HI			(OMAP1510P1_FPGA_BASE + 0x7)
+
+/* Interrupt mask */
+#define OMAP1510P1_FPGA_IMR_LO			(OMAP1510P1_FPGA_BASE + 0x8)
+#define OMAP1510P1_FPGA_IMR_HI			(OMAP1510P1_FPGA_BASE + 0x9)
+
+/* Reset registers */
+#define OMAP1510P1_FPGA_HOST_RESET		(OMAP1510P1_FPGA_BASE + 0xa)
+#define OMAP1510P1_FPGA_RST			(OMAP1510P1_FPGA_BASE + 0xb)
+
+#define OMAP1510P1_FPGA_AUDIO			(OMAP1510P1_FPGA_BASE + 0xc)
+#define OMAP1510P1_FPGA_DIP			(OMAP1510P1_FPGA_BASE + 0xe)
+#define OMAP1510P1_FPGA_FPGA_IO			(OMAP1510P1_FPGA_BASE + 0xf)
+#define OMAP1510P1_FPGA_UART1			(OMAP1510P1_FPGA_BASE + 0x14)
+#define OMAP1510P1_FPGA_UART2			(OMAP1510P1_FPGA_BASE + 0x15)
+#define OMAP1510P1_FPGA_OMAP1510_STATUS		(OMAP1510P1_FPGA_BASE + 0x16)
+#define OMAP1510P1_FPGA_BOARD_REV		(OMAP1510P1_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA			(OMAP1510P1_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS			(OMAP1510P1_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL			(OMAP1510P1_FPGA_BASE + 0x102)
+
+#define OMAP1510P1_FPGA_TOUCHSCREEN		(OMAP1510P1_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO			(OMAP1510P1_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO		(OMAP1510P1_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI		(OMAP1510P1_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO		(OMAP1510P1_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI		(OMAP1510P1_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO		(OMAP1510P1_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI		(OMAP1510P1_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL		(OMAP1510P1_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL		(OMAP1510P1_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2			(OMAP1510P1_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2			(OMAP1510P1_FPGA_BASE + 0x210)
+
+#define OMAP1510P1_FPGA_ETHR_START		(OMAP1510P1_FPGA_START + 0x300)
+#define OMAP1510P1_FPGA_ETHR_BASE		(OMAP1510P1_FPGA_BASE + 0x300)
+
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510P1_FPGA_RESET_VALUE		0x42
+
+#define OMAP1510P1_FPGA_PCR_IF_PD0		(1 << 7)
+#define OMAP1510P1_FPGA_PCR_COM2_EN		(1 << 6)
+#define OMAP1510P1_FPGA_PCR_COM1_EN		(1 << 5)
+#define OMAP1510P1_FPGA_PCR_EXP_PD0		(1 << 4)
+#define OMAP1510P1_FPGA_PCR_EXP_PD1		(1 << 3)
+#define OMAP1510P1_FPGA_PCR_48MHZ_CLK		(1 << 2)
+#define OMAP1510P1_FPGA_PCR_4MHZ_CLK		(1 << 1)
+#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0		(1 << 0)
+
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define FPGA_HID_SCLK	(1<<0)	/* output */
+#define FPGA_HID_MOSI	(1<<1)	/* output */
+#define FPGA_HID_nSS	(1<<2)	/* output 0/1 chip idle/select */
+#define FPGA_HID_nHSUS	(1<<3)	/* output 0/1 host active/suspended */
+#define FPGA_HID_MISO	(1<<4)	/* input */
+#define FPGA_HID_ATN	(1<<5)	/* input  0/1 chip idle/ATN */
+#define FPGA_HID_rsrvd	(1<<6)
+#define FPGA_HID_RESETn (1<<7)	/* output - 0/1 USAR reset/run */
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE			D256M_1X16_4B
+#endif
+
+#define OMAP1510P1_IMIF_PRI_VALUE		0x00
+#define OMAP1510P1_EMIFS_PRI_VALUE		0x00
+#define OMAP1510P1_EMIFF_PRI_VALUE		0x00
+
+/*
+ * These definitions define an area of FLASH set aside
+ * for the use of MTD/JFFS2. This is the area of flash
+ * that a JFFS2 filesystem will reside which is mounted
+ * at boot with the "root=/dev/mtdblock/0 rw"
+ * command line option. The flash address used here must
+ * fall within the legal range defined by rrload for storing
+ * the filesystem component. This address will be sufficiently
+ * deep into the overall flash range to avoid the other
+ * components also stored in flash such as the bootloader,
+ * the bootloader params, and the kernel.
+ * The SW2 settings for the map below are:
+ * 1 off, 2 off, 3 on, 4 off.
+ */
+
+/* Intel flash_0, partitioned as expected by rrload */
+#define OMAP_FLASH_0_BASE	0xD8000000
+#define OMAP_FLASH_0_START	0x00000000
+#define OMAP_FLASH_0_SIZE	SZ_16M
+
+/* Intel flash_1, used for cramfs or other flash file systems */
+#define OMAP_FLASH_1_BASE	0xD9000000
+#define OMAP_FLASH_1_START	0x01000000
+#define OMAP_FLASH_1_SIZE	SZ_16M
+
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define INT_FPGA		(IH_GPIO_BASE + 13)
+
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define IH_FPGA_BASE		IH_BOARD_BASE
+#define INT_FPGA_ATN		(IH_FPGA_BASE + 0)
+#define INT_FPGA_ACK		(IH_FPGA_BASE + 1)
+#define INT_FPGA2		(IH_FPGA_BASE + 2)
+#define INT_FPGA3		(IH_FPGA_BASE + 3)
+#define INT_FPGA4		(IH_FPGA_BASE + 4)
+#define INT_FPGA5		(IH_FPGA_BASE + 5)
+#define INT_FPGA6		(IH_FPGA_BASE + 6)
+#define INT_FPGA7		(IH_FPGA_BASE + 7)
+#define INT_FPGA8		(IH_FPGA_BASE + 8)
+#define INT_FPGA9		(IH_FPGA_BASE + 9)
+#define INT_FPGA10		(IH_FPGA_BASE + 10)
+#define INT_FPGA11		(IH_FPGA_BASE + 11)
+#define INT_FPGA12		(IH_FPGA_BASE + 12)
+#define INT_ETHER		(IH_FPGA_BASE + 13)
+#define INT_FPGAUART1		(IH_FPGA_BASE + 14)
+#define INT_FPGAUART2		(IH_FPGA_BASE + 15)
+#define INT_FPGA_TS		(IH_FPGA_BASE + 16)
+#define INT_FPGA17		(IH_FPGA_BASE + 17)
+#define INT_FPGA_CAM		(IH_FPGA_BASE + 18)
+#define INT_FPGA_RTC_A		(IH_FPGA_BASE + 19)
+#define INT_FPGA_RTC_B		(IH_FPGA_BASE + 20)
+#define INT_FPGA_CD		(IH_FPGA_BASE + 21)
+#define INT_FPGA22		(IH_FPGA_BASE + 22)
+#define INT_FPGA23		(IH_FPGA_BASE + 23)
+
+#define NR_FPGA_IRQS		 24
+
+#define MAXIRQNUM		(IH_FPGA_BASE + NR_FPGA_IRQS - 1)
+#define MAXFIQNUM		MAXIRQNUM
+#define MAXSWINUM		MAXIRQNUM
+
+#define NR_IRQS			256
+
+#ifndef __ASSEMBLY__
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+#endif
+
+#elif defined (CONFIG_ARCH_OMAP1610)
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define OMAP1610_ETHR_BASE		0xE8000000
+#define OMAP1610_ETHR_SIZE		SZ_4K
+#define OMAP1610_ETHR_START		0x04000000
+
+/* Intel STRATA NOR flash at CS3 */
+#define OMAP1610_NOR_FLASH_BASE		0xD8000000
+#define OMAP1610_NOR_FLASH_SIZE		SZ_32M
+#define OMAP1610_NOR_FLASH_START	0x0C000000
+
+#define MAXIRQNUM			(IH_BOARD_BASE)
+#define MAXFIQNUM			MAXIRQNUM
+#define MAXSWINUM			MAXIRQNUM
+
+#define NR_IRQS				(MAXIRQNUM + 1)
+
+#else
+#error "Only OMAP1510 and OMAP1610 Innovator supported!"
+#endif
+#endif
diff -Nru a/include/asm-arm/arch-omap/omap-perseus2.h b/include/asm-arm/arch-omap/omap-perseus2.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/omap-perseus2.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,152 @@
+/*
+ *  linux/include/asm-arm/arch-omap/omap-perseus2.h
+ *
+ *  Copyright 2003 by Texas Instruments Incorporated
+ *    OMAP730 / P2-sample additions
+ *    Author: Jean Pihet
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H
+#define __ASM_ARCH_OMAP_P2SAMPLE_H
+
+#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2)
+
+/*
+ * NOTE:  ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER
+ *	  P2SAMPLE_ since they are specific to the EVM and not the chip.
+ */
+
+/* ---------------------------------------------------------------------------
+ *  OMAP730 Debug Board FPGA
+ * ---------------------------------------------------------------------------
+ *
+ */
+
+/* maps in the FPGA registers and the ETHR registers */
+#define OMAP730_FPGA_BASE		0xE8000000	/* VA */
+#define OMAP730_FPGA_SIZE		SZ_4K		/* SIZE */
+#define OMAP730_FPGA_START		0x04000000	/* PA */
+
+#define OMAP730_FPGA_ETHR_START		OMAP730_FPGA_START
+#define OMAP730_FPGA_ETHR_BASE		OMAP730_FPGA_BASE
+#define OMAP730_FPGA_FPGA_REV		(OMAP730_FPGA_BASE + 0x10)	/* FPGA Revision */
+#define OMAP730_FPGA_BOARD_REV		(OMAP730_FPGA_BASE + 0x12)	/* Board Revision */
+#define OMAP730_FPGA_GPIO		(OMAP730_FPGA_BASE + 0x14)	/* GPIO outputs */
+#define OMAP730_FPGA_LEDS		(OMAP730_FPGA_BASE + 0x16)	/* LEDs outputs */
+#define OMAP730_FPGA_MISC_INPUTS	(OMAP730_FPGA_BASE + 0x18)	/* Misc inputs */
+#define OMAP730_FPGA_LAN_STATUS		(OMAP730_FPGA_BASE + 0x1A)	/* LAN Status line */
+#define OMAP730_FPGA_LAN_RESET		(OMAP730_FPGA_BASE + 0x1C)	/* LAN Reset line */
+
+// LEDs definition on debug board (16 LEDs)
+#define OMAP730_FPGA_LED_CLAIMRELEASE	(1 << 15)
+#define OMAP730_FPGA_LED_STARTSTOP	(1 << 14)
+#define OMAP730_FPGA_LED_HALTED		(1 << 13)
+#define OMAP730_FPGA_LED_IDLE		(1 << 12)
+#define OMAP730_FPGA_LED_TIMER		(1 << 11)
+// cpu0 load-meter LEDs
+#define OMAP730_FPGA_LOAD_METER		(1 << 0)	// A bit of fun on our board ...
+#define OMAP730_FPGA_LOAD_METER_SIZE	11
+#define OMAP730_FPGA_LOAD_METER_MASK	((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1)
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE		D256M_1X16_4B
+#endif
+
+
+/*
+ * These definitions define an area of FLASH set aside
+ * for the use of MTD/JFFS2. This is the area of flash
+ * that a JFFS2 filesystem will reside which is mounted
+ * at boot with the "root=/dev/mtdblock/0 rw"
+ * command line option.
+ */
+
+/* Intel flash_0, partitioned as expected by rrload */
+#define OMAP_FLASH_0_BASE	0xD8000000	/* VA */
+#define OMAP_FLASH_0_START	0x00000000	/* PA */
+#define OMAP_FLASH_0_SIZE	SZ_32M
+
+/* 2.9.6 Traffic Controller Memory Interface Registers */
+#define OMAP_FLASH_CFG_0		0xfffecc10
+#define OMAP_FLASH_ACFG_0		0xfffecc50
+
+#define OMAP_FLASH_CFG_1		0xfffecc14
+#define OMAP_FLASH_ACFG_1		0xfffecc54
+
+/*
+ * Configuration Registers
+ */
+#define PERSEUS2_CONFIG_BASE	   0xfffe1000
+#define PERSEUS2_IO_CONF_0	   0xfffe1070
+#define PERSEUS2_IO_CONF_1	   0xfffe1074
+#define PERSEUS2_IO_CONF_2	   0xfffe1078
+#define PERSEUS2_IO_CONF_3	   0xfffe107c
+#define PERSEUS2_IO_CONF_4	   0xfffe1080
+#define PERSEUS2_IO_CONF_5	   0xfffe1084
+#define PERSEUS2_IO_CONF_6	   0xfffe1088
+#define PERSEUS2_IO_CONF_7	   0xfffe108c
+#define PERSEUS2_IO_CONF_8	   0xfffe1090
+#define PERSEUS2_IO_CONF_9	   0xfffe1094
+#define PERSEUS2_IO_CONF_10	   0xfffe1098
+#define PERSEUS2_IO_CONF_11	   0xfffe109c
+#define PERSEUS2_IO_CONF_12	   0xfffe10a0
+#define PERSEUS2_IO_CONF_13	   0xfffe10a4
+
+#define PERSEUS2_MODE_1		   0xfffe1010
+#define PERSEUS2_MODE_2		   0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define PERSEUS2_MODE2_OFFSET	   0x14
+
+/* DSP control: ICR registers */
+#define ICR_BASE		0xfffbb800
+/* M_CTL */
+#define DSP_M_CTL		((volatile __u16 *)0xfffbb804)
+/* DSP control: MMU registers */
+#define DSP_MMU_BASE		((volatile __u16 *)0xfffed200)
+
+/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */
+#define INT_ETHER		INT_730_MPU_EXT_NIRQ
+
+#define MAXIRQNUM		IH_BOARD_BASE
+#define MAXFIQNUM		MAXIRQNUM
+#define MAXSWINUM		MAXIRQNUM
+
+#define NR_IRQS			(MAXIRQNUM + 1)
+
+#ifndef __ASSEMBLY__
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+#endif
+
+/* PCC_UPLD control register: OMAP730 */
+#define PCC_UPLD_CTRL_REG_BASE	(0xfffe0900)
+#define PCC_UPLD_CTRL_REG	(volatile __u16 *)(PCC_UPLD_CTRL_REG_BASE + 0x00)
+
+#else
+#error "Only OMAP730 Perseus2 supported!"
+#endif
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/omap1510.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,54 @@
+/* linux/include/asm-arm/arch-omap/omap1510.h
+ *
+ * Hardware definitions for TI OMAP1510 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP1510_H
+#define __ASM_ARCH_OMAP1510_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP_SRAM_BASE		0xD0000000
+#define OMAP_SRAM_SIZE		(SZ_128K + SZ_64K)
+#define OMAP_SRAM_START		0x20000000
+
+#define OMAP_MCBSP1_BASE	0xE1011000
+#define OMAP_MCBSP1_SIZE	SZ_4K
+#define OMAP_MCBSP1_START	0xE1011000
+
+#define OMAP_MCBSP2_BASE	0xFFFB1000
+
+#define OMAP_MCBSP3_BASE	0xE1017000
+#define OMAP_MCBSP3_SIZE	SZ_4K
+#define OMAP_MCBSP3_START	0xE1017000
+
+#endif /*  __ASM_ARCH_OMAP1510_H */
+
diff -Nru a/include/asm-arm/arch-omap/omap1610.h b/include/asm-arm/arch-omap/omap1610.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/omap1610.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,73 @@
+/* linux/include/asm-arm/arch-omap/omap1610.h
+ *
+ * Hardware definitions for TI OMAP1610 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP1610_H
+#define __ASM_ARCH_OMAP1610_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP_SRAM_BASE		0xD0000000
+#define OMAP_SRAM_SIZE		(SZ_16K)
+#define OMAP_SRAM_START		0x20000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP_RESET_CONTROL	0xfffe1140
+#define ARM_IDLECT3		(CLKGEN_RESET_BASE + 0x24)
+#define CONF_VOLTAGE_CTRL_0	0xfffe1060
+#define CONF_VOLTAGE_VDDSHV6	(1 << 8)
+#define CONF_VOLTAGE_VDDSHV7	(1 << 9)
+#define CONF_VOLTAGE_VDDSHV8	(1 << 10)
+#define CONF_VOLTAGE_VDDSHV9	(1 << 11)
+#define SUBLVDS_CONF_VALID	(1 << 13)
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+
+#define OMAP_TIPB_SWITCH	0xfffbc800
+#define TIPB_BRIDGE_INT		0xfffeca00	/* Private TIPB_CNTL */
+#define PRIVATE_MPU_TIPB_CNTL	0xfffeca08
+#define TIPB_BRIDGE_EXT		0xfffed300	/* Public (Shared) TIPB_CNTL */
+#define PUBLIC_MPU_TIPB_CNTL	0xfffed308
+#define TIPB_SWITCH_CFG		OMAP_TIPB_SWITCH
+#define MMCSD2_SSW_MPU_CONF	(TIPB_SWITCH_CFG + 0x160)
+
+#endif /*  __ASM_ARCH_OMAP1610_H */
+
diff -Nru a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/omap730.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,50 @@
+/* linux/include/asm-arm/arch-omap/omap730.h
+ *
+ * Hardware definitions for TI OMAP730 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP730_H
+#define __ASM_ARCH_OMAP730_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP_SRAM_BASE		0xD0000000
+#define OMAP_SRAM_SIZE		(SZ_128K + SZ_64K + SZ_8K)
+#define OMAP_SRAM_START		0x20000000
+
+#define OMAP_MCBSP1_BASE	0xfffb1000
+#define OMAP_MCBSP1_SIZE	(SZ_1K * 2)
+#define OMAP_MCBSP1_START	0xfffb1000
+
+#define OMAP_MCBSP2_BASE	0xfffb1800
+
+#endif /*  __ASM_ARCH_OMAP730_H */
+
diff -Nru a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/param.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/arch-omap/param.h
+ *
+ *  Initially based on linux/include/asm-arm/arch-integrator/param.h
+ *  Copyright (C) 1999 ARM Limited
+ *
+ *  BRIEF MODULE DESCRIPTION
+ *   a place holder
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
diff -Nru a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/pm.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,150 @@
+/*
+ * FILE NAME include/asm/arch-omap/pm.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ * Author: MontaVista Software, Inc.
+ *	   support@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * List of global OMAP registers to preserve.  All registers are 16 bits
+ * and must be accessed with 16 read/writes.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+#ifndef __ASM_ARCH_OMAP1510_PM_H
+#define __ASM_ARCH_OMAP1510_PM_H
+
+#define ARM_REG_BASE		(0xfffece00)
+#define ARM_ASM_IDLECT1		(ARM_REG_BASE + 0x4)
+#define ARM_ASM_IDLECT2		(ARM_REG_BASE + 0x8)
+#define ARM_ASM_RSTCT1		(ARM_REG_BASE + 0x10)
+#define ARM_ASM_RSTCT2		(ARM_REG_BASE + 0x14)
+#define ARM_ASM_SYSST		(ARM_REG_BASE + 0x18)
+/*
+ * Traffic Controller Memory Interface Registers
+ */
+#define TCMIF_BASE		0xfffecc00
+#define EMIFS_ASM_CONFIG_REG	(TCMIF_BASE + 0x0c)
+#define EMIFF_ASM_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
+#define IRQ_MIR1	(volatile unsigned int *)(OMAP_IH1_BASE + IRQ_MIR)
+#define IRQ_MIR2	(volatile unsigned int *)(OMAP_IH2_BASE + IRQ_MIR)
+
+#define IDLE_WAIT_CYCLES		0x000000ff
+#define PERIPHERAL_ENABLE		0x2
+#define BIG_SLEEP_REQUEST		0x0cc5
+#define IDLE_LOOP_REQUEST		0x0c00
+#define SELF_REFRESH_MODE		0x0c000001
+#define IDLE_EMIFS_REQUEST		0xc
+#define IDLE_CLOCK_DOMAINS		0x2
+#define MODEM_32K_EN			0x1
+
+#ifndef __ASSEMBLER__
+extern void omap1510_pm_idle(void);
+extern void omap_pm_suspend(void);
+extern int omap1510_cpu_suspend(void);
+extern int omap1510_idle_loop_suspend(void);
+extern struct async_struct *omap_pm_sercons;
+extern unsigned int serial_in(struct async_struct *, int);
+extern unsigned int serial_out(struct async_struct *, int, int);
+
+#define OMAP1510_SRAM_IDLE_SUSPEND	0xd002F000
+#define OMAP1510_SRAM_API_SUSPEND	0xd002F200
+#define CPU_SUSPEND_SIZE	200
+#define ARM_REG_BASE		(0xfffece00)
+#define ARM_ASM_IDLECT1		(ARM_REG_BASE + 0x4)
+#define ARM_ASM_IDLECT2		(ARM_REG_BASE + 0x8)
+#define ARM_ASM_RSTCT1		(ARM_REG_BASE + 0x10)
+#define ARM_ASM_RSTCT2		(ARM_REG_BASE + 0x14)
+#define ARM_ASM_SYSST		(ARM_REG_BASE + 0x18)
+
+#define TCMIF_BASE		0xfffecc00
+#define PM_EMIFS_CONFIG_REG	   (volatile unsigned int *)(TCMIF_BASE + 0x0c)
+#define PM_EMIFF_SDRAM_CONFIG	   (volatile unsigned int *)(TCMIF_BASE + 0x20)
+
+#define ULPD_LOW_POWER_REQ		0x3
+
+#define DSP_IDLE_DELAY			10
+#define DSP_IDLE			0x0040
+#define DSP_ENABLE			0x0002
+#define SUFFICIENT_DSP_RESET_TIME	1000
+#define DEFAULT_MPUI_CONFIG		0x05cf
+#define ENABLE_XORCLK			0x2
+#define DSP_RESET			0x2000
+#define TC_IDLE_REQUEST			(0x0000000c)
+#define EMIFF_CONFIG_REG		EMIFF_SDRAM_CONFIG
+
+
+#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = (unsigned short)*x
+#define ARM_RESTORE(x) *x = (unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x]
+#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
+
+#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = (unsigned short)*x
+#define ULPD_RESTORE(x) *x = (unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+
+#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = (unsigned int)*x
+#define MPUI_RESTORE(x) *x = (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
+#define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
+
+enum arm_save_state {
+	ARM_SLEEP_SAVE_START = 0,
+	/*
+	 * 9 MPU control registers, all 16 bits
+	 */
+	ARM_SLEEP_SAVE_ARM_CKCTL, ARM_SLEEP_SAVE_ARM_IDLECT1,
+	ARM_SLEEP_SAVE_ARM_IDLECT2, ARM_SLEEP_SAVE_ARM_EWUPCT,
+	ARM_SLEEP_SAVE_ARM_RSTCT1, ARM_SLEEP_SAVE_ARM_RSTCT2,
+	ARM_SLEEP_SAVE_ARM_SYSST,
+
+	ARM_SLEEP_SAVE_SIZE
+};
+
+enum ulpd_save_state {
+	ULDP_SLEEP_SAVE_START = 0,
+	ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG,
+	ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG,
+	ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG,
+	ULPD_SLEEP_SAVE_SIZE
+};
+
+enum mpui_save_state {
+	/*
+	 * MPUI registers 32 bits
+	 */
+	MPUI_SLEEP_SAVE_MPUI_CTRL_REG, MPUI_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+	MPUI_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+	MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG,
+	MPUI_SLEEP_SAVE_PM_EMIFF_SDRAM_CONFIG,
+	MPUI_SLEEP_SAVE_PM_EMIFS_CONFIG_REG,
+	MPUI_SLEEP_SAVE_IRQ_MIR1, MPUI_SLEEP_SAVE_IRQ_MIR2,
+
+	MPUI_SLEEP_SAVE_SIZE
+};
+
+
+#endif	/* ASSEMBLER */
+#endif
diff -Nru a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/serial.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,167 @@
+/*
+ * linux/include/asm-arm/arch-omap/serial.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ * serial definitions
+ *
+ */
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+
+#define OMAP1510_UART1_BASE	(unsigned char *)0xfffb0000
+#define OMAP1510_UART2_BASE	(unsigned char *)0xfffb0800
+#define OMAP1510_UART3_BASE	(unsigned char *)0xfffb9800
+
+#define OMAP730_UART1_BASE	(unsigned char *)0xfffb0000
+#define OMAP730_UART2_BASE	(unsigned char *)0xfffb0800
+
+#if defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP1610)
+#define OMAP_SERIAL_REG_SHIFT 2
+#else
+#define OMAP_SERIAL_REG_SHIFT 0
+#endif
+
+
+#ifndef __ASSEMBLY__
+
+#include <asm/arch/hardware.h>
+#include <asm/irq.h>
+
+
+/* UART3 Registers Maping through MPU bus */
+#define OMAP_MPU_UART3_BASE	0xFFFB9800	/* UART3 through MPU bus */
+#define UART3_RHR		(OMAP_MPU_UART3_BASE + 0)
+#define UART3_THR		(OMAP_MPU_UART3_BASE + 0)
+#define UART3_DLL		(OMAP_MPU_UART3_BASE + 0)
+#define UART3_IER		(OMAP_MPU_UART3_BASE + 4)
+#define UART3_DLH		(OMAP_MPU_UART3_BASE + 4)
+#define UART3_IIR		(OMAP_MPU_UART3_BASE + 8)
+#define UART3_FCR		(OMAP_MPU_UART3_BASE + 8)
+#define UART3_EFR		(OMAP_MPU_UART3_BASE + 8)
+#define UART3_LCR		(OMAP_MPU_UART3_BASE + 0x0C)
+#define UART3_MCR		(OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1	(OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2	(OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_LSR		(OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_TCR		(OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_MSR		(OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF1		(OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF2		(OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_SPR		(OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_TLR		(OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_MDR1		(OMAP_MPU_UART3_BASE + 0x20)
+#define UART3_MDR2		(OMAP_MPU_UART3_BASE + 0x24)
+#define UART3_SFLSR		(OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_TXFLL		(OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_RESUME		(OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_TXFLH		(OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_SFREGL		(OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_RXFLL		(OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_SFREGH		(OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_RXFLH		(OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_BLR		(OMAP_MPU_UART3_BASE + 0x38)
+#define UART3_ACREG		(OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_DIV16		(OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_SCR		(OMAP_MPU_UART3_BASE + 0x40)
+#define UART3_SSR		(OMAP_MPU_UART3_BASE + 0x44)
+#define UART3_EBLR		(OMAP_MPU_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL	(OMAP_MPU_UART3_BASE + 0x4C)
+#define UART3_MVR		(OMAP_MPU_UART3_BASE + 0x50)
+
+#ifdef CONFIG_ARCH_OMAP1510
+#define BASE_BAUD (12000000/16)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1610
+#define BASE_BAUD (48000000/16)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP730
+#define BASE_BAUD (48000000/16)
+
+#define RS_TABLE_SIZE		2
+
+#define STD_COM_FLAGS	(ASYNC_SKIP_TEST)
+
+#define STD_SERIAL_PORT_DEFNS	\
+	{	\
+		.uart =			PORT_OMAP,		\
+		.baud_base =		BASE_BAUD,		\
+		.iomem_base =		OMAP730_UART1_BASE,	\
+		.iomem_reg_shift =	0,			\
+		.io_type =		SERIAL_IO_MEM,		\
+		.irq =			INT_UART1,		\
+		.flags =			STD_COM_FLAGS,		\
+	}, {	\
+		.uart =			PORT_OMAP,		\
+		.baud_base =		BASE_BAUD,		\
+		.iomem_base =		OMAP730_UART2_BASE,	\
+		.iomem_reg_shift =	0,			\
+		.io_type =		SERIAL_IO_MEM,		\
+		.irq =			INT_UART2,		\
+		.flags =			STD_COM_FLAGS,		\
+	}
+
+#else
+
+#define RS_TABLE_SIZE	3
+
+#define STD_COM_FLAGS	(ASYNC_SKIP_TEST)
+
+#define STD_SERIAL_PORT_DEFNS	\
+	{	\
+		.uart =			PORT_OMAP,		\
+		.baud_base =		BASE_BAUD,		\
+		.iomem_base =		OMAP1510_UART1_BASE,	\
+		.iomem_reg_shift =	2,			\
+		.io_type =		SERIAL_IO_MEM,		\
+		.irq =			INT_UART1,		\
+		.flags =		STD_COM_FLAGS,		\
+	}, {	\
+		.uart =			PORT_OMAP,		\
+		.baud_base =		BASE_BAUD,		\
+		.iomem_base =		OMAP1510_UART2_BASE,	\
+		.iomem_reg_shift =	2,			\
+		.io_type =		SERIAL_IO_MEM,		\
+		.irq =			INT_UART2,		\
+		.flags =		STD_COM_FLAGS,		\
+	}, {	\
+		.uart =			PORT_OMAP,		\
+		.baud_base =		BASE_BAUD,		\
+		.iomem_base =		OMAP1510_UART3_BASE,	\
+		.iomem_reg_shift =	2,			\
+		.io_type =		SERIAL_IO_MEM,		\
+		.irq =			INT_UART3,		\
+		.flags =		STD_COM_FLAGS,		\
+	}
+#endif				/* CONFIG_ARCH_OMAP730 */
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+/* OMAP FCR trigger  redefinitions */
+#define UART_FCR_R_TRIGGER_8	0x00	/* Mask for receive trigger set at 8 */
+#define UART_FCR_R_TRIGGER_16	0x40	/* Mask for receive trigger set at 16 */
+#define UART_FCR_R_TRIGGER_56	0x80	/* Mask for receive trigger set at 56 */
+#define UART_FCR_R_TRIGGER_60	0xC0	/* Mask for receive trigger set at 60 */
+
+/* There is an error in the description of the transmit trigger levels of
+   OMAP5910 TRM from January 2003. The transmit trigger level 56 is not
+   56 but 32, the transmit trigger level 60 is not 60 but 56!
+   Additionally, the descritption of these trigger levels is
+   a little bit unclear. The trigger level define the number of EMPTY
+   entries in the FIFO. Thus, if TRIGGER_8 is used, an interrupt is requested
+   if 8 FIFO entries are empty (and 56 entries are still filled [the FIFO
+   size is 64]). Or: If TRIGGER_56 is selected, everytime there are less than
+   8 characters in the FIFO, an interrrupt is spawned. In other words: The
+   trigger number is equal the number of characters which can be
+   written without FIFO overrun */
+
+#define UART_FCR_T_TRIGGER_8	0x00	/* Mask for transmit trigger set at 8 */
+#define UART_FCR_T_TRIGGER_16	0x10	/* Mask for transmit trigger set at 16 */
+#define UART_FCR_T_TRIGGER_32	0x20	/* Mask for transmit trigger set at 32 */
+#define UART_FCR_T_TRIGGER_56	0x30	/* Mask for transmit trigger set at 56 */
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __ASM_ARCH_SERIAL_H */
diff -Nru a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/system.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,20 @@
+/*
+ * Copied from linux/include/asm-arm/arch-sa1100/system.h
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/config.h>
+#include <asm/arch/hardware.h>
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+	*(volatile u16 *)(ARM_RSTCT1) = 1;
+}
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/time.h b/include/asm-arm/arch-omap/time.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/time.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,212 @@
+/*
+ * linux/include/asm-arm/arch-omap/time.h
+ *
+ * 32kHz timer definition
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#if !defined(__ASM_ARCH_OMAP_TIME_H)
+#define __ASM_ARCH_OMAP_TIME_H
+
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/system.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/leds.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/clocks.h>
+
+#ifndef __instrument
+#define __instrument
+#define __noinstrument __attribute__ ((no_instrument_function))
+#endif
+
+typedef struct {
+	u32 cntl;     /* CNTL_TIMER, R/W */
+	u32 load_tim; /* LOAD_TIM,   W */
+	u32 read_tim; /* READ_TIM,   R */
+} mputimer_regs_t;
+
+#define mputimer_base(n) \
+    ((volatile mputimer_regs_t*)(OMAP_MPUTIMER_BASE + \
+				 (n)*OMAP_MPUTIMER_OFF))
+
+static inline unsigned long timer32k_read(int reg) {
+	unsigned long val;
+	val = (inw(IO_ADDRESS((reg) + OMAP_32kHz_TIMER_BASE)));
+	return val;
+}
+static inline void timer32k_write(int reg,int val) {
+	outw( (val), (IO_ADDRESS( (reg) + OMAP_32kHz_TIMER_BASE)));
+}
+
+/*
+ * How long is the timer interval? 100 HZ, right...
+ * IRQ rate = (TVR + 1) / 32768 seconds
+ * TVR = 32768 * IRQ_RATE -1
+ * IRQ_RATE =  1/100
+ * TVR = 326
+ */
+#define TIMER32k_PERIOD 326
+//#define TIMER32k_PERIOD 0x7ff
+
+static inline void start_timer32k(void) {
+	timer32k_write(TIMER32k_CR,
+		       TIMER32k_TSS | TIMER32k_TRB |
+		       TIMER32k_INT | TIMER32k_ARL);
+}
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+/*
+ * After programming PTV with 0 and setting the MPUTIM_CLOCK_ENABLE
+ * (external clock enable)  bit, the timer count rate is 6.5 MHz (13
+ * MHZ input/2). !! The divider by 2 is undocumented !!
+ */
+#define MPUTICKS_PER_SEC (13000000/2)
+#else
+/*
+ * After programming PTV with 0, the timer count rate is 6 MHz.
+ * WARNING! this must be an even number, or machinecycles_to_usecs
+ * below will break.
+ */
+#define MPUTICKS_PER_SEC  (12000000/2)
+#endif
+
+static int mputimer_started[3] = {0,0,0};
+
+static inline void __noinstrument start_mputimer(int n,
+						 unsigned long load_val)
+{
+	volatile mputimer_regs_t* timer = mputimer_base(n);
+
+	mputimer_started[n] = 0;
+	timer->cntl = MPUTIM_CLOCK_ENABLE;
+	udelay(1);
+
+	timer->load_tim = load_val;
+        udelay(1);
+	timer->cntl = (MPUTIM_CLOCK_ENABLE | MPUTIM_AR | MPUTIM_ST);
+	mputimer_started[n] = 1;
+}
+
+static inline unsigned long __noinstrument
+read_mputimer(int n)
+{
+	volatile mputimer_regs_t* timer = mputimer_base(n);
+	return (mputimer_started[n] ? timer->read_tim : 0);
+}
+
+void __noinstrument start_mputimer1(unsigned long load_val)
+{
+	start_mputimer(0, load_val);
+}
+void __noinstrument start_mputimer2(unsigned long load_val)
+{
+	start_mputimer(1, load_val);
+}
+void __noinstrument start_mputimer3(unsigned long load_val)
+{
+	start_mputimer(2, load_val);
+}
+
+unsigned long __noinstrument read_mputimer1(void)
+{
+	return read_mputimer(0);
+}
+unsigned long __noinstrument read_mputimer2(void)
+{
+	return read_mputimer(1);
+}
+unsigned long __noinstrument read_mputimer3(void)
+{
+	return read_mputimer(2);
+}
+
+unsigned long __noinstrument do_getmachinecycles(void)
+{
+	return 0 - read_mputimer(0);
+}
+
+unsigned long __noinstrument machinecycles_to_usecs(unsigned long mputicks)
+{
+	/* Round up to nearest usec */
+	return ((mputicks * 1000) / (MPUTICKS_PER_SEC / 2 / 1000) + 1) >> 1;
+}
+
+/*
+ * This marks the time of the last system timer interrupt
+ * that was *processed by the ISR* (timer 2).
+ */
+static unsigned long systimer_mark;
+
+static unsigned long omap1510_gettimeoffset(void)
+{
+	/* Return elapsed usecs since last system timer ISR */
+	return machinecycles_to_usecs(do_getmachinecycles() - systimer_mark);
+}
+
+static irqreturn_t
+omap1510_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	unsigned long now, ilatency;
+
+	/*
+	 * Mark the time at which the timer interrupt ocurred using
+	 * timer1. We need to remove interrupt latency, which we can
+	 * retrieve from the current system timer2 counter. Both the
+	 * offset timer1 and the system timer2 are counting at 6MHz,
+	 * so we're ok.
+	 */
+	now = 0 - read_mputimer1();
+	ilatency = MPUTICKS_PER_SEC / 100 - read_mputimer2();
+	systimer_mark = now - ilatency;
+
+	do_leds();
+	do_timer(regs);
+	do_profile(regs);
+
+	return IRQ_HANDLED;
+}
+
+void __init time_init(void)
+{
+	/* Since we don't call request_irq, we must init the structure */
+	gettimeoffset = omap1510_gettimeoffset;
+
+	timer_irq.handler = omap1510_timer_interrupt;
+	timer_irq.flags = SA_INTERRUPT;
+#ifdef OMAP1510_USE_32KHZ_TIMER
+	timer32k_write(TIMER32k_CR, 0x0);
+	timer32k_write(TIMER32k_TVR,TIMER32k_PERIOD);
+	setup_irq(INT_OS_32kHz_TIMER, &timer_irq);
+	start_timer32k();
+#else
+	setup_irq(INT_TIMER2, &timer_irq);
+	start_mputimer2(MPUTICKS_PER_SEC / 100 - 1);
+#endif
+}
+
+#endif
diff -Nru a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/timex.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-arm/arch-omap/timex.h
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author:  Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
+#define __ASM_ARCH_OMAP_TIMEX_H
+
+#include <asm/arch/clocks.h>
+/* TC clock */
+#define CLOCK_TICK_RATE		((OMAP_CK_MAX_RATE*1000000)/2)
+
+#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff -Nru a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/uncompress.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,76 @@
+/*
+ * linux/include/asm-arm/arch-omap/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/arch/serial.h>
+
+
+#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
+
+static void
+puts(const char *s)
+{
+	volatile u8 * uart = 0;
+	int shift = 0;
+
+	/* Determine which serial port to use */
+	do {
+		if (machine_is_innovator()) {
+			shift = 2;
+			uart = (volatile u8 *)(OMAP1510_UART1_BASE);
+		} else {
+			/* Assume nothing for unknown machines.
+			 * Add an entry for your machine to select
+			 * the default serial console here. If the
+			 * serial port is enabled, we'll use it to
+			 * display status messages. Else we'll be
+			 * quiet.
+			 */
+			return;
+		}
+		if (check_port(uart, shift))
+			break;
+		/* Silent boot if no serial ports are enabled. */
+		return;
+	} while (0);
+
+	/*
+	 * Now, xmit each character
+	 */
+	while (*s) {
+		while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+			barrier();
+		uart[UART_TX << shift] = *s;
+		if (*s++ == '\n') {
+			while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+				barrier();
+			uart[UART_TX << shift] = '\r';
+		}
+	}
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff -Nru a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-omap/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/arch-omap/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END	  (PAGE_OFFSET + 0x10000000)
diff -Nru a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
--- a/include/asm-arm/arch-pxa/memory.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-pxa/memory.h	Thu Apr  8 14:54:32 2004
@@ -55,4 +55,52 @@
 #define __virt_to_bus(x)	 __virt_to_phys(x)
 #define __bus_to_virt(x)	 __phys_to_virt(x)
 
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * The nodes are matched with the physical SDRAM banks as follows:
+ *
+ * 	node 0:  0xa0000000-0xa3ffffff	-->  0xc0000000-0xc3ffffff
+ * 	node 1:  0xa4000000-0xa7ffffff	-->  0xc4000000-0xc7ffffff
+ * 	node 2:  0xa8000000-0xabffffff	-->  0xc8000000-0xcbffffff
+ * 	node 3:  0xac000000-0xafffffff	-->  0xcc000000-0xcfffffff
+ */
+
+#define NR_NODES	4
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn)		(((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)	NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)	NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+	(((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
+
+#else
+
+#define PFN_TO_NID(addr)	(0)
+
+#endif
+
 #endif
diff -Nru a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
--- a/include/asm-arm/arch-pxa/pxa-regs.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-pxa/pxa-regs.h	Thu Apr  8 14:54:32 2004
@@ -1076,6 +1076,35 @@
 #define SSITR		__REG(0x4100000C)  /* SSP Interrupt Test Register */
 #define SSDR		__REG(0x41000010)  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
 
+#define SSCR0_DSS	(0x0000000f)	/* Data Size Select (mask) */
+#define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */
+#define SSCR0_FRF	(0x00000030)	/* FRame Format (mask) */
+#define SSCR0_Motorola	(0x0 << 4)	/* Motorola's Serial Peripheral Interface (SPI) */
+#define SSCR0_TI	(0x1 << 4)	/* Texas Instruments' Synchronous Serial Protocol (SSP) */
+#define SSCR0_National	(0x2 << 4)	/* National Microwire */
+#define SSCR0_ECS	(1 << 6)	/* External clock select */
+#define SSCR0_SSE	(1 << 7)	/* Synchronous Serial Port Enable */
+#define SSCR0_SCR	(0x0000ff00)	/* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+
+#define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE	(1 << 1)	/* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM	(1 << 2)	/* Loop-Back Mode */
+#define SSCR1_SPO	(1 << 3)	/* Motorola SPI SSPSCLK polarity setting */
+#define SSCR1_SPH	(1 << 4)	/* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS	(1 << 5)	/* Microwire Transmit Data Size */
+#define SSCR1_TFT	(0x000003c0)	/* Transmit FIFO Threshold (mask) */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_RFT	(0x00003c00)	/* Receive FIFO Threshold (mask) */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+
+#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
+#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
+#define SSSR_BSY	(1 << 4)	/* SSP Busy */
+#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
+#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
+#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
+
 
 /*
  * MultiMediaCard (MMC) controller
diff -Nru a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h
--- a/include/asm-arm/arch-pxa/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-pxa/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -20,6 +20,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (0xe8000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-rpc/vmalloc.h b/include/asm-arm/arch-rpc/vmalloc.h
--- a/include/asm-arm/arch-rpc/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-rpc/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -19,6 +19,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-s3c2410/bast-cpld.h b/include/asm-arm/arch-s3c2410/bast-cpld.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/bast-cpld.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,25 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * BAST - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  25-May-2003 BJD  Created file, added CTRL1 registers
+*/
+
+#ifndef __ASM_ARCH_BASTCPLD_H
+#define __ASM_ARCH_BASTCPLD_H
+
+#define BAST_CPLD_CTRL1_LRCOFF	    (0x00)
+#define BAST_CPLD_CTRL1_LRCADC	    (0x01)
+#define BAST_CPLD_CTRL1_LRCDAC	    (0x02)
+#define BAST_CPLD_CTRL1_LRCARM	    (0x03)
+#define BAST_CPLD_CTRL1_LRMASK	    (0x03)
+
+#endif /* __ASM_ARCH_BASTCPLD_H */
diff -Nru a/include/asm-arm/arch-s3c2410/bast-irq.h b/include/asm-arm/arch-s3c2410/bast-irq.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/bast-irq.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-irq.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine BAST - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version
+ */
+
+#ifndef __ASM_ARCH_BASTIRQ_H
+#define __ASM_ARCH_BASTIRQ_H
+
+/* irq numbers to onboard peripherals */
+
+#define IRQ_USBOC      IRQ_EINT19
+#define IRQ_IDE0       IRQ_EINT16
+#define IRQ_IDE1       IRQ_EINT17
+#define IRQ_PCSERIAL1  IRQ_EINT15
+#define IRQ_PCSERIAL2  IRQ_EINT14
+#define IRQ_PCPARALLEL IRQ_EINT13
+#define IRQ_ASIX       IRQ_EINT11
+#define IRQ_DM9000     IRQ_EINT10
+#define IRQ_ISA	       IRQ_EINT9
+#define IRQ_SMALERT    IRQ_EINT8
+
+#endif /* __ASM_ARCH_BASTIRQ_H */
diff -Nru a/include/asm-arm/arch-s3c2410/bast-map.h b/include/asm-arm/arch-s3c2410/bast-map.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/bast-map.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,150 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-map.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine BAST - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version, moved bast specifics from arch/map.h
+ *  12-Mar-2004 BJD  Fixed header include protection
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#ifndef __ASM_ARCH_BASTMAP_H
+#define __ASM_ARCH_BASTMAP_H
+
+#define BAST_IOADDR(x)	   (S3C2410_ADDR((x) + 0x01300000))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define BAST_VA_CTRL1	    BAST_IOADDR(0x00000000)	 /* 0x01300000 */
+#define BAST_PA_CTRL1	    (S3C2410_CS5 | 0x7800000)
+
+#define BAST_VA_CTRL2	    BAST_IOADDR(0x00100000)	 /* 0x01400000 */
+#define BAST_PA_CTRL2	    (S3C2410_CS1 | 0x6000000)
+
+#define BAST_VA_CTRL3	    BAST_IOADDR(0x00200000)	 /* 0x01500000 */
+#define BAST_PA_CTRL3	    (S3C2410_CS1 | 0x6800000)
+
+#define BAST_VA_CTRL4	    BAST_IOADDR(0x00300000)	 /* 0x01600000 */
+#define BAST_PA_CTRL4	    (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
+
+#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
+
+#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
+
+#define BAST_PA_LCD_RCMD1     (0x8800000)
+#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
+
+#define BAST_PA_LCD_WCMD1     (0x8000000)
+#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
+
+#define BAST_PA_LCD_RDATA1    (0x9800000)
+#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
+
+#define BAST_PA_LCD_WDATA1    (0x9000000)
+#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
+
+#define BAST_PA_LCD_RCMD2     (0xA800000)
+#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
+
+#define BAST_PA_LCD_WCMD2     (0xA000000)
+#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
+
+#define BAST_PA_LCD_RDATA2    (0xB800000)
+#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
+
+#define BAST_PA_LCD_WDATA2    (0xB000000)
+#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
+
+
+/* 0xE0000000 contains the IO space that is split by speed and
+ * wether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x00000000 to 0x01000000 16MB ISA IO space
+ * 0x01000000 to 0x02000000 16MB ISA memory space
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
+ * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define BAST_VA_MULTISPACE (0xE0000000)
+
+#define BAST_VA_ISAIO	   (BAST_VA_MULTISPACE + 0x00000000)
+#define BAST_VA_ISAMEM	   (BAST_VA_MULTISPACE + 0x01000000)
+#define BAST_VA_IDEPRI	   (BAST_VA_MULTISPACE + 0x02000000)
+#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
+#define BAST_VA_IDESEC	   (BAST_VA_MULTISPACE + 0x02200000)
+#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
+#define BAST_VA_ASIXNET	   (BAST_VA_MULTISPACE + 0x02400000)
+#define BAST_VA_DM9000	   (BAST_VA_MULTISPACE + 0x02500000)
+#define BAST_VA_SUPERIO	   (BAST_VA_MULTISPACE + 0x02600000)
+
+#define BAST_VA_MULTISPACE (0xE0000000)
+
+#define BAST_VAM_CS2 (0x00000000)
+#define BAST_VAM_CS3 (0x04000000)
+#define BAST_VAM_CS4 (0x08000000)
+#define BAST_VAM_CS5 (0x0C000000)
+
+/* physical offset addresses for the peripherals */
+
+#define BAST_PA_ISAIO	  (0x00000000)
+#define BAST_PA_ASIXNET	  (0x01000000)
+#define BAST_PA_SUPERIO	  (0x01800000)
+#define BAST_PA_IDEPRI	  (0x02000000)
+#define BAST_PA_IDEPRIAUX (0x02800000)
+#define BAST_PA_IDESEC	  (0x03000000)
+#define BAST_PA_IDESECAUX (0x03800000)
+#define BAST_PA_ISAMEM	  (0x04000000)
+#define BAST_PA_DM9000	  (0x05000000)
+
+/* some configurations for the peripherals */
+
+#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
+/*  */
+
+#define BAST_ASIXNET_CS  BAST_VAM_CS5
+#define BAST_IDE_CS	 BAST_VAM_CS5
+#define BAST_DM9000_CS	 BAST_VAM_CS4
+
+#endif /* __ASM_ARCH_BASTMAP_H */
diff -Nru a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/dma.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,169 @@
+/* linux/include/asm-arm/arch-bast/dma.h
+ *
+ * Copyright (C) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C2410X DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  ??-May-2003 BJD   Created file
+ *  ??-Jun-2003 BJD   Added more dma functionality to go with arch
+*/
+
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include <linux/config.h>
+#include "hardware.h"
+
+
+/*
+ * This is the maximum DMA address(physical address) that can be DMAd to.
+ *
+ */
+#define MAX_DMA_ADDRESS		0x20000000
+#define MAX_DMA_TRANSFER_SIZE	0x100000 /* Data Unit is half word  */
+
+
+/* according to the samsung port, we cannot use the regular
+ * dma channels... we must therefore provide our own interface
+ * for DMA, and allow our drivers to use that.
+ */
+
+#define MAX_DMA_CHANNELS	0
+
+
+/* we have 4 dma channels */
+#define S3C2410_DMA_CHANNELS	    (4)
+
+
+/* dma buffer */
+
+typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
+
+struct s3c2410_dma_buf_s {
+	s3c2410_dma_buf_t   *next;
+	int		     magic;	   /* magic */
+	int		     size;	   /* buffer size in bytes */
+	dma_addr_t	     data;	   /* start of DMA data */
+	dma_addr_t	     ptr;	   /* where the DMA got to [1] */
+	int		     ref;
+	void		     *id;	   /* client's id */
+	unsigned char	     no_callback;  /* disable callback for buffer */
+};
+
+/* [1] is this updated for both recv/send modes? */
+
+typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
+
+typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size);
+typedef void (*s3c2410_dma_enfn_t)(s3c2410_dma_chan_t *, int on);
+typedef void (*s3c2410_dma_pausefn_t)(s3c2410_dma_chan_t *, int on);
+
+struct s3c2410_dma_chan_s {
+	/* channel state flags */
+	unsigned char	       number;	      /* number of this dma channel */
+	unsigned char	       in_use;	      /* channel allocated */
+	unsigned char	       started;	      /* channel has been started */
+	unsigned char	       stopped;	      /* channel stopped */
+	unsigned char	       sleeping;
+	unsigned char	       xfer_unit;     /* size of an transfer */
+	unsigned char	       irq_claimed;
+
+	/* channel's hardware position and configuration */
+	unsigned long	       regs;	      /* channels registers */
+	unsigned int	       irq;	      /* channel irq */
+	unsigned long	       addr_reg;      /* data address register for buffs */
+	unsigned long	       dcon;	      /* default value of DCON */
+
+	/* driver handlers for channel */
+	s3c2410_dma_cbfn_t     callback_fn;   /* callback function for buf-done */
+	s3c2410_dma_enfn_t     enable_fn;     /* channel enable function */
+	s3c2410_dma_pausefn_t  pause_fn;      /* channel pause function */
+
+	/* buffer list and information */
+	s3c2410_dma_buf_t      *curr;	      /* current dma buffer */
+	s3c2410_dma_buf_t      *next;	      /* next buffer to load */
+	s3c2410_dma_buf_t      *end;	      /* end of queue */
+
+	int		       queue_count;   /* number of items in queue */
+	int		       loaded_count;  /* number of loaded buffers */
+};
+
+/* note, we don't really use dma_deivce_t at the moment */
+typedef unsigned long dma_device_t;
+
+typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
+
+/* these two defines control the source for the dma channel,
+ * wether it is from memory or an device
+*/
+
+enum s3c2410_dmasrc_e {
+  S3C2410_DMASRC_HW,	  /* source is memory */
+  S3C2410_DMASRC_MEM	  /* source is hardware */
+};
+
+/* dma control routines */
+
+extern int s3c2410_request_dma(dmach_t channel, const char *devid, void *dev);
+extern int s3c2410_free_dma(dmach_t channel);
+extern int s3c2410_dma_flush_all(dmach_t channel);
+
+extern int s3c2410_dma_stop(dmach_t channel);
+extern int s3c2410_dma_resume(dmach_t channel);
+
+extern int s3c2410_dma_queue(dmach_t channel, void *id,
+			     dma_addr_t data, int size);
+
+#define s3c2410_dma_queue_buffer s3c2410_dma_queue
+
+/* channel configuration */
+
+extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
+
+extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
+				 int hwcfg, unsigned long devaddr);
+
+extern int s3c2410_dma_set_enablefn(dmach_t, s3c2410_dma_enfn_t rtn);
+extern int s3c2410_dma_set_pausefn(dmach_t, s3c2410_dma_pausefn_t rtn);
+extern int s3c2410_dma_set_callbackfn(dmach_t, s3c2410_dma_cbfn_t rtn);
+
+#define s3c2410_dma_set_callback s3c2410_dma_set_callbackfn
+
+#define S3C2410_DMA_DISRC	(0x00)
+#define S3C2410_DMA_DISRCC	(0x04)
+#define S3C2410_DMA_DIDST	(0x08)
+#define S3C2410_DMA_DIDSTC	(0x0C)
+#define S3C2410_DMA_DCON	(0x10)
+#define S3C2410_DMA_DSTAT	(0x14)
+#define S3C2410_DMA_DCSRC	(0x18)
+#define S3C2410_DMA_DCDST	(0x1C)
+#define S3C2410_DMA_DMASKTRIG	(0x20)
+
+#define S3C2410_DMASKTRIG_STOP	 (1<<2)
+#define S3C2410_DMASKTRIG_ON	 (1<<1)
+#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
+
+#define S3C2410_DCOM_DEMAND	(0<<31)
+#define S3C2410_DCON_HANDSHAKE  (1<<31)
+#define S3C2410_DCON_SYNC_PCLK  (0<<30)
+#define S3C2410_DCON_SYNC_HCLK  (1<<30)
+
+#define S3C2410_DCON_INTREQ	(1<<29)
+
+#define S3C2410_DCON_SRCSHIFT	(24)
+
+#define S3C2410_DCON_BYTE	(0<<20)
+#define S3C2410_DCON_HALFWORD	(1<<20)
+#define S3C2410_DCON_WORD	(2<<20)
+
+#define S3C2410_DCON_AUTORELOAD (0<<22)
+#define S3C2410_DCON_HWTRIG	(1<<23)
+
+#endif /* __ASM_ARCH_DMA_H */
diff -Nru a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/hardware.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,43 @@
+/* linux/include/asm-arm/arch-s3c2410/hardware.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  21-May-2003 BJD  Created file
+ *  06-Jun-2003 BJD  Added CPU frequency settings
+ *  03-Sep-2003 BJD  Linux v2.6 support
+ *  12-Mar-2004 BJD  Fixed include protection, fixed type of clock vars
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+/* processor clock settings, in Hz */
+extern unsigned long s3c2410_pclk;
+extern unsigned long s3c2410_hclk;
+extern unsigned long s3c2410_fclk;
+
+#endif /* __ASSEMBLY__ */
+
+#include <asm/sizes.h>
+#include <asm/arch/map.h>
+
+/* machine specific includes, such as the BAST */
+
+#if defined(CONFIG_ARCH_BAST)
+#include <asm/arch/bast-cpld.h>
+#endif
+
+/* currently here until moved into config (todo) */
+#define CONFIG_NO_MULTIWORD_IO
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff -Nru a/include/asm-arm/arch-s3c2410/ide.h b/include/asm-arm/arch-s3c2410/ide.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/ide.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,49 @@
+/* linux/include/asm-arm/arch-s3c2410/ide.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *  Copyright (C) 2003 Simtec Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Modifications:
+ *   29-07-1998	RMK	Major re-work of IDE architecture specific code
+ *   16-05-2003 BJD	Changed to work with BAST IDE ports
+ *   04-09-2003 BJD	Modifications for V2.6
+ */
+
+#ifndef __ASM_ARCH_IDE_H
+#define __ASM_ARCH_IDE_H
+
+#include <asm/irq.h>
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+
+static __inline__ void
+ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
+{
+	ide_ioreg_t reg = (ide_ioreg_t) data_port;
+	int i;
+
+	memset(hw, 0, sizeof(*hw));
+
+	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+		hw->io_ports[i] = reg;
+		reg += 1;
+	}
+	hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
+	if (irq)
+		*irq = 0;
+}
+
+/* we initialise our ide devices from the main ide core, due to problems
+ * with doing it in this function
+*/
+
+#define ide_init_default_hwifs() do { } while(0)
+
+#endif /* __ASM_ARCH_IDE_H */
diff -Nru a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/io.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,198 @@
+/*
+ * linux/include/asm-arm/arch-s3c2410/io.h
+ *  from linux/include/asm-arm/arch-rpc/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *	     (C) 2003 Simtec Electronics
+ *
+ * Modifications:
+ *  06-Dec-1997	RMK	Created.
+ *  02-Sep-2003 BJD	Modified for S3C2410
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are above A28
+ * and are translated to the start of IO.  Note that all addresses are
+ * not shifted left!
+ */
+
+#define __PORT_PCIO(x)	((x) < (1<<28))
+
+#define PCIO_BASE	 (S3C2410_VA_ISA_WORD)
+#define PCIO_BASE_b	 (S3C2410_VA_ISA_BYTE)
+#define PCIO_BASE_w	 (S3C2410_VA_ISA_WORD)
+#define PCIO_BASE_l	 (S3C2410_VA_ISA_WORD)
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+
+#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
+static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
+{ \
+	unsigned long temp;				      \
+	__asm__ __volatile__(				      \
+	"cmp	%2, #(1<<28)\n\t"			      \
+	"mov	%0, %2\n\t"				      \
+	"addcc	%0, %0, %3\n\t"				      \
+	"str" instr " %1, [%0, #0 ]	@ out" #fnsuffix      \
+	: "=&r" (temp)					      \
+	: "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix)  \
+	: "cc");					      \
+}
+
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)				\
+static inline unsigned sz __in##fnsuffix (unsigned int port)		\
+{									\
+	unsigned long temp, value;					\
+	__asm__ __volatile__(						\
+	"cmp	%2, #(1<<28)\n\t"					\
+	"mov	%0, %2\n\t"						\
+	"addcc	%0, %0, %3\n\t"						\
+	"ldr" instr "	%1, [%0, #0 ]	@ in" #fnsuffix		\
+	: "=&r" (temp), "=r" (value)					\
+	: "r" (port), "Ir" (PCIO_BASE_##fnsuffix)	\
+	: "cc");							\
+	return (unsigned sz)value;					\
+}
+
+static inline unsigned int __ioaddr (unsigned int port)
+{
+	if (__PORT_PCIO(port))
+		return (unsigned int)(PCIO_BASE + (port));
+	else
+		return (unsigned int)(0 + (port));
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)	\
+	DECLARE_DYN_IN(sz,fnsuffix,instr) \
+	DECLARE_DYN_OUT(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"h")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)						\
+({									\
+	if (__PORT_PCIO((port)))					\
+		__asm__ __volatile__(					\
+		"strb	%0, [%1, %2]	@ outbc"			\
+		: : "r" (value), "r" (PCIO_BASE), "Jr" ((port)));	\
+	else								\
+		__asm__ __volatile__(					\
+		"strb	%0, [%1, #0]	@ outbc"			\
+		: : "r" (value), "r" ((port)));		\
+})
+
+#define __inbc(port)							\
+({									\
+	unsigned char result;						\
+	if (__PORT_PCIO((port)))					\
+		__asm__ __volatile__(					\
+		"ldrb	%0, [%1, %2]	@ inbc"				\
+		: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));	\
+	else								\
+		__asm__ __volatile__(					\
+		"ldrb	%0, [%1, #0]	@ inbc"				\
+		: "=r" (result) : "r" ((port)));	\
+	result;								\
+})
+
+#define __outwc(value,port)						\
+({									\
+	unsigned long v = value;					\
+	if (__PORT_PCIO((port)))					\
+		__asm__ __volatile__(					\
+		"strh	%0, [%1, %2]	@ outwc"			\
+		: : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));	\
+	else								\
+		__asm__ __volatile__(					\
+		"strh	%0, [%1, #0]	@ outwc"			\
+		: : "r" (v), "r" ((port)));	\
+})
+
+#define __inwc(port)							\
+({									\
+	unsigned short result;						\
+	if (__PORT_PCIO((port)))					\
+		__asm__ __volatile__(					\
+		"ldrh	%0, [%1, %2]	@ inwc"				\
+		: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));	\
+	else								\
+		__asm__ __volatile__(					\
+		"ldrh	%0, [%1, #0]	@ inwc"				\
+		: "=r" (result) : "r" ((port)));		\
+	result;						\
+})
+
+#define __outlc(value,port)						\
+({									\
+	unsigned long v = value;					\
+	if (__PORT_PCIO((port)))					\
+		__asm__ __volatile__(					\
+		"str	%0, [%1, %2]	@ outlc"			\
+		: : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));	\
+	else								\
+		__asm__ __volatile__(					\
+		"str	%0, [%1, #0]	@ outlc"			\
+		: : "r" (v), "r" ((port)));		\
+})
+
+#define __inlc(port)							\
+({									\
+	unsigned long result;						\
+	if (__PORT_PCIO((port)))					\
+		__asm__ __volatile__(					\
+		"ldr	%0, [%1, %2]	@ inlc"				\
+		: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));	\
+	else								\
+		__asm__ __volatile__(					\
+		"ldr	%0, [%1, #0]	@ inlc"				\
+		: "=r" (result) : "r" ((port)));		\
+	result;								\
+})
+
+#define __ioaddrc(port)	(__PORT_PCIO((port)) ? PCIO_BASE + ((port)) : ((port)))
+
+#define inb(p)		(__builtin_constant_p((p)) ? __inbc(p)	   : __inb(p))
+#define inw(p)		(__builtin_constant_p((p)) ? __inwc(p)	   : __inw(p))
+#define inl(p)		(__builtin_constant_p((p)) ? __inlc(p)	   : __inl(p))
+#define outb(v,p)	(__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)	(__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)	(__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)	(__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)			__ioaddr((port))
+
+#define insb(p,d,l)	__raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)	__raw_readsw(__ioaddr(p),d,l)
+#define insl(p,d,l)	__raw_readsl(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)	__raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)	__raw_writesw(__ioaddr(p),d,l)
+#define outsl(p,d,l)	__raw_writesl(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)	(x)
+
+#endif
diff -Nru a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/irqs.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,115 @@
+/* linux/include/asm-arm/arch-s3c2410/irqs.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  12-May-2003 BJD  Created file
+ *  08-Jan-2003 BJD  Linux 2.6.0 version, moved BAST bits out
+ *  12-Mar-2004 BJD  Fixed bug in header protection
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ */
+
+#define S3C2410_CPUIRQ_OFFSET	 (16)
+
+#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
+
+/* main cpu interrupts */
+#define IRQ_EINT0      S3C2410_IRQ(0)	    /* 16 */
+#define IRQ_EINT1      S3C2410_IRQ(1)
+#define IRQ_EINT2      S3C2410_IRQ(2)
+#define IRQ_EINT3      S3C2410_IRQ(3)
+#define IRQ_EINT4t7    S3C2410_IRQ(4)	    /* 20 */
+#define IRQ_EINT8t23   S3C2410_IRQ(5)
+#define IRQ_RESERVED6  S3C2410_IRQ(6)
+#define IRQ_BATT_FLT   S3C2410_IRQ(7)
+#define IRQ_TICK       S3C2410_IRQ(8)	    /* 24 */
+#define IRQ_WDT	       S3C2410_IRQ(9)
+#define IRQ_TIMER0     S3C2410_IRQ(10)
+#define IRQ_TIMER1     S3C2410_IRQ(11)
+#define IRQ_TIMER2     S3C2410_IRQ(12)
+#define IRQ_TIMER3     S3C2410_IRQ(13)
+#define IRQ_TIMER4     S3C2410_IRQ(14)
+#define IRQ_UART2      S3C2410_IRQ(15)
+#define IRQ_LCD	       S3C2410_IRQ(16)	    /* 32 */
+#define IRQ_DMA0       S3C2410_IRQ(17)
+#define IRQ_DMA1       S3C2410_IRQ(18)
+#define IRQ_DMA2       S3C2410_IRQ(19)
+#define IRQ_DMA3       S3C2410_IRQ(20)
+#define IRQ_SDI	       S3C2410_IRQ(21)
+#define IRQ_SPI0       S3C2410_IRQ(22)
+#define IRQ_UART1      S3C2410_IRQ(23)
+#define IRQ_RESERVED24 S3C2410_IRQ(24)	    /* 40 */
+#define IRQ_USBD       S3C2410_IRQ(25)
+#define IRQ_USBH       S3C2410_IRQ(26)
+#define IRQ_IIC	       S3C2410_IRQ(27)
+#define IRQ_UART0      S3C2410_IRQ(28)	    /* 44 */
+#define IRQ_SPI1       S3C2410_IRQ(29)
+#define IRQ_RTC	       S3C2410_IRQ(30)
+#define IRQ_ADCPARENT  S3C2410_IRQ(31)
+
+/* interrupts generated from the external interrupts sources */
+#define IRQ_EINT4      S3C2410_IRQ(32)	   /* 48 */
+#define IRQ_EINT5      S3C2410_IRQ(33)
+#define IRQ_EINT6      S3C2410_IRQ(34)
+#define IRQ_EINT7      S3C2410_IRQ(35)
+#define IRQ_EINT8      S3C2410_IRQ(36)
+#define IRQ_EINT9      S3C2410_IRQ(37)
+#define IRQ_EINT10     S3C2410_IRQ(38)
+#define IRQ_EINT11     S3C2410_IRQ(39)
+#define IRQ_EINT12     S3C2410_IRQ(40)
+#define IRQ_EINT13     S3C2410_IRQ(41)
+#define IRQ_EINT14     S3C2410_IRQ(42)
+#define IRQ_EINT15     S3C2410_IRQ(43)
+#define IRQ_EINT16     S3C2410_IRQ(44)
+#define IRQ_EINT17     S3C2410_IRQ(45)
+#define IRQ_EINT18     S3C2410_IRQ(46)
+#define IRQ_EINT19     S3C2410_IRQ(47)
+#define IRQ_EINT20     S3C2410_IRQ(48)	   /* 64 */
+#define IRQ_EINT21     S3C2410_IRQ(49)
+#define IRQ_EINT22     S3C2410_IRQ(50)
+#define IRQ_EINT23     S3C2410_IRQ(51)
+
+
+#define IRQ_EINT(x)    S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
+
+#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+
+/* IRQs for the interal UARTs, and ADC
+ * these need to be ordered in number of appearance in the
+ * SUBSRC mask register
+*/
+#define IRQ_S3CUART_RX0  S3C2410_IRQ(54)   /* 70 */
+#define IRQ_S3CUART_TX0  S3C2410_IRQ(55)   /* 71 */
+#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
+
+#define IRQ_S3CUART_RX1  S3C2410_IRQ(57)
+#define IRQ_S3CUART_TX1  S3C2410_IRQ(58)
+#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
+
+#define IRQ_S3CUART_RX2  S3C2410_IRQ(60)
+#define IRQ_S3CUART_TX2  S3C2410_IRQ(61)
+#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
+
+#define IRQ_TC		 S3C2410_IRQ(63)
+#define IRQ_ADC		 S3C2410_IRQ(64)
+
+#define NR_IRQS (IRQ_ADC+1)
+
+
+#endif /* __ASM_ARCH_IRQ_H */
diff -Nru a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/map.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,148 @@
+/* linux/include/asm-arm/arch-s3c2410/map.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  12-May-2003 BJD  Created file
+ *  06-Jan-2003 BJD  Linux 2.6.0 version, moved bast specifics out
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+/* we have a bit of a tight squeeze to fit all our registers from
+ * 0xF00000000 upwards, since we use all of the nGCS space in some
+ * capacity, and also need to fit the S3C2410 registers in as well...
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ *
+ * Note, we are trying to remove some of these from the implementation
+ * as they are only useful to certain drivers...
+ */
+
+#define S3C2410_ADDR(x)	  (0xF0000000 + (x))
+
+/* interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C2410_VA_IRQ	   S3C2410_ADDR(0x00000000)
+#define S3C2410_PA_IRQ	   (0x4A000000)
+#define S3C2410_SZ_IRQ	   SZ_1M
+
+/* memory controller registers */
+#define S3C2410_VA_MEMCTRL S3C2410_ADDR(0x00100000)
+#define S3C2410_PA_MEMCTRL (0x48000000)
+#define S3C2410_SZ_MEMCTRL SZ_1M
+
+/* USB host controller */
+#define S3C2410_VA_USBHOST S3C2410_ADDR(0x00200000)
+#define S3C2410_PA_USBHOST (0x49000000)
+#define S3C2410_SZ_USBHOST SZ_1M
+
+/* DMA controller */
+#define S3C2410_VA_DMA	   S3C2410_ADDR(0x00300000)
+#define S3C2410_PA_DMA	   (0x4B000000)
+#define S3C2410_SZ_DMA	   SZ_1M
+
+/* Clock and Power management */
+#define S3C2410_VA_CLKPWR  S3C2410_ADDR(0x00400000)
+#define S3C2410_PA_CLKPWR  (0x4C000000)
+#define S3C2410_SZ_CLKPWR  SZ_1M
+
+/* LCD controller */
+#define S3C2410_VA_LCD	   S3C2410_ADDR(0x00600000)
+#define S3C2410_PA_LCD	   (0x4D000000)
+#define S3C2410_SZ_LCD	   SZ_1M
+
+/* NAND flash controller */
+#define S3C2410_VA_NAND	   S3C2410_ADDR(0x00700000)
+#define S3C2410_PA_NAND	   (0x4E000000)
+#define S3C2410_SZ_NAND	   SZ_1M
+
+/* UARTs */
+#define S3C2410_VA_UART	   S3C2410_ADDR(0x00800000)
+#define S3C2410_PA_UART	   (0x50000000)
+#define S3C2410_SZ_UART	   SZ_1M
+
+/* Timers */
+#define S3C2410_VA_TIMER   S3C2410_ADDR(0x00900000)
+#define S3C2410_PA_TIMER   (0x51000000)
+#define S3C2410_SZ_TIMER   SZ_1M
+
+/* USB Device port */
+#define S3C2410_VA_USBDEV  S3C2410_ADDR(0x00A00000)
+#define S3C2410_PA_USBDEV  (0x52000000)
+#define S3C2410_SZ_USBDEV  SZ_1M
+
+/* Watchdog */
+#define S3C2410_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
+#define S3C2410_PA_WATCHDOG (0x53000000)
+#define S3C2410_SZ_WATCHDOG SZ_1M
+
+/* IIC hardware controller */
+#define S3C2410_VA_IIC	   S3C2410_ADDR(0x00C00000)
+#define S3C2410_PA_IIC	   (0x54000000)
+#define S3C2410_SZ_IIC	   SZ_1M
+
+#define VA_IIC_BASE	   (S3C2410_VA_IIC)
+
+/* IIS controller */
+#define S3C2410_VA_IIS	   S3C2410_ADDR(0x00D00000)
+#define S3C2410_PA_IIS	   (0x55000000)
+#define S3C2410_SZ_IIS	   SZ_1M
+
+/* GPIO ports */
+#define S3C2410_VA_GPIO	   S3C2410_ADDR(0x00E00000)
+#define S3C2410_PA_GPIO	   (0x56000000)
+#define S3C2410_SZ_GPIO	   SZ_1M
+
+/* RTC */
+#define S3C2410_VA_RTC	   S3C2410_ADDR(0x00F00000)
+#define S3C2410_PA_RTC	   (0x57000000)
+#define S3C2410_SZ_RTC	   SZ_1M
+
+/* ADC */
+#define S3C2410_VA_ADC	   S3C2410_ADDR(0x01000000)
+#define S3C2410_PA_ADC	   (0x58000000)
+#define S3C2410_SZ_ADC	   SZ_1M
+
+/* SPI */
+#define S3C2410_VA_SPI	   S3C2410_ADDR(0x01100000)
+#define S3C2410_PA_SPI	   (0x59000000)
+#define S3C2410_SZ_SPI	   SZ_1M
+
+/* SDI */
+#define S3C2410_VA_SDI	   S3C2410_ADDR(0x01200000)
+#define S3C2410_PA_SDI	   (0x5A000000)
+#define S3C2410_SZ_SDI	   SZ_1M
+
+/* ISA style IO, for each machine to sort out mappings for, if it
+ * implements it. We reserve two 16M regions for ISA.
+ */
+
+#define S3C2410_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
+#define S3C2410_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C2410_CS0 (0x00000000)
+#define S3C2410_CS1 (0x08000000)
+#define S3C2410_CS2 (0x10000000)
+#define S3C2410_CS3 (0x18000000)
+#define S3C2410_CS4 (0x20000000)
+#define S3C2410_CS5 (0x28000000)
+#define S3C2410_CS6 (0x30000000)
+#define S3C2410_CS7 (0x38000000)
+
+#define S3C2410_SDRAM_PA    (S3C2410_CS6)
+
+
+#endif /* __ASM_ARCH_MAP_H */
diff -Nru a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/memory.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,61 @@
+/*
+ *  linux/include/asm-arm/arch-s3c2410/memory.h
+ *
+ *  from linux/include/asm-arm/arch-rpc/memory.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK	Created
+ *   31-Dec-1997 RMK	Fixed definitions to reduce warnings
+ *   11-Jan-1998 RMK	Uninlined to reduce hits on cache
+ *   08-Feb-1998 RMK	Added __virt_to_bus and __bus_to_virt
+ *   21-Mar-1999 RMK	Renamed to memory.h
+ *		 RMK	Added TASK_SIZE and PAGE_OFFSET
+ *   05-Apr-2004 BJD    Copied and altered for arch-s3c2410
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE	(0xbf000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (0x40000000)
+
+/*
+ * Page offset: 3GB
+ *
+ * DRAM starts at 0x30000000
+*/
+
+#define PAGE_OFFSET	(0xc0000000UL)
+#define PHYS_OFFSET	(0x30000000UL)
+
+#define __virt_to_phys__is_a_macro
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt__is_a_macro
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
+
+/*
+ * These are exactly the same on the S3C2410 as the
+ * physical memory view.
+*/
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff -Nru a/include/asm-arm/arch-s3c2410/param.h b/include/asm-arm/arch-s3c2410/param.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/param.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,27 @@
+/* linux/include/asm-arm/arch-s3c2410/param.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - Machine parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  02-Sep-2003 BJD  Created file
+ *  12-Mar-2004 BJD  Added include protection
+*/
+
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+/* we cannot get our timer down to 100Hz with the setup as is, but we can
+ * manage 200 clock ticks per second... if this is a problem, we can always
+ * add a software pre-scaler to the evil timer systems.
+*/
+
+#define __KERNEL_HZ   200
+
+#endif /* __ASM_ARCH_PARAM_H */
diff -Nru a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,72 @@
+/* linux/include/asm/arch-s3c2410/regs-clock.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 clock register definitions
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+ */
+
+
+
+#ifndef __ASM_ARM_REGS_CLOCK
+#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
+
+#define S3C2410_CLKREG(x) ((x) + S3C2410_VA_CLKPWR)
+
+#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
+
+#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
+#define S3C2410_MPLLCON	    S3C2410_CLKREG(0x04)
+#define S3C2410_UPLLCON	    S3C2410_CLKREG(0x08)
+#define S3C2410_CLKCON	    S3C2410_CLKREG(0x0C)
+#define S3C2410_CLKSLOW	    S3C2410_CLKREG(0x10)
+#define S3C2410_CLKDIVN	    S3C2410_CLKREG(0x14)
+
+#define S3C2410_PLLCON_MDIVSHIFT     12
+#define S3C2410_PLLCON_PDIVSHIFT     4
+#define S3C2410_PLLCON_SDIVSHIFT     0
+#define S3C2410_PLLCON_MDIVMASK	     ((1<<(1+(19-12)))-1)
+#define S3C2410_PLLCON_PDIVMASK	     ((1<<5)-1)
+#define S3C2410_PLLCON_SDIVMASK	     3
+
+/* DCLKCON register addresses in gpio.h */
+
+#define S3C2410_DCLKCON_DCLK0EN	     (1<<0)
+#define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
+#define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
+#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
+#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
+
+#define S3C2410_DCLKCON_DCLK1EN	     (1<<16)
+#define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
+#define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
+#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
+
+#define S3C2410_CLKDIVN_PDIVN	     (1<<0)
+#define S3C2410_CLKDIVN_HDIVN	     (1<<1)
+
+static inline unsigned int
+s3c2410_get_pll(int pllval, int baseclk)
+{
+  int mdiv, pdiv, sdiv;
+
+  mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
+  pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
+  sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
+
+  mdiv &= S3C2410_PLLCON_MDIVMASK;
+  pdiv &= S3C2410_PLLCON_PDIVMASK;
+  sdiv &= S3C2410_PLLCON_SDIVMASK;
+
+  return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
+}
+
+#endif /* __ASM_ARM_REGS_CLOCK */
diff -Nru a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,604 @@
+/* linux/include/asm/hardware/s3c2410/
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 GPIO register definitions
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    23-06-2003     BJD     Updated GSTATUS registers
+ *    12-03-2004     BJD     Updated include protection
+ */
+
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
+
+/* configure GPIO ports A..G */
+
+#define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO)
+
+/* port A - 22bits, zero in bit X makes pin X output
+ * 1 makes port special function, this is default
+*/
+#define S3C2410_GPACON	   S3C2410_GPIOREG(0x00)
+#define S3C2410_GPADAT	   S3C2410_GPIOREG(0x04)
+
+/* 0x08 and 0x0c are reserved */
+
+/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
+ *   00 = input, 01 = output, 10=special function, 11=reserved
+ * bit 0,1 = pin 0, 2,3= pin 1...
+ *
+ * CPBUP = pull up resistor control, 1=disabled, 0=enabled
+*/
+
+#define S3C2410_GPBCON	   S3C2410_GPIOREG(0x10)
+#define S3C2410_GPBDAT	   S3C2410_GPIOREG(0x14)
+#define S3C2410_GPBUP	   S3C2410_GPIOREG(0x18)
+
+/* no i/o pin in port b can have value 3! */
+
+#define S3C2410_GPB0_INP     (0x00 << 0)
+#define S3C2410_GPB0_OUTP    (0x01 << 0)
+#define S3C2410_GPB0_TOUT0   (0x02 << 0)
+
+#define S3C2410_GPB1_INP     (0x00 << 2)
+#define S3C2410_GPB1_OUTP    (0x01 << 2)
+#define S3C2410_GPB1_TOUT1   (0x02 << 2)
+
+#define S3C2410_GPB2_INP     (0x00 << 4)
+#define S3C2410_GPB2_OUTP    (0x01 << 4)
+#define S3C2410_GPB2_TOUT2   (0x02 << 4)
+
+#define S3C2410_GPB3_INP     (0x00 << 6)
+#define S3C2410_GPB3_OUTP    (0x01 << 6)
+#define S3C2410_GPB3_TOUT3   (0x02 << 6)
+
+#define S3C2410_GPB4_INP     (0x00 << 8)
+#define S3C2410_GPB4_OUTP    (0x01 << 8)
+#define S3C2410_GPB4_TCLK0   (0x02 << 8)
+#define S3C2410_GPB4_MASK    (0x03 << 8)
+
+#define S3C2410_GPB5_INP     (0x00 << 10)
+#define S3C2410_GPB5_OUTP    (0x01 << 10)
+#define S3C2410_GPB5_nXBACK  (0x02 << 10)
+
+#define S3C2410_GPB6_INP     (0x00 << 12)
+#define S3C2410_GPB6_OUTP    (0x01 << 12)
+#define S3C2410_GPB6_nXBREQ  (0x02 << 12)
+
+#define S3C2410_GPB7_INP     (0x00 << 14)
+#define S3C2410_GPB7_OUTP    (0x01 << 14)
+#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
+
+#define S3C2410_GPB8_INP     (0x00 << 16)
+#define S3C2410_GPB8_OUTP    (0x01 << 16)
+#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
+
+#define S3C2410_GPB9_INP     (0x00 << 18)
+#define S3C2410_GPB9_OUTP    (0x01 << 18)
+#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
+
+#define S3C2410_GPB10_INP     (0x00 << 18)
+#define S3C2410_GPB10_OUTP    (0x01 << 18)
+#define S3C2410_GPB10_nXDRE0 (0x02 << 18)
+
+/* Port C consits of 16 GPIO/Special function
+ *
+ * almost identical setup to port b, but the special functions are mostly
+ * to do with the video system's sync/etc.
+*/
+
+#define S3C2410_GPCCON	   S3C2410_GPIOREG(0x20)
+#define S3C2410_GPCDAT	   S3C2410_GPIOREG(0x24)
+#define S3C2410_GPCUP	   S3C2410_GPIOREG(0x28)
+
+#define S3C2410_GPC0_INP	(0x00 << 0)
+#define S3C2410_GPC0_OUTP	(0x01 << 0)
+#define S3C2410_GPC0_LEND	(0x02 << 0)
+
+#define S3C2410_GPC1_INP	(0x00 << 2)
+#define S3C2410_GPC1_OUTP	(0x01 << 2)
+#define S3C2410_GPC1_VCLK	(0x02 << 2)
+
+#define S3C2410_GPC2_INP	(0x00 << 4)
+#define S3C2410_GPC2_OUTP	(0x01 << 4)
+#define S3C2410_GPC2_VLINE	(0x02 << 4)
+
+#define S3C2410_GPC3_INP	(0x00 << 6)
+#define S3C2410_GPC3_OUTP	(0x01 << 6)
+#define S3C2410_GPC3_VFRAME	(0x02 << 6)
+
+#define S3C2410_GPC4_INP	(0x00 << 8)
+#define S3C2410_GPC4_OUTP	(0x01 << 8)
+#define S3C2410_GPC4_VM		(0x02 << 8)
+
+#define S3C2410_GPC5_INP	(0x00 << 10)
+#define S3C2410_GPC5_OUTP	(0x01 << 10)
+#define S3C2410_GPC5_LCDVF0	(0x02 << 10)
+
+#define S3C2410_GPC6_INP	(0x00 << 12)
+#define S3C2410_GPC6_OUTP	(0x01 << 12)
+#define S3C2410_GPC6_LCDVF1	(0x02 << 12)
+
+#define S3C2410_GPC7_INP	(0x00 << 14)
+#define S3C2410_GPC7_OUTP	(0x01 << 14)
+#define S3C2410_GPC7_LCDVF2	(0x02 << 14)
+
+#define S3C2410_GPC8_INP	(0x00 << 16)
+#define S3C2410_GPC8_OUTP	(0x01 << 16)
+#define S3C2410_GPC8_VD0	(0x02 << 16)
+
+#define S3C2410_GPC9_INP	(0x00 << 18)
+#define S3C2410_GPC9_OUTP	(0x01 << 18)
+#define S3C2410_GPC9_VD1	(0x02 << 18)
+
+#define S3C2410_GPC10_INP	(0x00 << 20)
+#define S3C2410_GPC10_OUTP	(0x01 << 20)
+#define S3C2410_GPC10_VD2	(0x02 << 20)
+
+#define S3C2410_GPC11_INP	(0x00 << 22)
+#define S3C2410_GPC11_OUTP	(0x01 << 22)
+#define S3C2410_GPC11_VD3	(0x02 << 22)
+
+#define S3C2410_GPC12_INP	(0x00 << 24)
+#define S3C2410_GPC12_OUTP	(0x01 << 24)
+#define S3C2410_GPC12_VD4	(0x02 << 24)
+
+#define S3C2410_GPC13_INP	(0x00 << 26)
+#define S3C2410_GPC13_OUTP	(0x01 << 26)
+#define S3C2410_GPC13_VD5	(0x02 << 26)
+
+#define S3C2410_GPC14_INP	(0x00 << 28)
+#define S3C2410_GPC14_OUTP	(0x01 << 28)
+#define S3C2410_GPC14_VD6	(0x02 << 28)
+
+#define S3C2410_GPC15_INP	(0x00 << 30)
+#define S3C2410_GPC15_OUTP	(0x01 << 30)
+#define S3C2410_GPC15_VD7	(0x02 << 30)
+
+/* Port D consists of 16 GPIO/Special function
+ *
+ * almost identical setup to port b, but the special functions are mostly
+ * to do with the video system's data.
+*/
+
+#define S3C2410_GPDCON	   S3C2410_GPIOREG(0x30)
+#define S3C2410_GPDDAT	   S3C2410_GPIOREG(0x34)
+#define S3C2410_GPDUP	   S3C2410_GPIOREG(0x38)
+
+#define S3C2410_GPD0_INP	(0x00 << 0)
+#define S3C2410_GPD0_OUTP	(0x01 << 0)
+#define S3C2410_GPD0_VD8	(0x02 << 0)
+
+#define S3C2410_GPD1_INP	(0x00 << 2)
+#define S3C2410_GPD1_OUTP	(0x01 << 2)
+#define S3C2410_GPD1_VD9	(0x02 << 2)
+
+#define S3C2410_GPD2_INP	(0x00 << 4)
+#define S3C2410_GPD2_OUTP	(0x01 << 4)
+#define S3C2410_GPD2_VD10	(0x02 << 4)
+
+#define S3C2410_GPD3_INP	(0x00 << 6)
+#define S3C2410_GPD3_OUTP	(0x01 << 6)
+#define S3C2410_GPD3_VD11	(0x02 << 6)
+
+#define S3C2410_GPD4_INP	(0x00 << 8)
+#define S3C2410_GPD4_OUTP	(0x01 << 8)
+#define S3C2410_GPD4_VD12	(0x02 << 8)
+
+#define S3C2410_GPD5_INP	(0x00 << 10)
+#define S3C2410_GPD5_OUTP	(0x01 << 10)
+#define S3C2410_GPD5_VD13	(0x02 << 10)
+
+#define S3C2410_GPD6_INP	(0x00 << 12)
+#define S3C2410_GPD6_OUTP	(0x01 << 12)
+#define S3C2410_GPD6_VD14	(0x02 << 12)
+
+#define S3C2410_GPD7_INP	(0x00 << 14)
+#define S3C2410_GPD7_OUTP	(0x01 << 14)
+#define S3C2410_GPD7_VD15	(0x02 << 14)
+
+#define S3C2410_GPD8_INP	(0x00 << 16)
+#define S3C2410_GPD8_OUTP	(0x01 << 16)
+#define S3C2410_GPD8_VD16	(0x02 << 16)
+
+#define S3C2410_GPD9_INP	(0x00 << 18)
+#define S3C2410_GPD9_OUTP	(0x01 << 18)
+#define S3C2410_GPD9_VD17	(0x02 << 18)
+
+#define S3C2410_GPD10_INP	(0x00 << 20)
+#define S3C2410_GPD10_OUTP	(0x01 << 20)
+#define S3C2410_GPD10_VD18	(0x02 << 20)
+
+#define S3C2410_GPD11_INP	(0x00 << 22)
+#define S3C2410_GPD11_OUTP	(0x01 << 22)
+#define S3C2410_GPD11_VD19	(0x02 << 22)
+
+#define S3C2410_GPD12_INP	(0x00 << 24)
+#define S3C2410_GPD12_OUTP	(0x01 << 24)
+#define S3C2410_GPD12_VD20	(0x02 << 24)
+
+#define S3C2410_GPD13_INP	(0x00 << 26)
+#define S3C2410_GPD13_OUTP	(0x01 << 26)
+#define S3C2410_GPD13_VD21	(0x02 << 26)
+
+#define S3C2410_GPD14_INP	(0x00 << 28)
+#define S3C2410_GPD14_OUTP	(0x01 << 28)
+#define S3C2410_GPD14_VD22	(0x02 << 28)
+
+#define S3C2410_GPD15_INP	(0x00 << 30)
+#define S3C2410_GPD15_OUTP	(0x01 << 30)
+#define S3C2410_GPD15_VD23	(0x02 << 30)
+
+/* Port E consists of 16 GPIO/Special function
+ *
+ * again, the same as port B, but dealing with I2S, SDI, and
+ * more miscellaneous functions
+*/
+
+#define S3C2410_GPECON	   S3C2410_GPIOREG(0x40)
+#define S3C2410_GPEDAT	   S3C2410_GPIOREG(0x44)
+#define S3C2410_GPEUP	   S3C2410_GPIOREG(0x48)
+
+#define S3C2410_GPE0_INP       (0x00 << 0)
+#define S3C2410_GPE0_OUTP      (0x01 << 0)
+#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
+#define S3C2410_GPE0_MASK      (0x03 << 0)
+
+#define S3C2410_GPE1_INP       (0x00 << 2)
+#define S3C2410_GPE1_OUTP      (0x01 << 2)
+#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
+#define S3C2410_GPE1_MASK      (0x03 << 2)
+
+#define S3C2410_GPE2_INP       (0x00 << 4)
+#define S3C2410_GPE2_OUTP      (0x01 << 4)
+#define S3C2410_GPE2_CDCLK     (0x02 << 4)
+
+#define S3C2410_GPE3_INP       (0x00 << 6)
+#define S3C2410_GPE3_OUTP      (0x01 << 6)
+#define S3C2410_GPE3_I2SSDI    (0x02 << 6)
+#define S3C2410_GPE3_MASK      (0x03 << 6)
+
+#define S3C2410_GPE4_INP       (0x00 << 8)
+#define S3C2410_GPE4_OUTP      (0x01 << 8)
+#define S3C2410_GPE4_I2SSDO    (0x02 << 8)
+#define S3C2410_GPE4_MASK      (0x03 << 8)
+
+#define S3C2410_GPE5_INP       (0x00 << 10)
+#define S3C2410_GPE5_OUTP      (0x01 << 10)
+#define S3C2410_GPE5_SDCLK     (0x02 << 10)
+
+#define S3C2410_GPE6_INP       (0x00 << 12)
+#define S3C2410_GPE6_OUTP      (0x01 << 12)
+#define S3C2410_GPE6_SDCLK     (0x02 << 12)
+
+#define S3C2410_GPE7_INP       (0x00 << 14)
+#define S3C2410_GPE7_OUTP      (0x01 << 14)
+#define S3C2410_GPE7_SDCMD     (0x02 << 14)
+
+#define S3C2410_GPE8_INP       (0x00 << 16)
+#define S3C2410_GPE8_OUTP      (0x01 << 16)
+#define S3C2410_GPE8_SDDAT1    (0x02 << 16)
+
+#define S3C2410_GPE9_INP       (0x00 << 18)
+#define S3C2410_GPE9_OUTP      (0x01 << 18)
+#define S3C2410_GPE9_SDDAT2    (0x02 << 18)
+
+#define S3C2410_GPE10_INP      (0x00 << 20)
+#define S3C2410_GPE10_OUTP     (0x01 << 20)
+#define S3C2410_GPE10_SDDAT3   (0x02 << 20)
+
+#define S3C2410_GPE11_INP      (0x00 << 22)
+#define S3C2410_GPE11_OUTP     (0x01 << 22)
+#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
+
+#define S3C2410_GPE12_INP      (0x00 << 24)
+#define S3C2410_GPE12_OUTP     (0x01 << 24)
+#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
+
+#define S3C2410_GPE13_INP      (0x00 << 26)
+#define S3C2410_GPE13_OUTP     (0x01 << 26)
+#define S3C2410_GPE13_SPICLK0  (0x02 << 26)
+
+#define S3C2410_GPE14_INP      (0x00 << 28)
+#define S3C2410_GPE14_OUTP     (0x01 << 28)
+#define S3C2410_GPE14_IICSCL   (0x02 << 28)
+#define S3C2410_GPE14_MASK     (0x03 << 28)
+
+#define S3C2410_GPE15_INP      (0x00 << 30)
+#define S3C2410_GPE15_OUTP     (0x01 << 30)
+#define S3C2410_GPE15_IICSDA   (0x02 << 30)
+#define S3C2410_GPE15_MASK     (0x03 << 30)
+
+#define S3C2410_GPE_PUPDIS(x)  (1<<(x))
+
+/* Port F consists of 8 GPIO/Special function
+ *
+ * GPIO / interrupt inputs
+ *
+ * GPFCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPFCON	   S3C2410_GPIOREG(0x50)
+#define S3C2410_GPFDAT	   S3C2410_GPIOREG(0x54)
+#define S3C2410_GPFUP	   S3C2410_GPIOREG(0x58)
+
+
+#define S3C2410_GPF0_INP    (0x00 << 0)
+#define S3C2410_GPF0_OUTP   (0x01 << 0)
+#define S3C2410_GPF0_EINT0  (0x02 << 0)
+
+#define S3C2410_GPF1_INP    (0x00 << 2)
+#define S3C2410_GPF1_OUTP   (0x01 << 2)
+#define S3C2410_GPF1_EINT1  (0x02 << 2)
+
+#define S3C2410_GPF2_INP    (0x00 << 4)
+#define S3C2410_GPF2_OUTP   (0x01 << 4)
+#define S3C2410_GPF2_EINT2  (0x02 << 4)
+
+#define S3C2410_GPF3_INP    (0x00 << 6)
+#define S3C2410_GPF3_OUTP   (0x01 << 6)
+#define S3C2410_GPF3_EINT3  (0x02 << 6)
+
+#define S3C2410_GPF4_INP    (0x00 << 8)
+#define S3C2410_GPF4_OUTP   (0x01 << 8)
+#define S3C2410_GPF4_EINT4  (0x02 << 8)
+
+#define S3C2410_GPF5_INP    (0x00 << 10)
+#define S3C2410_GPF5_OUTP   (0x01 << 10)
+#define S3C2410_GPF5_EINT5  (0x02 << 10)
+
+#define S3C2410_GPF6_INP    (0x00 << 12)
+#define S3C2410_GPF6_OUTP   (0x01 << 12)
+#define S3C2410_GPF6_EINT6  (0x02 << 12)
+
+#define S3C2410_GPF7_INP    (0x00 << 14)
+#define S3C2410_GPF7_OUTP   (0x01 << 14)
+#define S3C2410_GPF7_EINT7  (0x02 << 14)
+
+/* Port G consists of 8 GPIO/IRQ/Special function
+ *
+ * GPGCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPGCON	   S3C2410_GPIOREG(0x60)
+#define S3C2410_GPGDAT	   S3C2410_GPIOREG(0x64)
+#define S3C2410_GPGUP	   S3C2410_GPIOREG(0x68)
+
+#define S3C2410_GPG0_INP      (0x00 << 0)
+#define S3C2410_GPG0_OUTP     (0x01 << 0)
+#define S3C2410_GPG0_EINT8    (0x02 << 0)
+
+#define S3C2410_GPG1_INP      (0x00 << 2)
+#define S3C2410_GPG1_OUTP     (0x01 << 2)
+#define S3C2410_GPG1_EINT9    (0x02 << 2)
+
+#define S3C2410_GPG2_INP      (0x00 << 4)
+#define S3C2410_GPG2_OUTP     (0x01 << 4)
+#define S3C2410_GPG2_EINT10   (0x02 << 4)
+
+#define S3C2410_GPG3_INP      (0x00 << 6)
+#define S3C2410_GPG3_OUTP     (0x01 << 6)
+#define S3C2410_GPG3_EINT11   (0x02 << 6)
+
+#define S3C2410_GPG4_INP      (0x00 << 8)
+#define S3C2410_GPG4_OUTP     (0x01 << 8)
+#define S3C2410_GPG4_EINT12   (0x02 << 8)
+#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
+
+#define S3C2410_GPG5_INP      (0x00 << 10)
+#define S3C2410_GPG5_OUTP     (0x01 << 10)
+#define S3C2410_GPG5_EINT13   (0x02 << 10)
+#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
+
+#define S3C2410_GPG6_INP      (0x00 << 12)
+#define S3C2410_GPG6_OUTP     (0x01 << 12)
+#define S3C2410_GPG6_EINT14   (0x02 << 12)
+#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
+
+#define S3C2410_GPG7_INP      (0x00 << 14)
+#define S3C2410_GPG7_OUTP     (0x01 << 14)
+#define S3C2410_GPG7_EINT15   (0x02 << 14)
+#define S3C2410_GPG7_SPICLK1  (0x03 << 14)
+
+#define S3C2410_GPG8_INP      (0x00 << 16)
+#define S3C2410_GPG8_OUTP     (0x01 << 16)
+#define S3C2410_GPG8_EINT16   (0x02 << 16)
+
+#define S3C2410_GPG9_INP      (0x00 << 18)
+#define S3C2410_GPG9_OUTP     (0x01 << 18)
+#define S3C2410_GPG9_EINT17   (0x02 << 18)
+
+#define S3C2410_GPG10_INP     (0x00 << 20)
+#define S3C2410_GPG10_OUTP    (0x01 << 20)
+#define S3C2410_GPG10_EINT18  (0x02 << 20)
+
+#define S3C2410_GPG11_INP     (0x00 << 22)
+#define S3C2410_GPG11_OUTP    (0x01 << 22)
+#define S3C2410_GPG11_EINT19  (0x02 << 22)
+#define S3C2410_GPG11_TCLK1   (0x03 << 22)
+
+#define S3C2410_GPG12_INP     (0x00 << 24)
+#define S3C2410_GPG12_OUTP    (0x01 << 24)
+#define S3C2410_GPG12_EINT18  (0x02 << 24)
+#define S3C2410_GPG12_XMON    (0x03 << 24)
+
+#define S3C2410_GPG13_INP     (0x00 << 26)
+#define S3C2410_GPG13_OUTP    (0x01 << 26)
+#define S3C2410_GPG13_EINT18  (0x02 << 26)
+#define S3C2410_GPG13_nXPON   (0x03 << 26)
+
+#define S3C2410_GPG14_INP     (0x00 << 28)
+#define S3C2410_GPG14_OUTP    (0x01 << 28)
+#define S3C2410_GPG14_EINT18  (0x02 << 28)
+#define S3C2410_GPG14_YMON    (0x03 << 28)
+
+#define S3C2410_GPG15_INP     (0x00 << 30)
+#define S3C2410_GPG15_OUTP    (0x01 << 30)
+#define S3C2410_GPG15_EINT18  (0x02 << 30)
+#define S3C2410_GPG15_nYPON   (0x03 << 30)
+
+
+#define S3C2410_GPG_PUPDIS(x)  (1<<(x))
+
+/* Port H consists of11 GPIO/serial/Misc pins
+ *
+ * GPGCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPHCON	   S3C2410_GPIOREG(0x70)
+#define S3C2410_GPHDAT	   S3C2410_GPIOREG(0x74)
+#define S3C2410_GPHUP	   S3C2410_GPIOREG(0x78)
+
+#define S3C2410_GPH0_INP    (0x00 << 0)
+#define S3C2410_GPH0_OUTP   (0x01 << 0)
+#define S3C2410_GPH0_nCTS0  (0x02 << 0)
+
+#define S3C2410_GPH1_INP    (0x00 << 2)
+#define S3C2410_GPH1_OUTP   (0x01 << 2)
+#define S3C2410_GPH1_nRTS0  (0x02 << 2)
+
+#define S3C2410_GPH2_INP    (0x00 << 4)
+#define S3C2410_GPH2_OUTP   (0x01 << 4)
+#define S3C2410_GPH2_TXD0   (0x02 << 4)
+
+#define S3C2410_GPH3_INP    (0x00 << 6)
+#define S3C2410_GPH3_OUTP   (0x01 << 6)
+#define S3C2410_GPH3_RXD0   (0x02 << 6)
+
+#define S3C2410_GPH4_INP    (0x00 << 8)
+#define S3C2410_GPH4_OUTP   (0x01 << 8)
+#define S3C2410_GPH4_TXD1   (0x02 << 8)
+
+#define S3C2410_GPH5_INP    (0x00 << 10)
+#define S3C2410_GPH5_OUTP   (0x01 << 10)
+#define S3C2410_GPH5_RXD1   (0x02 << 10)
+
+#define S3C2410_GPH6_INP    (0x00 << 12)
+#define S3C2410_GPH6_OUTP   (0x01 << 12)
+#define S3C2410_GPH6_TXD2   (0x02 << 12)
+#define S3C2410_GPH6_nRTS1  (0x03 << 12)
+
+#define S3C2410_GPH7_INP    (0x00 << 14)
+#define S3C2410_GPH7_OUTP   (0x01 << 14)
+#define S3C2410_GPH7_RXD2   (0x02 << 14)
+#define S3C2410_GPH7_nCTS1  (0x03 << 14)
+
+#define S3C2410_GPH8_INP    (0x00 << 16)
+#define S3C2410_GPH8_OUTP   (0x01 << 16)
+#define S3C2410_GPH8_UCLK   (0x02 << 16)
+
+#define S3C2410_GPH9_INP     (0x00 << 18)
+#define S3C2410_GPH9_OUTP    (0x01 << 18)
+#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
+
+#define S3C2410_GPH10_INP   (0x00 << 20)
+#define S3C2410_GPH10_OUTP  (0x01 << 20)
+#define S3C2410_GPH10_CLKOUT1  (0x02 << 20)
+
+/* miscellaneous control */
+
+#define S3C2410_MISCCR	   S3C2410_GPIOREG(0x80)
+#define S3C2410_DCLKCON	   S3C2410_GPIOREG(0x84)
+
+/* see clock.h for dclk definitions */
+
+/* pullup control on databus */
+#define S3C2410_MISCCR_SPUCR_HEN    (0)
+#define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
+#define S3C2410_MISCCR_SPUCR_LEN    (0)
+#define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
+
+#define S3C2410_MISCCR_USBDEV	    (0)
+#define S3C2410_MISCCR_USBHOST	    (1<<3)
+
+#define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
+#define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
+#define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
+#define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
+#define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
+#define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
+
+#define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
+#define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
+#define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
+#define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
+#define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
+#define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
+
+#define S3C2410_MISCCR_USBSUSPND0   (1<<12)
+#define S3C2410_MISCCR_USBSUSPND1   (1<<13)
+
+#define S3C2410_MISCCR_nRSTCON	    (1<<16)
+
+/* external interrupt control... */
+/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
+ * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
+ * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
+ *
+ * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
+ *
+ * Samsung datasheet p9-25
+*/
+
+#define S3C2410_EXTINT0	   S3C2410_GPIOREG(0x88)
+#define S3C2410_EXTINT1	   S3C2410_GPIOREG(0x8C)
+#define S3C2410_EXTINT2	   S3C2410_GPIOREG(0x90)
+
+/* values for S3C2410_EXTINT0/1/2 */
+#define S3C2410_EXTINT_LOWLEV	 (0x00)
+#define S3C2410_EXTINT_HILEV	 (0x01)
+#define S3C2410_EXTINT_FALLEDGE	 (0x02)
+#define S3C2410_EXTINT_RISEEDGE	 (0x04)
+#define S3C2410_EXTINT_BOTHEDGE	 (0x06)
+
+/* interrupt filtering conrrol for EINT16..EINT23 */
+#define S3C2410_EINFLT0	   S3C2410_GPIOREG(0x94)
+#define S3C2410_EINFLT1	   S3C2410_GPIOREG(0x98)
+#define S3C2410_EINFLT2	   S3C2410_GPIOREG(0x9C)
+#define S3C2410_EINFLT3	   S3C2410_GPIOREG(0xA0)
+
+/* mask: 0=enable, 1=disable
+ * 1 bit EINT, 4=EINT4, 23=EINT23
+ * EINT0,1,2,3 are not handled here.
+*/
+#define S3C2410_EINTMASK   S3C2410_GPIOREG(0xA4)
+#define S3C2410_EINTPEND   S3C2410_GPIOREG(0xA8)
+
+/* GSTATUS have miscellaneous information in them
+ *
+ */
+
+#define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
+#define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
+#define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
+#define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
+#define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
+
+#define S3C2410_GSTATUS0_nWAIT	   (1<<3)
+#define S3C2410_GSTATUS0_NCON	   (1<<2)
+#define S3C2410_GSTATUS0_RnB	   (1<<1)
+#define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
+
+#define S3C2410_GSTATUS2_WTRESET   (1<<2)
+#define S3C2410_GSTATUs2_OFFRESET  (1<<1)
+#define S3C2410_GSTATUS2_PONRESET  (1<<0)
+
+#endif	/* __ASM_ARCH_REGS_GPIO_H */
+
diff -Nru a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,63 @@
+/* linux/include/asm/arch-s3c2410/regs-iis.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 IIS register definition
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    26-06-2003     BJD     Finished off definitions for register addresses
+ *    12-03-2004     BJD     Updated include protection
+ */
+
+#ifndef __ASM_ARCH_REGS_IIS_H
+#define __ASM_ARCH_REGS_IIS_H
+
+#define S3C2410_IISCON	 (S3C2410_VA_IIS + 0x00)
+
+#define S3C2410_IISCON_LRINDEX	  (1<<8)
+#define S3C2410_IISCON_TXFIFORDY  (1<<7)
+#define S3C2410_IISCON_RXFIFORDY  (1<<6)
+#define S3C2410_IISCON_TXDMAEN	  (1<<5)
+#define S3C2410_IISCON_RXDMAEN	  (1<<4)
+#define S3C2410_IISCON_TXIDLE	  (1<<3)
+#define S3C2410_IISCON_RXIDLE	  (1<<2)
+#define S3C2410_IISCON_IISEN	  (1<<0)
+
+#define S3C2410_IISMOD	 (S3C2410_VA_IIS + 0x04)
+
+#define S3C2410_IISMOD_SLAVE	  (1<<8)
+#define S3C2410_IISMOD_NOXFER	  (0<<6)
+#define S3C2410_IISMOD_RXMODE	  (1<<6)
+#define S3C2410_IISMOD_TXMODE	  (2<<6)
+#define S3C2410_IISMOD_TXRXMODE	  (3<<6)
+#define S3C2410_IISMOD_LR_LLOW	  (0<<5)
+#define S3C2410_IISMOD_LR_RLOW	  (1<<5)
+#define S3C2410_IISMOD_IIS	  (0<<4)
+#define S3C2410_IISMOD_MSB	  (1<<4)
+#define S3C2410_IISMOD_8BIT	  (0<<3)
+#define S3C2410_IISMOD_16BIT	  (1<<3)
+#define S3C2410_IISMOD_256FS	  (0<<1)
+#define S3C2410_IISMOD_384FS	  (1<<1)
+#define S3C2410_IISMOD_16FS	  (0<<0)
+#define S3C2410_IISMOD_32FS	  (1<<0)
+#define S3C2410_IISMOD_48FS	  (2<<0)
+
+#define S3C2410_IISPSR	 (S3C2410_VA_IIS + 0x08)
+
+#define S3C2410_IISFCON  (S3C2410_VA_IIS + 0x0c)
+
+#define S3C2410_IISFCON_TXDMA	  (1<<15)
+#define S3C2410_IISFCON_RXDMA	  (1<<14)
+#define S3C2410_IISFCON_TXENABLE  (1<<13)
+#define S3C2410_IISFCON_RXENABLE  (1<<12)
+
+#define S3C2410_IISFIFO  (S3C2410_VA_IIS + 0x10)
+
+#endif /* __ASM_ARCH_REGS_IIS_H */
+
diff -Nru a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-irq.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,38 @@
+/* linux/include/asm/arch-s3c2410/regs-irq.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+ */
+
+
+#ifndef ___ASM_ARCH_REGS_IRQ_H
+#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
+
+/* interrupt controller */
+
+#define S3C2410_IRQREG(x)   ((x) + S3C2410_VA_IRQ)
+#define S3C2410_EINTREG(x)  ((x) + S3C2410_VA_GPIO)
+
+#define S3C2410_SRCPND	       S3C2410_IRQREG(0x000)
+#define S3C2410_INTMOD	       S3C2410_IRQREG(0x004)
+#define S3C2410_INTMSK	       S3C2410_IRQREG(0x008)
+#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
+#define S3C2410_INTPND	       S3C2410_IRQREG(0x010)
+#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
+#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
+#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
+
+#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
+#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
+
+#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff -Nru a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,107 @@
+/* linux/include/asm/arch-s3c2410/regs-lcd.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ *
+ *  Changelog:
+ *    12-06-2003     BJD     Created file
+ *    26-06-2003     BJD     Updated LCDCON register definitions
+ *    12-03-2004     BJD     Updated include protection
+*/
+
+
+#ifndef ___ASM_ARCH_REGS_LCD_H
+#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
+
+#define S3C2410_LCDREG(x) ((x) + S3C2410_VA_LCD)
+
+/* LCD control registers */
+#define S3C2410_LCDCON1	    S3C2410_LCDREG(0x00)
+#define S3C2410_LCDCON2	    S3C2410_LCDREG(0x04)
+#define S3C2410_LCDCON3	    S3C2410_LCDREG(0x08)
+#define S3C2410_LCDCON4	    S3C2410_LCDREG(0x0C)
+#define S3C2410_LCDCON5	    S3C2410_LCDREG(0x10)
+
+#define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
+#define S3C2410_LCDCON1_MMODE	   (1<<6)
+#define S3C2410_LCDCON1_DSCAN4	   (0<<5)
+#define S3C2410_LCDCON1_STN4	   (1<<5)
+#define S3C2410_LCDCON1_STN8	   (2<<5)
+#define S3C2410_LCDCON1_TFT	   (3<<5)
+
+#define S3C2410_LCDCON1_STN1BPP	   (0<<1)
+#define S3C2410_LCDCON1_STN2GREY   (1<<1)
+#define S3C2410_LCDCON1_STN4GREY   (2<<1)
+#define S3C2410_LCDCON1_STN8BPP	   (3<<1)
+#define S3C2410_LCDCON1_STN12BPP   (4<<1)
+
+#define S3C2410_LCDCON1_TFT1BPP	   (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP	   (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP	   (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP	   (11<<1)
+#define S3C2410_LCDCON1_TFT16BPP   (12<<1)
+#define S3C2410_LCDCON1_TFT24BPP   (13<<1)
+
+#define S3C2410_LCDCON1_ENVDI	   (1)
+
+#define S3C2410_LCDCON2_VBPD(x)	    ((x) << 24)
+#define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
+#define S3C2410_LCDCON2_VFPD(x)	    ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)	    ((x) << 0)
+
+#define S3C2410_LCDCON3_HBPD(x)	    ((x) << 25)
+#define S3C2410_LCDCON3_WDLY(x)	    ((x) << 25)
+#define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
+#define S3C2410_LCDCON3_HFPD(x)	    ((x) << 0)
+#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
+
+#define S3C2410_LCDCON4_MVAL(x)	    ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)	    ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)	    ((x) << 0)
+
+#define S3C2410_LCDCON5_BPP24BL	    (1<<12)
+#define S3C2410_LCDCON5_FRM565	    (1<<11)
+#define S3C2410_LCDCON5_INVVCLK	    (1<<10)
+#define S3C2410_LCDCON5_INVVLINE    (1<<9)
+#define S3C2410_LCDCON5_INVVFRAME   (1<<8)
+#define S3C2410_LCDCON5_INVVD	    (1<<7)
+#define S3C2410_LCDCON5_INVVDEN	    (1<<6)
+#define S3C2410_LCDCON5_INVPWREN    (1<<5)
+#define S3C2410_LCDCON5_INVLEND	    (1<<4)
+#define S3C2410_LCDCON5_PWREN	    (1<<3)
+#define S3C2410_LCDCON5_ENLEND	    (1<<2)
+#define S3C2410_LCDCON5_BSWP	    (1<<1)
+#define S3C2410_LCDCON5_HWSWP	    (1<<0)
+
+/* framebuffer start addressed */
+#define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
+#define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
+#define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
+
+/* colour lookup and miscellaneous controls */
+
+#define S3C2410_REDLUT	   S3C2410_LCDREG(0x20)
+#define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
+#define S3C2410_BLUELUT	   S3C2410_LCDREG(0x28)
+
+#define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
+#define S3C2410_TPAL	   S3C2410_LCDREG(0x50)
+
+/* interrupt info */
+#define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
+#define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
+#define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
+#define S3C2410_LPCSEL	   S3C2410_LCDREG(0x60)
+
+#define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
+
+#endif /* ___ASM_ARCH_REGS_LCD_H */
+
+
+
diff -Nru a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/arch-s3c2410/regs-rtc.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-rtc.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,63 @@
+/* linux/include/asm/arch-s3c2410/regs-rtc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Internal RTC register definition
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+*/
+
+#ifndef __ASM_ARCH_REGS_RTC_H
+#define __ASM_ARCH_REGS_RTC_H __FILE__
+
+#define S3C2410_RTCREG(x) ((x) + S3C2410_VA_RTC)
+
+#define S3C2410_RTCCON	      S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN  (1<<0)
+#define S3C2410_RTCCON_CLKRST (1<<3)
+
+#define S3C2410_TICNT	      S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE  (1<<7)
+
+#define S3C2410_RTCALM	      S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN  (1<<6)
+#define S3C2410_RTCALM_YEAREN (1<<5)
+#define S3C2410_RTCALM_MONEN  (1<<4)
+#define S3C2410_RTCALM_DAYEN  (1<<3)
+#define S3C2410_RTCALM_HOUREN (1<<2)
+#define S3C2410_RTCALM_MINEN  (1<<1)
+#define S3C2410_RTCALM_SECEN  (1<<0)
+
+#define S3C2410_RTCALM_ALL \
+  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
+  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
+  S3C2410_RTCALM_SECEN
+
+
+#define S3C2410_ALMSEC	      S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN	      S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR	      S3C2410_RTCREG(0x5c)
+
+#define S3C2410_ALMDATE	      S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON	      S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR	      S3C2410_RTCREG(0x68)
+
+#define S3C2410_RTCRST	      S3C2410_RTCREG(0x6c)
+
+#define S3C2410_RTCSEC	      S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN	      S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR	      S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE	      S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCDAY	      S3C2410_RTCREG(0x80)
+#define S3C2410_RTCMON	      S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR	      S3C2410_RTCREG(0x88)
+
+
+#endif /* __ASM_ARCH_REGS_RTC_H */
diff -Nru a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,140 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
+ *
+ *  From linux/include/asm-arm/hardware/serial_s3c2410.h
+ *
+ *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
+ *
+ *  Adapted from:
+ *
+ *  Internal header file for MX1ADS serial ports (UART1 & 2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define S3C2410_VA_UART0      (S3C2410_VA_UART)
+#define S3C2410_VA_UART1      (S3C2410_VA_UART + 0x4000 )
+#define S3C2410_VA_UART2      (S3C2410_VA_UART + 0x8000 )
+
+#define S3C2410_PA_UART0      (S3C2410_PA_UART)
+#define S3C2410_PA_UART1      (S3C2410_PA_UART + 0x4000 )
+#define S3C2410_PA_UART2      (S3C2410_PA_UART + 0x8000 )
+
+#define S3C2410_URXH	  (0x24)
+#define S3C2410_UTXH	  (0x20)
+#define S3C2410_ULCON	  (0x00)
+#define S3C2410_UCON	  (0x04)
+#define S3C2410_UFCON	  (0x08)
+#define S3C2410_UMCON	  (0x0C)
+#define S3C2410_UBRDIV	  (0x28)
+#define S3C2410_UTRSTAT	  (0x10)
+#define S3C2410_UERSTAT	  (0x14)
+#define S3C2410_UFSTAT	  (0x18)
+#define S3C2410_UMSTAT	  (0x1C)
+
+#define S3C2410_LCON_CFGMASK	  ((0xF<<3)|(0x3))
+
+#define S3C2410_LCON_CS5	  (0x0)
+#define S3C2410_LCON_CS6	  (0x1)
+#define S3C2410_LCON_CS7	  (0x2)
+#define S3C2410_LCON_CS8	  (0x3)
+#define S3C2410_LCON_CSMASK	  (0x3)
+
+#define S3C2410_LCON_PNONE	  (0x0)
+#define S3C2410_LCON_PEVEN	  (0x5 << 3)
+#define S3C2410_LCON_PODD	  (0x4 << 3)
+#define S3C2410_LCON_PMASK	  (0x7 << 3)
+
+#define S3C2410_LCON_STOPB	  (1<<2)
+
+#define S3C2410_UCON_UCLK	  (1<<10)
+#define S3C2410_UCON_SBREAK	  (1<<4)
+
+#define S3C2410_UCON_TXILEVEL	  (1<<9)
+#define S3C2410_UCON_RXILEVEL	  (1<<8)
+#define S3C2410_UCON_TXIRQMODE	  (1<<2)
+#define S3C2410_UCON_RXIRQMODE	  (1<<0)
+#define S3C2410_UCON_RXFIFO_TOI	  (1<<7)
+
+#define S3C2410_UCON_DEFAULT	  (S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL \
+				   | S3C2410_UCON_TXIRQMODE | S3C2410_UCON_RXIRQMODE \
+				   | S3C2410_UCON_RXFIFO_TOI)
+
+#define S3C2410_UFCON_FIFOMODE	  (1<<0)
+#define S3C2410_UFCON_TXTRIG0	  (0<<6)
+#define S3C2410_UFCON_RXTRIG8	  (1<<4)
+#define S3C2410_UFCON_RXTRIG12	  (2<<4)
+
+#define S3C2410_UFCON_RESETBOTH	  (3<<1)
+
+#define S3C2410_UFCON_DEFAULT	  (S3C2410_UFCON_FIFOMODE | S3C2410_UFCON_TXTRIG0 \
+				  | S3C2410_UFCON_RXTRIG8 )
+
+#define S3C2410_UFSTAT_TXFULL	  (1<<9)
+#define S3C2410_UFSTAT_RXFULL	  (1<<8)
+#define S3C2410_UFSTAT_TXMASK	  (15<<4)
+#define S3C2410_UFSTAT_TXSHIFT	  (4)
+#define S3C2410_UFSTAT_RXMASK	  (15<<0)
+#define S3C2410_UFSTAT_RXSHIFT	  (0)
+
+#define S3C2410_UTRSTAT_TXFE	  (1<<1)
+#define S3C2410_UTRSTAT_RXDR	  (1<<0)
+
+#define S3C2410_UERSTAT_OVERRUN	  (1<<0)
+#define S3C2410_UERSTAT_FRAME	  (1<<2)
+#define S3C2410_UERSTAT_ANY	  (S3C2410_UERSTAT_OVERRUN | S3C2410_UERSTAT_FRAME)
+
+/* fifo size information */
+
+#define S3C2410_UFCON_RXC(fcon)	  (((fcon) & S3C2410_UFSTAT_RXMASK) >> S3C2410_UFSTAT_RXSHIFT)
+#define S3C2410_UFCON_TXC(fcon)	  (((fcon) & S3C2410_UFSTAT_TXMASK) >> S3C2410_UFSTAT_TXSHIFT)
+
+#define S3C2410_UMSTAT_CTS	  (1<<0)
+#define S3C2410_UMSTAT_DeltaCTS	  (1<<2)
+
+#ifndef __ASSEMBLY__
+/* configuration structure for per-machine configurations for the
+ * serial port
+ *
+ * the pointer is setup by the machine specific initialisation from the
+ * arch/arm/mach-s3c2410/ directory.
+*/
+
+struct s3c2410_uartcfg {
+	unsigned char	   hwport;	 /* hardware port number */
+	unsigned char	   unused;
+	unsigned short	   flags;
+
+	unsigned long	  *clock;	 /* pointer to clock rate */
+
+	unsigned long	   ucon;	 /* value of ucon for port */
+	unsigned long	   ulcon;	 /* value of ulcon for port */
+	unsigned long	   ufcon;	 /* value of ufcon for port */
+};
+
+extern struct s3c2410_uartcfg *s3c2410_uartcfgs;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+
diff -Nru a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/arch-s3c2410/regs-timer.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-timer.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,108 @@
+/* linux/include/asm/arch-s3c2410/regs-timer.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Timer configuration
+ *
+ *  Changelog:
+ *    05-06-2003     BJD     Created file
+ *    26-06-2003     BJD     Added more timer definitions to mux / control
+ *    12-03-2004     BJD     Updated include protection
+*/
+
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
+
+#define S3C2410_TIMERREG(x) (S3C2410_VA_TIMER + (x))
+#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+
+#define S3C2410_TCFG0	      S3C2410_TIMERREG(0x00)
+#define S3C2410_TCFG1	      S3C2410_TIMERREG(0x04)
+#define S3C2410_TCON	      S3C2410_TIMERREG(0x08)
+
+#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
+#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
+#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
+
+#define S3C2410_TCFG1_MUX4_DIV2	  (0<<16)
+#define S3C2410_TCFG1_MUX4_DIV4	  (1<<16)
+#define S3C2410_TCFG1_MUX4_DIV8	  (2<<16)
+#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
+#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
+#define S3C2410_TCFG1_MUX4_MASK	  (15<<16)
+
+#define S3C2410_TCFG1_MUX3_DIV2	  (0<<12)
+#define S3C2410_TCFG1_MUX3_DIV4	  (1<<12)
+#define S3C2410_TCFG1_MUX3_DIV8	  (2<<12)
+#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
+#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
+#define S3C2410_TCFG1_MUX3_MASK	  (15<<12)
+
+
+#define S3C2410_TCFG1_MUX2_DIV2	  (0<<8)
+#define S3C2410_TCFG1_MUX2_DIV4	  (1<<8)
+#define S3C2410_TCFG1_MUX2_DIV8	  (2<<8)
+#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
+#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
+#define S3C2410_TCFG1_MUX2_MASK	  (15<<8)
+
+
+#define S3C2410_TCFG1_MUX1_DIV2	  (0<<4)
+#define S3C2410_TCFG1_MUX1_DIV4	  (1<<4)
+#define S3C2410_TCFG1_MUX1_DIV8	  (2<<4)
+#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
+#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
+#define S3C2410_TCFG1_MUX1_MASK	  (15<<4)
+
+#define S3C2410_TCFG1_MUX0_DIV2	  (0<<0)
+#define S3C2410_TCFG1_MUX0_DIV4	  (1<<0)
+#define S3C2410_TCFG1_MUX0_DIV8	  (2<<0)
+#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
+#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
+#define S3C2410_TCFG1_MUX0_MASK	  (15<<0)
+
+/* for each timer, we have an count buffer, an compare buffer and
+ * an observation buffer
+*/
+
+/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
+
+#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+
+#define S3C2410_TCON_T4RELOAD	  (1<<22)
+#define S3C2410_TCON_T4MANUALUPD  (1<<21)
+#define S3C2410_TCON_T4START	  (1<<20)
+
+#define S3C2410_TCON_T3RELOAD	  (1<<19)
+#define S3C2410_TCON_T3INVERT	  (1<<18)
+#define S3C2410_TCON_T3MANUALUPD  (1<<17)
+#define S3C2410_TCON_T3START	  (1<<16)
+
+#define S3C2410_TCON_T2RELOAD	  (1<<15)
+#define S3C2410_TCON_T2INVERT	  (1<<14)
+#define S3C2410_TCON_T2MANUALUPD  (1<<13)
+#define S3C2410_TCON_T2START	  (1<<12)
+
+#define S3C2410_TCON_T1RELOAD	  (1<<11)
+#define S3C2410_TCON_T1INVERT	  (1<<10)
+#define S3C2410_TCON_T1MANUALUPD  (1<<9)
+#define S3C2410_TCON_T1START	  (1<<8)
+
+#define S3C2410_TCON_T0DEADZONE	  (1<<4)
+#define S3C2410_TCON_T0RELOAD	  (1<<3)
+#define S3C2410_TCON_T0INVERT	  (1<<2)
+#define S3C2410_TCON_T0MANUALUPD  (1<<1)
+#define S3C2410_TCON_T0START	  (1<<0)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
+
+
+
diff -Nru a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/regs-watchdog.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,44 @@
+/* linux/include/asm/arch-s3c2410/regs0watchdog.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Watchdog timer control
+ *
+ *  Changelog:
+ *    21-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+*/
+
+
+#ifndef __ASM_ARCH_REGS_WATCHDOG_H
+#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
+
+#define S3C2410_WDOGREG(x) ((x) + S3C2410_VA_WATCHDOG)
+
+#define S3C2410_WTCON	   S3C2410_WDOGREG(0x00)
+#define S3C2410_WTDAT	   S3C2410_WDOGREG(0x04)
+#define S3C2410_WTCNT	   S3C2410_WDOGREG(0x08)
+
+/* the watchdog can either generate a reset pulse, or an
+ * interrupt.
+ */
+
+#define S3C2410_WTCON_RSTEN   (0x01)
+#define S3C2410_WTCON_INTEN   (1<<2)
+#define S3C2410_WTCON_ENABLE  (1<<5)
+
+#define S3C2410_WTCON_DIV16   (0<<3)
+#define S3C2410_WTCON_DIV32   (1<<3)
+#define S3C2410_WTCON_DIV64   (2<<3)
+#define S3C2410_WTCON_DIV128  (3<<3)
+
+#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
+
+#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
+
+
diff -Nru a/include/asm-arm/arch-s3c2410/serial.h b/include/asm-arm/arch-s3c2410/serial.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/serial.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,28 @@
+/* linux/include/asm-arm/arch-s3c2410/serial.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - serial port definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  03-Sep-2003 BJD  Created file
+ *  19-Mar-2004 BJD  Removed serial port definitions, inserted elsewhere
+*/
+
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+/* Standard COM flags */
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#define BASE_BAUD ( 1843200 / 16 )
+
+#define STD_SERIAL_PORT_DEFNS
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif /* __ASM_ARCH_SERIAL_H */
diff -Nru a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/system.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,84 @@
+/* linux/include/asm-arm/arch-s3c2410/system.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System function defines and includes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  12-May-2003 BJD  Created file
+ *  14-May-2003 BJD  Removed idle to aid debugging
+ *  12-Jun-2003 BJD  Added reset via watchdog
+ *  04-Sep-2003 BJD  Moved to v2.6
+ */
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+#include <asm/arch/map.h>
+
+#include <asm/arch/regs-watchdog.h>
+#include <asm/arch/regs-clock.h>
+
+extern void printascii(const char *);
+
+void
+arch_idle(void)
+{
+	//unsigned long reg = S3C2410_CLKCON;
+
+	//printascii("arch_idle:\n");
+
+	/* idle the system by using the idle mode which will wait for an
+	 * interrupt to happen before restarting the system.
+	 */
+
+	/* going into idle state upsets the jtag, so don't do it
+	 * at the moment */
+
+#if 0
+	__raw_writel(__raw_readl(reg) | (1<<2), reg);
+
+	/* the samsung port seems to do a loop and then unset idle.. */
+	for (i = 0; i < 50; i++) {
+		tmp = __raw_readl(reg); /* ensure loop not optimised out */
+	}
+
+	//printascii("arch_idle: done\n");
+
+	__raw_writel(__raw_readl(reg) & ~(1<<2), reg);
+#endif
+}
+
+
+static void
+arch_reset(char mode)
+{
+	if (mode == 's') {
+		cpu_reset(0);
+	}
+
+	printk("arch_reset: attempting watchdog reset\n");
+
+	__raw_writel(0, S3C2410_WTCON);	  /* disable watchdog, to be safe  */
+
+	/* put initial values into count and data */
+	__raw_writel(0x100, S3C2410_WTCNT);
+	__raw_writel(0x100, S3C2410_WTDAT);
+
+	/* set the watchdog to go and reset... */
+	__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+		     S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+
+	/* wait for reset to assert... */
+	mdelay(5000);
+
+	panic("Watchdog reset failed to assert reset\n");
+
+	/* we'll take a jump through zero as a poor second */
+	cpu_reset(0);
+}
diff -Nru a/include/asm-arm/arch-s3c2410/time.h b/include/asm-arm/arch-s3c2410/time.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/time.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,173 @@
+/* linux/include/asm-arm/arch-s3c2410/time.h
+ *
+ *  Copyright (C) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *    Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <asm/system.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include <asm/io.h>
+#include <asm/arch/map.h>
+#include <asm/arch/regs-timer.h>
+
+extern unsigned long (*gettimeoffset)(void);
+
+static unsigned long timer_startval;
+static unsigned long timer_ticks_usec;
+
+#ifdef CONFIG_S3C2410_RTC
+extern void s3c2410_rtc_check();
+#endif
+
+/* with an 12MHz clock, we get 12 ticks per-usec
+ */
+
+
+/***
+ * Returns microsecond  since last clock interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ * IRQs are disabled before entering here from do_gettimeofday()
+ */
+static unsigned long s3c2410_gettimeoffset (void)
+{
+	unsigned long tdone;
+	unsigned long usec;
+
+	/* work out how many ticks have gone since last timer interrupt */
+
+	tdone = timer_startval - __raw_readl(S3C2410_TCNTO(4));
+
+	/* currently, tcnt is in 12MHz units, but this may change
+	 * for non-bast machines...
+	 */
+
+	usec = tdone / timer_ticks_usec;
+
+	return usec;
+}
+
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+s3c2410_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	do_leds();
+	do_timer(regs);
+
+	do_set_rtc();
+	//s3c2410_rtc_check();
+	do_profile(regs);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+
+/* currently we only use timer4, as it is the only timer which has no
+ * other function that can be exploited externally
+*/
+
+void __init time_init (void)
+{
+	unsigned long tcon;
+	unsigned long tcnt;
+	unsigned long tcfg1;
+	unsigned long tcfg0;
+
+	gettimeoffset = s3c2410_gettimeoffset;
+	timer_irq.handler = s3c2410_timer_interrupt;
+
+	tcnt = 0xffff;  /* default value for tcnt */
+
+	/* read the current timer configuration bits */
+
+	tcon = __raw_readl(S3C2410_TCON);
+	tcfg1 = __raw_readl(S3C2410_TCFG1);
+	tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+	/* configure the system for whichever machine is in use */
+
+	if (machine_is_bast() || machine_is_vr1000()) {
+		timer_ticks_usec = 12;	      /* timer is at 12MHz */
+		tcnt = (timer_ticks_usec * (1000*1000)) / HZ;
+	}
+
+	/* for the h1940, we use the pclk from the core to generate
+	 * the timer values. since 67.5MHz is not a value we can directly
+	 * generate the timer value from, we need to pre-scale and
+	 * divied before using it.
+	 *
+	 * overall divsior to get 200Hz is 337500
+	 *   we can fit tcnt if we pre-scale by 6, producing a tick rate
+	 *   of 11.25MHz, and a tcnt of 56250.
+	 */
+
+	if (machine_is_h1940()) {
+		timer_ticks_usec = s3c2410_pclk / (1000*1000);
+		timer_ticks_usec /= 6;
+
+		tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
+		tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
+
+		tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+		tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
+
+		tcnt = (s3c2410_pclk / 6) / HZ;
+	}
+
+
+	printk("setup_timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx\n",
+	       tcon, tcnt, tcfg0, tcfg1);
+
+	/* check to see if timer is within 16bit range... */
+	if (tcnt > 0xffff) {
+		panic("setup_timer: HZ is too small, cannot configure timer!");
+		return;
+	}
+
+	__raw_writel(tcfg1, S3C2410_TCFG1);
+	__raw_writel(tcfg0, S3C2410_TCFG0);
+
+	timer_startval = tcnt;
+	__raw_writel(tcnt, S3C2410_TCNTB(4));
+
+	/* ensure timer is stopped... */
+
+	tcon &= ~(7<<20);
+	tcon |= S3C2410_TCON_T4RELOAD;
+	tcon |= S3C2410_TCON_T4MANUALUPD;
+
+	__raw_writel(tcon, S3C2410_TCON);
+	__raw_writel(tcnt, S3C2410_TCNTB(4));
+	__raw_writel(tcnt, S3C2410_TCMPB(4));
+
+	setup_irq(IRQ_TIMER4, &timer_irq);
+
+	/* start the timer running */
+	tcon |= S3C2410_TCON_T4START;
+	tcon &= ~S3C2410_TCON_T4MANUALUPD;
+	__raw_writel(tcon, S3C2410_TCON);
+}
+
+
+
diff -Nru a/include/asm-arm/arch-s3c2410/timex.h b/include/asm-arm/arch-s3c2410/timex.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/timex.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,33 @@
+/* linux/include/asm-arm/arch-s3c2410/timex.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  02-Sep-2003 BJD  Created file
+ *  05-Jan-2004 BJD  Updated for Linux 2.6.0
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#if 0
+/* todo - this does not seem to work with 2.6.0 -> division by zero
+ * in header files
+ */
+extern int s3c2410_clock_tick_rate;
+
+#define CLOCK_TICK_RATE (s3c2410_clock_tick_rate)
+#endif
+
+/* currently, the BAST uses 24MHz as a base clock rate */
+#define CLOCK_TICK_RATE 24000000
+
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff -Nru a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/uncompress.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,110 @@
+/* linux/include/asm-arm/arch-s3c2410/uncompress.h
+ *
+ * (c) 2003 Simtec Electronics
+ *    Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  22-May-2003 BJD  Created
+ *  08-Sep-2003 BJD  Moved to linux v2.6
+ *  12-Mar-2004 BJD  Updated header protection
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+/* defines for UART registers */
+#include "asm/arch/regs-serial.h"
+
+#include <asm/arch/map.h>
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX	 (14)
+
+#if 1
+#define uart_base S3C2410_PA_UART
+#else
+static unsigned int uart_base = S3C2410_PA_UART;
+#endif
+
+static __inline__ void
+uart_wr(unsigned int reg, unsigned int val)
+{
+	volatile unsigned int *ptr;
+
+	ptr = (volatile unsigned int *)(reg + uart_base);
+	*ptr = val;
+}
+
+static __inline__ unsigned int
+uart_rd(unsigned int reg)
+{
+	volatile unsigned int *ptr;
+
+	ptr = (volatile unsigned int *)(reg + uart_base);
+	return *ptr;
+}
+
+
+/* currently we do not need the watchdog... */
+#define arch_decomp_wdog()
+
+
+static void error(char *err);
+
+static void
+arch_decomp_setup(void)
+{
+	/* we may need to setup the uart(s) here if we are not running
+	 * on an BAST... the BAST will have left the uarts configured
+	 * after calling linux.
+	 */
+}
+
+/* we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+*/
+
+static void
+putc(char ch)
+{
+	if (ch == '\n')
+		putc('\r');    /* expand newline to \r\n */
+
+	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+		int level;
+
+		while (1) {
+			level = uart_rd(S3C2410_UFSTAT);
+			level &= S3C2410_UFSTAT_TXMASK;
+			level >>= S3C2410_UFSTAT_TXSHIFT;
+
+			if (level < FIFO_MAX)
+				break;
+		}
+
+	} else {
+		/* not using fifos */
+
+		while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE) != S3C2410_UTRSTAT_TXFE);
+	}
+
+	/* write byte to transmission register */
+	uart_wr(S3C2410_UTXH, ch);
+}
+
+static void
+puts(const char *ptr)
+{
+	for (; *ptr != '\0'; ptr++) {
+		putc(*ptr);
+	}
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff -Nru a/include/asm-arm/arch-s3c2410/vmalloc.h b/include/asm-arm/arch-s3c2410/vmalloc.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-s3c2410/vmalloc.h
+ *
+ * from linux/include/asm-arm/arch-iop3xx/vmalloc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *		      http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 vmalloc definition
+ *
+ *  Changelog:
+ *    12-Mar-2004 BJD	Fixed header, added include protection
+ *    12=Mar-2004 BJD	Fixed VMALLOC_END definitions
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END	  (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff -Nru a/include/asm-arm/arch-s3c2410/vr1000-cpld.h b/include/asm-arm/arch-s3c2410/vr1000-cpld.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/vr1000-cpld.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,22 @@
+/* linux/include/asm-arm/arch-s3c2410/vr1000-cpld.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * VR1000 - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  25-May-2003 BJD  Created file, added CTRL1 registers
+ *  19-Mar-2004 BJD  Added VR1000 CPLD definitions
+*/
+
+#ifndef __ASM_ARCH_VR1000CPLD_H
+#define __ASM_ARCH_VR1000CPLD_H
+
+#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
+
+#endif /* __ASM_ARCH_VR1000CPLD_H */
diff -Nru a/include/asm-arm/arch-s3c2410/vr1000-irq.h b/include/asm-arm/arch-s3c2410/vr1000-irq.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/vr1000-irq.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,30 @@
+/* linux/include/asm-arm/arch-s3c2410/vr1000-irq.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine VR1000 - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version
+ *  19-Mar-2004 BJD  Updates for VR1000
+ */
+
+#ifndef __ASM_ARCH_VR1000IRQ_H
+#define __ASM_ARCH_VR1000IRQ_H
+
+/* irq numbers to onboard peripherals */
+
+#define IRQ_USBOC	     IRQ_EINT19
+#define IRQ_IDE0	     IRQ_EINT16
+#define IRQ_IDE1	     IRQ_EINT17
+#define IRQ_VR1000_SERIAL    IRQ_EINT12
+#define IRQ_VR1000_DM9000A   IRQ_EINT10
+#define IRQ_VR1000_DM9000N   IRQ_EINT9
+#define IRQ_SMALERT	     IRQ_EINT8
+
+#endif /* __ASM_ARCH_VR1000IRQ_H */
diff -Nru a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-arm/arch-s3c2410/vr1000-map.h	Thu Apr  8 14:54:32 2004
@@ -0,0 +1,112 @@
+/* linux/include/asm-arm/arch-s3c2410/vr1000-map.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine VR1000 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version, split specifics from arch/map.h
+ *  12-Mar-2004 BJD  Fixed header include protection
+ *  19-Mar-2004 BJD  Copied to VR1000 machine headers.
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#ifndef __ASM_ARCH_VR1000MAP_H
+#define __ASM_ARCH_VR1000MAP_H
+
+#include <asm/arch/bast-map.h>
+
+#define VR1000_IOADDR(x) BAST_IOADDR(x)
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define VR1000_VA_CTRL1	    VR1000_IOADDR(0x00000000)	 /* 0x01300000 */
+#define VR1000_PA_CTRL1	    (S3C2410_CS5 | 0x7800000)
+
+#define VR1000_VA_CTRL2	    VR1000_IOADDR(0x00100000)	 /* 0x01400000 */
+#define VR1000_PA_CTRL2	    (S3C2410_CS1 | 0x6000000)
+
+#define VR1000_VA_CTRL3	    VR1000_IOADDR(0x00200000)	 /* 0x01500000 */
+#define VR1000_PA_CTRL3	    (S3C2410_CS1 | 0x6800000)
+
+#define VR1000_VA_CTRL4	    VR1000_IOADDR(0x00300000)	 /* 0x01600000 */
+#define VR1000_PA_CTRL4	    (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
+
+#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
+
+#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
+
+/* 0xE0000000 contains the IO space that is split by speed and
+ * wether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
+ * 0x02600000 to 0x02700000 1MB
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define VR1000_VA_MULTISPACE (0xE0000000)
+
+#define VR1000_VA_ISAIO		   (VR1000_VA_MULTISPACE + 0x00000000)
+#define VR1000_VA_ISAMEM	   (VR1000_VA_MULTISPACE + 0x01000000)
+#define VR1000_VA_IDEPRI	   (VR1000_VA_MULTISPACE + 0x02000000)
+#define VR1000_VA_IDEPRIAUX	   (VR1000_VA_MULTISPACE + 0x02100000)
+#define VR1000_VA_IDESEC	   (VR1000_VA_MULTISPACE + 0x02200000)
+#define VR1000_VA_IDESECAUX	   (VR1000_VA_MULTISPACE + 0x02300000)
+#define VR1000_VA_ASIXNET	   (VR1000_VA_MULTISPACE + 0x02400000)
+#define VR1000_VA_DM9000	   (VR1000_VA_MULTISPACE + 0x02500000)
+#define VR1000_VA_SUPERIO	   (VR1000_VA_MULTISPACE + 0x02600000)
+
+
+/* physical offset addresses for the peripherals */
+
+#define VR1000_PA_IDEPRI	   (0x02000000)
+#define VR1000_PA_IDEPRIAUX	   (0x02800000)
+#define VR1000_PA_IDESEC	   (0x03000000)
+#define VR1000_PA_IDESECAUX	   (0x03800000)
+#define VR1000_PA_DM9000	   (0x05000000)
+
+#define VR1000_PA_SERIAL	   (0x11800000)
+
+/* some configurations for the peripherals */
+
+#define VR1000_DM9000_CS	 VR1000_VAM_CS4
+
+#endif /* __ASM_ARCH_VR1000MAP_H */
diff -Nru a/include/asm-arm/arch-sa1100/vmalloc.h b/include/asm-arm/arch-sa1100/vmalloc.h
--- a/include/asm-arm/arch-sa1100/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-sa1100/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (0xe8000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-shark/vmalloc.h b/include/asm-arm/arch-shark/vmalloc.h
--- a/include/asm-arm/arch-shark/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-shark/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/arch-tbox/vmalloc.h b/include/asm-arm/arch-tbox/vmalloc.h
--- a/include/asm-arm/arch-tbox/vmalloc.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/arch-tbox/vmalloc.h	Thu Apr  8 14:54:32 2004
@@ -13,6 +13,3 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
-
-#define MODULE_START	(PAGE_OFFSET - 16*1048576)
-#define MODULE_END	(PAGE_OFFSET)
diff -Nru a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
--- a/include/asm-arm/cacheflush.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/cacheflush.h	Thu Apr  8 14:54:32 2004
@@ -41,7 +41,7 @@
 #endif
 
 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
-    defined(CONFIG_CPU_ARM1020)
+    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
 # define MULTI_CACHE 1
 #endif
 
diff -Nru a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
--- a/include/asm-arm/ecard.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/ecard.h	Thu Apr  8 14:54:32 2004
@@ -208,7 +208,13 @@
 /*
  * Obtain the address of a card
  */
-extern unsigned int ecard_address (struct expansion_card *ec, card_type_t card_type, card_speed_t speed);
+extern __deprecated unsigned int ecard_address (struct expansion_card *ec, card_type_t card_type, card_speed_t speed);
+
+/*
+ * Request and release ecard resources
+ */
+extern int ecard_request_resources(struct expansion_card *ec);
+extern void ecard_release_resources(struct expansion_card *ec);
 
 #ifdef ECARD_C
 /* Definitions internal to ecard.c - for it's use only!!
diff -Nru a/include/asm-arm/memory.h b/include/asm-arm/memory.h
--- a/include/asm-arm/memory.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/memory.h	Thu Apr  8 14:54:32 2004
@@ -15,6 +15,17 @@
 #include <linux/config.h>
 #include <asm/arch/memory.h>
 
+/*
+ * The module space lives between the addresses given by TASK_SIZE
+ * and PAGE_OFFSET - it must be within 32MB of the kernel text.
+ */
+#define MODULE_END	(PAGE_OFFSET)
+#define MODULE_START	(MODULE_END - 16*1048576)
+
+#if TASK_SIZE > MODULE_START
+#error Top of user space clashes with start of module space
+#endif
+
 #ifndef __ASSEMBLY__
 
 /*
diff -Nru a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
--- a/include/asm-arm/proc-fns.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/proc-fns.h	Thu Apr  8 14:54:32 2004
@@ -66,6 +66,14 @@
 #   define CPU_NAME cpu_arm922
 #  endif
 # endif
+# ifdef CONFIG_CPU_ARM925T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm925
+#  endif
+# endif
 # ifdef CONFIG_CPU_ARM926T
 #  ifdef CPU_NAME
 #   undef  MULTI_CPU
diff -Nru a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
--- a/include/asm-arm/thread_info.h	Thu Apr  8 14:54:32 2004
+++ b/include/asm-arm/thread_info.h	Thu Apr  8 14:54:32 2004
@@ -108,8 +108,8 @@
 #define TI_CPU		20
 #define TI_CPU_DOMAIN	24
 #define TI_CPU_SAVE	28
-#define TI_USED_MATH	76
-#define TI_FPSTATE	(TI_USED_MATH+16)
+#define TI_USED_CP	76
+#define TI_FPSTATE	(TI_USED_CP+16)
 
 #endif