From: Michael Hunold <hunold@linuxtv.org>

- saa7146: fix timeout bug on AMD64 in saa7146_wait_for_debi_done()

- saa7146: release resources for video overlay properly, don't
  (incorrectly) rely on VIDIOC_OVERLAY(0)


---

 25-akpm/drivers/media/common/saa7146_core.c  |    6 +++---
 25-akpm/drivers/media/common/saa7146_video.c |    1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff -puN drivers/media/common/saa7146_core.c~dvb-02-update-saa7146-core drivers/media/common/saa7146_core.c
--- 25/drivers/media/common/saa7146_core.c~dvb-02-update-saa7146-core	Mon Feb 23 14:05:06 2004
+++ 25-akpm/drivers/media/common/saa7146_core.c	Mon Feb 23 14:05:06 2004
@@ -69,14 +69,14 @@ void saa7146_set_gpio(struct saa7146_dev
 /* This DEBI code is based on the saa7146 Stradis driver by Nathan Laredo */
 int saa7146_wait_for_debi_done(struct saa7146_dev *dev)
 {
-	int start;
+	unsigned long start;
 
 	/* wait for registers to be programmed */
 	start = jiffies;
 	while (1) {
                 if (saa7146_read(dev, MC2) & 2)
                         break;
-		if (jiffies-start > HZ/20) {
+		if (time_after(jiffies, start + HZ/20)) {
 			DEB_S(("timed out while waiting for registers getting programmed\n"));
 			return -ETIMEDOUT;
 		}
@@ -88,7 +88,7 @@ int saa7146_wait_for_debi_done(struct sa
 		if (!(saa7146_read(dev, PSR) & SPCI_DEBI_S))
 			break;
 		saa7146_read(dev, MC2);
-		if (jiffies-start > HZ/4) {
+		if (time_after(jiffies, start + HZ/4)) {
 			DEB_S(("timed out while waiting for transfer completion\n"));
 			return -ETIMEDOUT;
 		}
diff -puN drivers/media/common/saa7146_video.c~dvb-02-update-saa7146-core drivers/media/common/saa7146_video.c
--- 25/drivers/media/common/saa7146_video.c~dvb-02-update-saa7146-core	Mon Feb 23 14:05:06 2004
+++ 25-akpm/drivers/media/common/saa7146_video.c	Mon Feb 23 14:05:06 2004
@@ -1413,6 +1413,7 @@ static void video_close(struct saa7146_d
 			spin_lock_irqsave(&dev->slock,flags);
 			saa7146_stop_preview(fh);
 			spin_unlock_irqrestore(&dev->slock,flags);
+			saa7146_res_free(fh, RESOURCE_DMA1_HPS|RESOURCE_DMA2_CLP);
 		}
 	}
 	

_