From: Andi Kleen <ak@suse.de>,
From Suresh.B.Siddha
Fix another bug caused by the recent IA32e merge. The full L1 cache size
padding of the GDT didn't work with smaller cache line sizes. Just revert
that.
I must admit I still don't understand why it didn't work, but it's better
to have a working system for now.
---
25-akpm/arch/x86_64/kernel/head.S | 2 +-
25-akpm/include/asm-x86_64/segment.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff -puN arch/x86_64/kernel/head.S~ia32e-GDT-fix arch/x86_64/kernel/head.S
--- 25/arch/x86_64/kernel/head.S~ia32e-GDT-fix Thu Feb 19 14:32:29 2004
+++ 25-akpm/arch/x86_64/kernel/head.S Thu Feb 19 14:32:29 2004
@@ -358,7 +358,7 @@ gdt_end:
/* asm/segment.h:GDT_ENTRIES must match this */
/* This should be a multiple of the cache line size */
/* GDTs of other CPUs: */
- .fill (L1_CACHE_BYTES * NR_CPUS) - (gdt_end - cpu_gdt_table)
+ .fill (GDT_SIZE * NR_CPUS) - (gdt_end - cpu_gdt_table)
.align L1_CACHE_BYTES
ENTRY(idt_table)
diff -puN include/asm-x86_64/segment.h~ia32e-GDT-fix include/asm-x86_64/segment.h
--- 25/include/asm-x86_64/segment.h~ia32e-GDT-fix Thu Feb 19 14:32:29 2004
+++ 25-akpm/include/asm-x86_64/segment.h Thu Feb 19 14:32:29 2004
@@ -40,7 +40,7 @@
#define FS_TLS_SEL ((GDT_ENTRY_TLS_MIN+FS_TLS)*8 + 3)
#define IDT_ENTRIES 256
-#define GDT_ENTRIES (L1_CACHE_BYTES / 8)
+#define GDT_ENTRIES 16
#define GDT_SIZE (GDT_ENTRIES * 8)
#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
_