From: Kumar Gala <kumar.gala@freescale.com> We run into problems if we blindly enable L2 prefetching without checking that the L2 cache is actually enabled. Additionaly, if we disable the L2 cache we need to ensure that we disable L2 prefetching. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> --- arch/ppc/kernel/cpu_setup_6xx.S | 5 ++++- arch/ppc/kernel/l2cr.S | 29 +++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff -puN arch/ppc/kernel/cpu_setup_6xx.S~ppc32-l2-cache-prefetch-fixes-on-745x arch/ppc/kernel/cpu_setup_6xx.S --- devel/arch/ppc/kernel/cpu_setup_6xx.S~ppc32-l2-cache-prefetch-fixes-on-745x 2005-08-30 21:59:01.000000000 -0700 +++ devel-akpm/arch/ppc/kernel/cpu_setup_6xx.S 2005-08-30 21:59:01.000000000 -0700 @@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) sync isync - /* Enable L2 HW prefetch + /* Enable L2 HW prefetch, if L2 is enabled */ + mfspr r3,SPRN_L2CR + andis. r3,r3,L2CR_L2E@h + beqlr mfspr r3,SPRN_MSSCR0 ori r3,r3,3 sync diff -puN arch/ppc/kernel/l2cr.S~ppc32-l2-cache-prefetch-fixes-on-745x arch/ppc/kernel/l2cr.S --- devel/arch/ppc/kernel/l2cr.S~ppc32-l2-cache-prefetch-fixes-on-745x 2005-08-30 21:59:01.000000000 -0700 +++ devel-akpm/arch/ppc/kernel/l2cr.S 2005-08-30 21:59:01.000000000 -0700 @@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) The bit moved on the 7450..... ****/ +BEGIN_FTR_SECTION + /* Disable L2 prefetch on some 745x and try to ensure + * L2 prefetch engines are idle. As explained by errata + * text, we can't be sure they are, we just hope very hard + * that well be enough (sic !). At least I noticed Apple + * doesn't even bother doing the dcbf's here... + */ + mfspr r4,SPRN_MSSCR0 + rlwinm r4,r4,0,0,29 + sync + mtspr SPRN_MSSCR0,r4 + sync + isync + lis r4,KERNELBASE@h + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 +END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) + /* TODO: use HW flush assist when available */ lis r4,0x0002 @@ -231,6 +251,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) mtspr SPRN_L2CR,r3 sync + /* Enable L2 HW prefetch on 744x/745x */ +BEGIN_FTR_SECTION + mfspr r3,SPRN_MSSCR0 + ori r3,r3,3 + sync + mtspr SPRN_MSSCR0,r3 + sync + isync +END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) 4: /* Restore HID0[DPM] to whatever it was before */ _