From: Eugene Surovegin <ebs@ebshome.net>

Add dcr_base field to ocp_func_mal_data.  This is preparation step for the
new EMAC driver.

Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---

 arch/ppc/platforms/4xx/ibm405ep.c  |    1 +
 arch/ppc/platforms/4xx/ibm405gp.c  |    1 +
 arch/ppc/platforms/4xx/ibm405gpr.c |    1 +
 arch/ppc/platforms/4xx/ibm440ep.c  |    1 +
 arch/ppc/platforms/4xx/ibm440gp.c  |    1 +
 arch/ppc/platforms/4xx/ibm440gx.c  |    1 +
 arch/ppc/platforms/4xx/ibm440sp.c  |    1 +
 arch/ppc/platforms/4xx/ibmnp405h.c |    1 +
 include/asm-ppc/ibm_ocp.h          |    3 +++
 9 files changed, 11 insertions(+)

diff -puN arch/ppc/platforms/4xx/ibm405ep.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm405ep.c
--- devel/arch/ppc/platforms/4xx/ibm405ep.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm405ep.c	2005-08-30 21:58:42.000000000 -0700
@@ -33,6 +33,7 @@ static struct ocp_func_mal_data ibm405ep
 	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 10,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibm405gp.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm405gp.c
--- devel/arch/ppc/platforms/4xx/ibm405gp.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm405gp.c	2005-08-30 21:58:42.000000000 -0700
@@ -46,6 +46,7 @@ static struct ocp_func_mal_data ibm405gp
 	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 10,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibm405gpr.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm405gpr.c
--- devel/arch/ppc/platforms/4xx/ibm405gpr.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm405gpr.c	2005-08-30 21:58:42.000000000 -0700
@@ -42,6 +42,7 @@ static struct ocp_func_mal_data ibm405gp
 	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 10,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibm440ep.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm440ep.c
--- devel/arch/ppc/platforms/4xx/ibm440ep.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm440ep.c	2005-08-30 21:58:42.000000000 -0700
@@ -53,6 +53,7 @@ static struct ocp_func_mal_data ibm440ep
 	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 32,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibm440gp.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm440gp.c
--- devel/arch/ppc/platforms/4xx/ibm440gp.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm440gp.c	2005-08-30 21:58:42.000000000 -0700
@@ -56,6 +56,7 @@ static struct ocp_func_mal_data ibm440gp
 	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 32,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibm440gx.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm440gx.c
--- devel/arch/ppc/platforms/4xx/ibm440gx.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm440gx.c	2005-08-30 21:58:42.000000000 -0700
@@ -84,6 +84,7 @@ static struct ocp_func_mal_data ibm440gx
 	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 32,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibm440sp.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibm440sp.c
--- devel/arch/ppc/platforms/4xx/ibm440sp.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibm440sp.c	2005-08-30 21:58:42.000000000 -0700
@@ -43,6 +43,7 @@ static struct ocp_func_mal_data ibm440sp
 	.txde_irq	= 34,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 35,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 33,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN arch/ppc/platforms/4xx/ibmnp405h.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data arch/ppc/platforms/4xx/ibmnp405h.c
--- devel/arch/ppc/platforms/4xx/ibmnp405h.c~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ibmnp405h.c	2005-08-30 21:58:42.000000000 -0700
@@ -73,6 +73,7 @@ static struct ocp_func_mal_data ibmnp405
 	.txde_irq	= 46,		/* TX Descriptor Error IRQ */
 	.rxde_irq	= 47,		/* RX Descriptor Error IRQ */
 	.serr_irq	= 45,		/* MAL System Error IRQ    */
+	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
 };
 OCP_SYSFS_MAL_DATA()
 
diff -puN include/asm-ppc/ibm_ocp.h~ppc32-add-dcr_base-field-to-ocp_func_mal_data include/asm-ppc/ibm_ocp.h
--- devel/include/asm-ppc/ibm_ocp.h~ppc32-add-dcr_base-field-to-ocp_func_mal_data	2005-08-30 21:58:42.000000000 -0700
+++ devel-akpm/include/asm-ppc/ibm_ocp.h	2005-08-30 21:58:42.000000000 -0700
@@ -147,6 +147,7 @@ struct ocp_func_mal_data {
 	int	txde_irq;	/* TX Descriptor Error IRQ */
 	int	rxde_irq;	/* RX Descriptor Error IRQ */
 	int	serr_irq;	/* MAL System Error IRQ    */
+	int	dcr_base;	/* MALx_CFG DCR number   */
 };
 
 #define OCP_SYSFS_MAL_DATA()						\
@@ -157,6 +158,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_mal_data
 OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq)	\
 OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq)	\
 OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq)	\
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base)	\
 									\
 void ocp_show_mal_data(struct device *dev)				\
 {									\
@@ -167,6 +169,7 @@ void ocp_show_mal_data(struct device *de
 	device_create_file(dev, &dev_attr_mal_txde_irq);		\
 	device_create_file(dev, &dev_attr_mal_rxde_irq);		\
 	device_create_file(dev, &dev_attr_mal_serr_irq);		\
+	device_create_file(dev, &dev_attr_mal_dcr_base);		\
 }
 
 /*
_