From: "Andi Kleen" <ak@suse.de>
Were either outdated or misleading.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
include/asm-x86_64/tlbflush.h | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff -puN include/asm-x86_64/tlbflush.h~x86_64-fix-some-comments-in-tlbflushh include/asm-x86_64/tlbflush.h
--- devel/include/asm-x86_64/tlbflush.h~x86_64-fix-some-comments-in-tlbflushh 2005-07-27 12:36:21.000000000 -0700
+++ devel-akpm/include/asm-x86_64/tlbflush.h 2005-07-27 12:36:21.000000000 -0700
@@ -56,8 +56,9 @@ extern unsigned long pgkern_mask;
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
*
- * ..but the x86_64 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
*/
#ifndef CONFIG_SMP
@@ -115,7 +116,9 @@ static inline void flush_tlb_range(struc
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
- /* x86_64 does not keep any page table caches in TLB */
+ /* x86_64 does not keep any page table caches in a software TLB.
+ The CPUs do in their hardware TLBs, but they are handled
+ by the normal TLB flushing algorithms. */
}
#endif /* _X8664_TLBFLUSH_H */
_